PROFINET IRT Device Architecture & HW Scheduling Windows
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A PROFINET IRT device delivers motion-grade determinism by enforcing a hardware-timed cyclic schedule with bounded jitter, while keeping acyclic parameter/diagnostic traffic isolated so it cannot steal time from the IRT window.
The practical goal is simple: prove “missed=0” and jitter ≤ X with device-side counters, trace logs, and repeatable bring-up/production gates.
H2-1 · What is a PROFINET IRT Device (and what “IRT” really means)
A PROFINET IRT device is a deterministic Ethernet endpoint that runs a hardware-timed cyclic schedule and guarantees a bounded jitter for time-critical process data, while keeping acyclic parameter/diagnostic traffic running in parallel without disturbing the cycle.
Definition (engineer’s version)
- IRT is not “faster Ethernet”—it is more predictable Ethernet with a cycle that can be proven.
- The core promise is worst-case bounds: latency and jitter must stay within X (placeholder) across load, diagnostics, and configuration traffic.
- The device must keep time-critical cyclic data on a hardware-controlled path, and run acyclic traffic with isolation (rate-limits / queues / backpressure).
Determinism ladder (concept only): NRT = best-effort → RT = prioritized → IRT = time-windowed + bounded jitter
When an IRT device is needed
An IRT device becomes necessary when application performance depends on cycle-accurate timing, not just throughput.
- Motion / synchronization requires bounded packet delay variation (jitter ≤ X).
- Cyclic process data must keep its schedule even during parameter downloads, diagnostics, and alarms.
- A pass/fail statement must exist: “The device meets cycle timing under worst-case load” (verified by counters + traces + acceptance thresholds).
Device responsibilities (high level): fixed cycle boundary · IO image commit point · cyclic/acyclic isolation · observable timing health
When IRT is not required
- The system cares about average latency or throughput, but does not require a worst-case jitter bound.
- The control loop can tolerate timing variation through buffering, interpolation, or lower update rates.
- Diagnostics/parameter traffic can be delayed without affecting machine stability.
Scope guard: This page focuses on device-side determinism. PHY/EMC, TSN switching, and time-sync algorithms are handled in their dedicated pages.
H2-2 · System-level architecture of an IRT Device
The architecture goal is simple: keep cyclic process data on a hardware-timed fast path, and run acyclic parameter/diagnostic traffic on an isolated path with strict limits—so the cycle remains stable under worst-case conditions.
Building blocks (mapped to responsibilities)
Time core (defines the cycle boundary)
Cycle timer + schedule table sets the window timing. This becomes the reference for IO-image commit points and for any “late/early” detection.
Deterministic data plane (keeps jitter bounded)
HW scheduler + timestamp tap + DMA establish a fast path that avoids CPU timing noise. The timestamp location must be stable and consistent across variants.
IO-image handoff (prevents data tearing)
Dual-buffer IO image (A/B) provides an atomic “commit” at the cycle boundary. The application reads the last committed image, while the next cycle image is prepared in parallel.
Acyclic / diagnostics plane (stays parallel, stays contained)
Acyclic traffic uses separate queues, limits, and backpressure so that diagnostics, alarms, and parameter transfers never consume the cyclic window.
Control plane (config + observability)
CPU/RTOS handles configuration, diagnostics export, and non-critical tasks. The cyclic fast path should remain valid even under CPU load spikes.
Path A · Cyclic fast path (what must stay deterministic)
- RX → parse/classify → queue → gate(window) → TX is driven by hardware timing, not task scheduling.
- IO-image commit point is aligned to the cycle boundary (atomic swap), so every cycle uses a consistent snapshot.
- Timing health must be measurable: late/early counts, queue overflow, and cycle-skew indicators.
Path B · Acyclic + diagnostics (what must stay parallel)
- Acyclic traffic is useful and necessary, but must be treated as “contained load”.
- Isolation mechanisms: separate queues, rate limits, and explicit backpressure—so bursts do not shift the cyclic schedule.
- Failure mode to prevent: “parameter download causes cyclic jitter increase” (must be blocked by design).
Control plane · Configuration + observability (what proves it works)
- Configuration must be versioned and safe to apply: schedule table changes should not introduce transient cycle violations.
- Observability outputs: counters + event ring buffer (timestamped) + export path to field tools.
- Pass criteria must exist: “Under worst-case load, cycle jitter ≤ X, missed windows = 0, queue drops ≤ X.”
H2-1 · What is a PROFINET IRT Device (and what “IRT” really means)
A PROFINET IRT device is a deterministic Ethernet endpoint that runs a hardware-timed cyclic schedule and guarantees a bounded jitter for time-critical process data, while keeping acyclic parameter/diagnostic traffic running in parallel without disturbing the cycle.
Definition (engineer’s version)
- IRT is not “faster Ethernet”—it is more predictable Ethernet with a cycle that can be proven.
- The core promise is worst-case bounds: latency and jitter must stay within X (placeholder) across load, diagnostics, and configuration traffic.
- The device must keep time-critical cyclic data on a hardware-controlled path, and run acyclic traffic with isolation (rate-limits / queues / backpressure).
Determinism ladder (concept only): NRT = best-effort → RT = prioritized → IRT = time-windowed + bounded jitter
When an IRT device is needed
An IRT device becomes necessary when application performance depends on cycle-accurate timing, not just throughput.
- Motion / synchronization requires bounded packet delay variation (jitter ≤ X).
- Cyclic process data must keep its schedule even during parameter downloads, diagnostics, and alarms.
- A pass/fail statement must exist: “The device meets cycle timing under worst-case load” (verified by counters + traces + acceptance thresholds).
Device responsibilities (high level): fixed cycle boundary · IO image commit point · cyclic/acyclic isolation · observable timing health
When IRT is not required
- The system cares about average latency or throughput, but does not require a worst-case jitter bound.
- The control loop can tolerate timing variation through buffering, interpolation, or lower update rates.
- Diagnostics/parameter traffic can be delayed without affecting machine stability.
Scope guard: This page focuses on device-side determinism. PHY/EMC, TSN switching, and time-sync algorithms are handled in their dedicated pages.
H2-2 · System-level architecture of an IRT Device
The architecture goal is simple: keep cyclic process data on a hardware-timed fast path, and run acyclic parameter/diagnostic traffic on an isolated path with strict limits—so the cycle remains stable under worst-case conditions.
Building blocks (mapped to responsibilities)
Time core (defines the cycle boundary)
Cycle timer + schedule table sets the window timing. This becomes the reference for IO-image commit points and for any “late/early” detection.
Deterministic data plane (keeps jitter bounded)
HW scheduler + timestamp tap + DMA establish a fast path that avoids CPU timing noise. The timestamp location must be stable and consistent across variants.
IO-image handoff (prevents data tearing)
Dual-buffer IO image (A/B) provides an atomic “commit” at the cycle boundary. The application reads the last committed image, while the next cycle image is prepared in parallel.
Acyclic / diagnostics plane (stays parallel, stays contained)
Acyclic traffic uses separate queues, limits, and backpressure so that diagnostics, alarms, and parameter transfers never consume the cyclic window.
Control plane (config + observability)
CPU/RTOS handles configuration, diagnostics export, and non-critical tasks. The cyclic fast path should remain valid even under CPU load spikes.
Path A · Cyclic fast path (what must stay deterministic)
- RX → parse/classify → queue → gate(window) → TX is driven by hardware timing, not task scheduling.
- IO-image commit point is aligned to the cycle boundary (atomic swap), so every cycle uses a consistent snapshot.
- Timing health must be measurable: late/early counts, queue overflow, and cycle-skew indicators.
Path B · Acyclic + diagnostics (what must stay parallel)
- Acyclic traffic is useful and necessary, but must be treated as “contained load”.
- Isolation mechanisms: separate queues, rate limits, and explicit backpressure—so bursts do not shift the cyclic schedule.
- Failure mode to prevent: “parameter download causes cyclic jitter increase” (must be blocked by design).
Control plane · Configuration + observability (what proves it works)
- Configuration must be versioned and safe to apply: schedule table changes should not introduce transient cycle violations.
- Observability outputs: counters + event ring buffer (timestamped) + export path to field tools.
- Pass criteria must exist: “Under worst-case load, cycle jitter ≤ X, missed windows = 0, queue drops ≤ X.”
H2-3 · Cyclic schedule: phases, windows, and the hardware time base
An IRT cycle is a time contract: each phase occupies a defined window, and the device must keep cyclic traffic inside its window with a bounded timing error. The “colors” below are conceptual labels for constraints, not protocol trivia.
Concept: phases, windows, and why guard bands exist
Cycle
A repeating timeline with a cycle start boundary. The boundary must be measurable (counters + timestamps).
Windows (concept labels)
- IRT window: cyclic process data runs here (bounded jitter target ≤ X).
- RT window: prioritized real-time traffic (less strict than IRT).
- NRT window: best-effort traffic (variable latency/jitter).
Guard band
A protected margin that absorbs implementation and path uncertainty. Without guard bands, a “correct” configuration can still violate timing under load.
Key constraint: IRT determinism requires a hardware-timed boundary + a hard gate at the arbitration point + measurable late/early signals.
Engineering: implementing the schedule without timing drift
Time base + boundary
- A hardware timer defines the cycle boundary (compare match / phase ticks).
- A cycle counter and boundary timestamps are exported for correlation and audits.
- Cycle interrupt (if used) must not be the sole timing source—timing should remain correct under CPU load spikes.
Schedule engine: table-driven vs state-machine
Table-driven
- Schedule = phase list + compare times.
- Strong for versioning + safe updates at cycle boundaries.
State-machine
- Hard logic advances phases.
- Works for fixed schedules, but requires strong observability hooks.
Margins: guard band, TX advance, RX alignment
- Guard band absorbs uncertainty so the cyclic window remains uncontaminated.
- TX advance aligns the “effective on-wire time” to the window, not merely the enqueue time.
- RX alignment ensures classification, DMA, and IO-image commit do not cross the cycle boundary.
Acceptance placeholders: late/early ≤ X · guard band intrusion = 0 · missed window = 0
H2-4 · Parallel cyclic & acyclic channels: keeping determinism while staying debuggable
Acyclic traffic is essential for configuration, reads/writes, diagnostics, and alarms. The core design rule is to treat it as contained load—use isolation and shaping so it never shifts the cyclic schedule.
Problem: how acyclic traffic hurts cyclic determinism
- Parameter downloads can burst and compete for the same arbitration point.
- Diagnostics and alarm storms can saturate queues and DMA paths.
- Unbounded retries and timeouts can create feedback loops that amplify jitter.
Target outcome: cyclic window stays clean · acyclic remains usable · timing health stays observable
Mechanisms: isolation + shaping + backpressure + timeout policy
Queue isolation
Separate cyclic and acyclic queues. Cyclic traffic must pass a hard gate; acyclic traffic must never bypass it.
Shaping & limits
Use token/credit limits so acyclic bandwidth becomes a controlled budget: per-cycle frames ≤ X, or bandwidth ≤ X%.
Backpressure
When acyclic queues build up, apply explicit backpressure so congestion does not propagate into the cyclic arbitration point.
Timeout policy
Define fail-fast behavior for acyclic operations to avoid retry storms. Failures must be diagnosable and bounded in rate.
Prevention: stop “acyclic storm → cyclic jitter”
- Budget acyclic traffic: per-cycle or per-second caps (≤ X frames, ≤ X% bandwidth).
- Add storm guards: when alarm/diag rate exceeds X, aggregate, suppress, or downgrade acyclic service.
- Keep cyclic health observable: late/early counters, queue overflow, and “guard band intrusion” indicators.
- Ensure the arbitration point enforces a hard gate for cyclic traffic, not merely a priority hint.
Acceptance placeholders: jitter ≤ X · late/early ≤ X · missed window = 0 · acyclic cap enforced
H2-5 · IO data path: IO image, double buffering, and application handoff
Stable cyclic exchange requires a snapshot contract: network-facing updates are staged into an IO image, then atomically committed at the cycle boundary so the application never observes torn data.
Must-have structure (required for determinism)
IO image (shadow copy)
Process data is staged into a dedicated memory image to decouple hard cycle timing from soft task scheduling.
Double buffer (ping-pong)
Maintain Committed and Next buffers. All network writes go to Next; application reads Committed only.
Commit point at cycle boundary
- Swap pointers (or roles) via an atomic operation tied to the cycle timer boundary.
- Update Version and Commit timestamp for correlation and audits.
- Export late/missed commit counters to avoid silent timing debt.
Acceptance placeholders: tear = 0 · missed commit = 0 · late commit ≤ X · version monotonic
Optional optimizations (recommended for robustness)
Versioned reads (low-lock)
Use a read protocol: read Version → read data → re-read Version. If mismatch, retry. This detects mid-update hazards without heavy locks.
Dirty mask + partial commit
Track changed signals and commit only updated regions to reduce per-cycle copy and DMA pressure.
Late-data policy
- Inbound late: drop or defer to next cycle; keep last-good values for stability.
- Outbound late: hold last committed output; increment late-output counter.
- Define “late” with a measurable boundary rule (≤ X from window close).
Anti-patterns to avoid: shared live memory · CPU-driven commit without timestamps · no late/missed counters
H2-6 · Time sync dependency: what the device must assume and what it must measure
The device should treat synchronization as an interface contract: it consumes a sync event plus quality flags, disciplines a local timebase for cycle start alignment, and exports health metrics for deterministic operation and controlled holdover.
Inputs (consumed as signals, not algorithms)
- Sync event: a boundary/reference pulse used for cycle alignment.
- Quality flags: locked / holdover / degraded states that gate deterministic guarantees.
- Loss behavior: event missing, jittery input, or degraded quality must trigger explicit state transitions.
Scope guard: this section defines device-side interface requirements only
Outputs (what the device must make stable)
- Local clock discipline: produce a usable local timebase for cycle timing.
- Cycle start alignment: align the cycle boundary to the sync event within ≤ X.
- Timestamp tap point: keep a fixed, calibratable timestamping point for correlation.
- Observable signals: counters/state snapshots for audits and field debugging.
Acceptance placeholders: boundary alignment ≤ X · stable tap point · quality state exported
Health metrics (measurement + controlled holdover)
Offset metric
Define a measurement window and export offset values and thresholds (≤ X) for deterministic guarantees.
Jitter metric
Export jitter statistics (RMS/peak-to-peak placeholders) and detect boundary noise that can contaminate the cycle.
Holdover behavior
- Enter holdover when quality flags degrade or sync events are missing.
- Bound holdover duration to ≤ X, then raise alarms or degrade service.
- Tie degrade actions to measurable metrics (offset/jitter thresholds).
Degrade actions (examples): tighten acyclic budget · widen guard band · flag deterministic mode off
H2-7 · Latency & jitter budgeting for motion-grade performance
Motion-grade performance is proven by a repeatable loop: decompose the end-to-end path into measurable blocks, assign per-block budgets (Xi), and validate the worst-case with stable tap points and auditable counters.
End-to-end decomposition (define measurable tap points)
- Ingress (Rx tap) → parse/classify → queue/gate wait → DMA/memory move.
- IO commit (cycle boundary) → application consume/compute → output staging.
- Egress (Tx gate/tap) → transmit; add forwarding as a separate block if bridging/switching exists.
Metrics placeholders: latency(max/p99) · jitter(p99) · missed=0 · late/early ≤ X
Worst-case drivers (prove the upper bound, not the typical case)
Queue depth & arbitration
Stress queue occupancy and gate waiting. Validate that cyclic traffic remains bounded when acyclic traffic is busy.
DMA contention & memory pressure
Combine IO image transfers with logging/diagnostics to expose bus contention and worst-case transfer delays.
Interrupt/service latency
Correlate spikes with service latency and critical sections; treat outliers as first-class evidence, not noise.
Cache/path variability
Compare cold-start vs steady-state runs to prevent hidden cache effects from breaking the bound.
Evidence rule: every worst-case spike must map to a counter, a tap point, or a reproducible trigger
Budget template (use a card list to stay mobile-safe)
Assign a budget and a measurement definition to each block. Keep the fields stable across test runs so evidence can be compared.
Block: Ingress (Rx)
- Budget: X
- Tap: Rx timestamp / Rx boundary counter
- Worst-case: burst + back-to-back frames
- Pass: max ≤ X, p99 ≤ X
Block: Queue / Gate wait
- Budget: X
- Tap: queue enqueue/dequeue counters
- Worst-case: depth at cap + gate closed
- Pass: bounded wait, overflow = 0
Block: DMA / IO image
- Budget: X
- Tap: DMA start/end timestamps
- Worst-case: memory contention + logging
- Pass: max ≤ X, p99 ≤ X
Block: IO commit (cycle boundary)
- Budget: X
- Tap: commit timestamp + version counter
- Worst-case: boundary contention
- Pass: missed commit = 0, late ≤ X
Block: Application processing
- Budget: X
- Tap: app start/end markers
- Worst-case: cache misses + heavy path
- Pass: p99 ≤ X, max ≤ X
Block: Egress (Tx)
- Budget: X
- Tap: Tx gate release / Tx timestamp
- Worst-case: gate wait + FIFO pressure
- Pass: bounded jitter, drops = 0
End-to-end acceptance placeholders: Σ Xi ≤ X · p99 latency ≤ X · p99 jitter ≤ X · missed=0 · overflow=0
H2-8 · Conformance & certification: what you must be able to demonstrate
Certification success depends on demonstrable behavior and an evidence pack: consistent cyclic/acyclic handling, measurable performance, robust error handling, and logs that map directly to pass criteria.
Pre-test readiness (capabilities that must exist)
- Behavior consistency: cyclic schedule execution is repeatable; acyclic activity cannot break the bound.
- Stable tap points: Rx/commit/Tx measurement points are fixed and documented.
- Counters present: cycle counters, late/early, missed, queue overflow, storm guard triggers.
- Sync quality export: locked/degraded/holdover states are visible to logs and diagnostics.
During test (capture what makes results auditable)
- Record the active configuration snapshot (schedule version, queue caps, shaping limits, feature flags).
- Export rolling latency/jitter stats (p99/max placeholders) aligned to a fixed measurement window.
- Log every boundary exception: late/early, missed commit, overflow, watchdog/state transitions.
- Annotate runs with reproducible conditions (load level, traffic mix, duration, environment placeholders).
Evidence pack (what must be deliverable)
Required logs
Cycle counter · late/early · missed · queue overflow · sync quality · storm guard · reset/recovery markers
Configuration snapshot
Schedule version · queue/shaper limits · feature flags · firmware build ID · test duration and load placeholders
Results summary
Budget mapping (Σ Xi) · p99/max stats · anomaly list with timestamps · pass criteria table (X placeholders)
Common interoperability failure patterns: inconsistent tap points · missing overflow logs · unbounded acyclic storm · ambiguous sync quality state
H2-9 · Diagnostics & field service: make determinism observable
Field triage becomes reliable when determinism is observable: counters provide direction in seconds, a black-box trace makes rare events replayable, and export hooks map evidence to pass criteria (X).
MVP diagnostics set (minimum viable for field service)
Per-cycle health counters
- late / early (per cycle)
- missed window / missed commit
- active schedule epoch (version)
Queue & resource counters
- cyclic drops/overflow = 0 (target)
- acyclic drops/overflow + limit hits
- max depth watermark (cyclic/acyclic)
Black-box trace ring (small, fixed fields)
- time: cycle index / local timestamp (X)
- cause: late, missed, overflow, schedule-switch
- snapshot: queue depth, epoch, sync quality
MVP export hooks: read counters (low-rate) · dump ring (on demand) · map to pass criteria (X)
Pro diagnostics set (for rare, multi-factor failures)
Deeper counters (partitioned view)
Split by port, by queue, by window, and by cause category. Add watermarks and rate counters for storm detection (X).
Richer snapshots (still bounded)
Add IO commit version, DMA stall bucket, and service-latency bucket (X) so every outlier can be explained or reproduced.
Event-driven export (rate-limited)
Push a compact event summary on boundary exceptions, but enforce strict throttling and keep the export path out of the cyclic fast path.
Non-intrusive rules (placeholders): counter poll rate ≤ X · ring write O(1) · export is rate-limited · no cyclic-path blocking
Field triage (fast decision path)
Step A: deterministic health
Check late/early and missed first. If missed > 0 or late spikes exceed X, treat it as a boundary/latency problem.
Step B: queue & resource
If cyclic health degrades during acyclic activity, inspect queue drops/overflow, depth watermarks, and shaper limit hits (X).
Step C: black-box replay
Export the ring and correlate cause + snapshot to reproduce the outlier. Each spike must match a counter or a trigger condition.
H2-10 · Design hooks & pitfalls (IRT Device–specific)
The fastest way to harden an IRT device is to treat common pitfalls as reviewable cards: each item provides symptom, first check, fix, and pass criteria (X).
Pitfall #1 · Inconsistent timestamp tap points
Symptom: measured latency/offset differs across tools or stations; results cannot be compared.
First check: verify Rx/commit/Tx tap definition and whether epoch + cycle index are exported.
Fix: standardize tap points, freeze naming, and bind measurement to exported markers.
Pass criteria: multi-tool delta remains stable ≤ X under the same load.
Pitfall #2 · Acyclic storm steals resources from cyclic determinism
Symptom: jitter spikes and occasional missed cycles during parameterization/diagnostics.
First check: correlate cyclic late/early with acyclic depth, drops, and limit-hit counters.
Fix: isolate queues, enforce shaping/limits, and apply backpressure with bounded behavior.
Pass criteria: under worst-case acyclic load, cyclic p99 jitter ≤ X and missed=0.
Pitfall #3 · IO image race / data tearing
Symptom: process data appears inconsistent within the same cycle (partial old + partial new).
First check: inspect commit version monotonicity and cross-boundary writes.
Fix: enforce double buffering + atomic swap at boundary; define late-data handling (X).
Pass criteria: tearing = 0, commit occurs only on cycle boundary.
Pitfall #4 · Schedule table switch causes transient mismatch
Symptom: immediate cycle errors or short burst of drops right after switching schedules.
First check: confirm epoch switch is logged and aligned strictly to the cycle boundary.
Fix: use dual-table staging and boundary-only activation; provide rollback criteria (X).
Pass criteria: schedule switch causes missed=0 and late/early ≤ X.
Pitfall #5 · Interrupt storm / CPU preemption breaks cycle timing
Symptom: isolated jitter outliers that repeat under load; periodic drift during busy periods.
First check: correlate outliers with service-latency buckets and trace-ring cause codes.
Fix: minimize cyclic-path preemption windows; cap diagnostic/export rates; protect priorities (X).
Pass criteria: worst-case max jitter ≤ X with reproducible, explainable outliers.
H2-11 · Engineering checklist (Design → Bring-up → Production)
This checklist turns IRT-device requirements into auditable actions. Each stage expects concrete outputs: configuration locks, counters/log fields, stress evidence, and traceable production signatures (X).
Design (architecture, scheduling, buffers/queues, observability)
Architecture anchors (choose + freeze)
- Select PROFINET device silicon approach and document the IRT-critical blocks (examples: Renesas TPS-1, Siemens ERTEC 200P-3, Hilscher netX 52, TI Sitara AM335x/AM437x (PRU-ICSS)).
- Define cyclic fast path vs. acyclic path resource boundaries (queues, DMA channels, CPU budget) and forbid cyclic-path blocking.
- Freeze cycle time, window split, and guard-band policy as configuration items; assign pass thresholds (X).
- Freeze schedule epoch model (active table ID + boundary-only switch) and define rollback criteria (X).
Scheduling + IO image (determinism must be structural)
- Implement table-driven or state-driven scheduling and prove constant-time decision per packet/window (X).
- Implement IO image with ping-pong buffers and atomic swap at the cycle boundary; define late-data handling (drop/mark/degrade) (X).
- Enforce strict queue isolation: cyclic queue is hardware-gated; acyclic queue is shaped/limited with bounded backpressure behavior (X).
- Define and freeze timestamp tap points (Rx / commit / Tx) and export markers (epoch + cycle index) so measurements remain comparable.
Observability (evidence pipeline must be non-intrusive)
- Define MVP counters: late/early, missed window/commit, cyclic drops=0 target, acyclic drops/limit-hits, max depth watermark, active epoch.
- Define trace ring entry fields (fixed): time (local/cycle), cause code, snapshot (depth, epoch, sync quality) and guarantee O(1) write cost.
- Provide export hooks with throttling: read counters (low-rate), dump ring (on demand), compact event notify (rate-limited) (X).
- Define a “pass criteria map” that binds evidence to thresholds (p99 jitter ≤ X, max jitter ≤ X, missed=0).
Reference component anchors (examples, choose equivalents as needed)
- Protocol/ASIC/SoC: Renesas TPS-1; Siemens ERTEC 200P-3; Hilscher netX 52; TI AM335x/AM437x (PRU-ICSS).
- Ethernet PHY: TI DP83822I (10/100), TI DP83869HM (1G), ADI ADIN1300 (1G).
- ESD (data lines): TI TPD4E05U06 (multi-line ESD array).
- SPI NOR Flash (logs/config): Winbond W25Q64JV (64Mbit).
- I²C EEPROM (board ID/cal): Microchip 24LC02B.
- Reset supervisor: TI TPS3808G01.
- Buck regulator: TI TPS62130 (example).
- LDO: TI TLV1117-33 (example).
Bring-up (cycle alignment, stress tests, fault injection)
Alignment verification (boundary correctness)
- Verify cycle index continuity and boundary stability; late/early counters must stay within X and missed must remain 0.
- Verify epoch switching is boundary-only; after switch, missed=0 and transient spikes must stay ≤ X.
- Verify tap-point consistency by comparing measurements bound to the exported epoch + cycle index; delta must remain stable ≤ X.
- Verify IO image atomicity: commit version must be monotonic; tearing indicators must remain 0.
Stress tests (prove worst-case margins)
- Run acyclic/diagnostic max-load while cyclic traffic stays deterministic: cyclic p99 jitter ≤ X and missed=0.
- Push queue depth to watermark and confirm counters match reality (drops/overflow + trace cause codes align).
- Enable PHY loopback/PRBS and confirm link health tools do not distort cyclic timing (example PHYs: TI DP83869HM, ADI ADIN1300).
- Validate export throttling: counter polling and ring dumps must not increase late/early beyond X.
Fault injection (force observable exceptions)
- Inject “late” by delaying the service path; verify late counter increments, ring cause captures it, and recovery behavior is bounded (X).
- Inject “overflow” via acyclic storm; verify shaping/limits trigger, cyclic queue remains protected, and missed stays 0.
- Inject schedule switch under load; verify epoch log exists, boundary-only switch holds, and transient errors remain ≤ X.
- Induce ESD-like disturbances at the interface (with proper lab safety) and confirm protection paths are effective (example ESD: TI TPD4E05U06).
Production (consistency checks, version lock, regression matrix, traceability)
Consistency gates (every unit, every lot)
- Lock default determinism configuration (cycle/window/limits) and export a config signature (hash) per build (X).
- Run a minimal deterministic health test: late/early within X, missed=0, cyclic drops=0, acyclic drops within X.
- Station-to-station correlation: the same DUT must show stable deltas ≤ X when measurements are bound to tap + epoch + cycle index.
- Verify IO image integrity under production load: commit version monotonic; tearing=0.
Version lock + regression matrix (avoid “same name, different behavior”)
- Freeze schedule table format, epoch mapping, and switch rules; forbid undocumented changes.
- Freeze counter semantics and log enums across releases so field evidence remains comparable.
- Maintain a regression matrix: functional + determinism (p99/max/missed) + evidence pipeline (counters/ring/export) (X).
- Lock key storage/log parts and validate alternates (examples: Winbond W25Q64JV, Microchip 24LC02B).
Field traceability (standard evidence pack)
- Export a minimal trace header: firmware version, config signature, active epoch, sync quality state, build timestamp (X).
- Keep ring dump format stable and parsable across versions; include cycle index/time, cause code, snapshot.
- Standardize the field evidence pack: counter snapshot + ring dump + reproduction trigger description + pass criteria (X).
- Validate reset and brownout behavior stays bounded (example supervisor: TI TPS3808G01).
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H2-12 · FAQs (troubleshooting, fixed 4-line answers)
Each answer is intentionally compact and data-oriented: Likely cause, Quick check, Fix, and Pass criteria (threshold placeholders: X).
Cycle time is identical, but jitter grows under specific conditions—interrupt storm or acyclic burst?
Likely cause: IRQ service latency spikes or acyclic queue bursts stealing shared resources (DMA/CPU/memory).
Quick check: correlate cyclic late/early peaks with IRQ service-latency bucket and acyclic depth / limit-hit counters within the same epoch.
Fix: cap diagnostic/export rates, isolate cyclic path priorities, and tighten acyclic shaping/backpressure to bounded behavior.
Pass criteria: cyclic p99 jitter ≤ X, max jitter ≤ X, missed=0 under the worst-case workload profile.
Works in the lab, but occasionally shows “missed IRT window” in the field—queue depth or DMA contention first?
Likely cause: cyclic queue watermark hits (burst or arbitration) or DMA stalls/priority inversion delaying commit/Tx past the window.
Quick check: read missed-window counter with timestamped trace; inspect cyclic queue watermark and DMA-stall bucket around the same cycle index.
Fix: increase cyclic reserve (queue/DMA channel), raise cyclic arbitration priority, and reduce shared-bus contention from non-cyclic transfers.
Pass criteria: missed-window=0 over X cycles in field-equivalent load; cyclic watermark stays < X% of capacity.
Same firmware, but a different hardware revision shifts latency globally—timestamp tap changed or guard schedule changed?
Likely cause: tap-point definition moved (Rx/commit/Tx), or schedule/guard-band defaults differ despite identical cycle time.
Quick check: compare exported tap ID + config signature + active epoch across revisions; verify measurement binding uses the same epoch + cycle index.
Fix: standardize tap definitions and freeze schedule defaults; if hardware requires a different tap, version it and map it explicitly in tooling.
Pass criteria: cross-revision latency delta remains stable ≤ X and is fully explained by documented tap/schedule differences.
Cyclic data occasionally “tears”—is the double-buffer swap not at the cycle boundary?
Likely cause: swap/commit occurs outside the cycle boundary, or the application writes into the active buffer without a versioned handoff.
Quick check: read commit version monotonicity and tearing flag; confirm trace shows swap only at boundary (cycle index aligned).
Fix: enforce ping-pong buffers with atomic boundary swap; gate application access via version/lock discipline and forbid active-buffer writes.
Pass criteria: tearing=0 and boundary-only commit over X cycles under worst-case CPU load.
During acyclic parameter download, cyclic jitter increases—shaping not working or arbitration point is wrong?
Likely cause: acyclic flow bypasses the shaper (wrong queue path) or arbitration allows acyclic bursts to preempt cyclic service.
Quick check: confirm limit-hit increments during download; if not, the shaper is not in-path. Compare cyclic late/early vs. acyclic depth in the same epoch.
Fix: route all acyclic traffic through the shaped queue, enforce bounded backpressure, and reserve cyclic service in arbitration.
Pass criteria: under max acyclic download, cyclic p99 jitter ≤ X, missed=0, and acyclic depth stays below X.
Some devices fail to stay cycle-synchronous during interoperability—sync quality flags ignored or holdover behavior differs?
Likely cause: device logic treats degraded sync as “good enough” (quality flags not gating), or holdover state causes boundary drift without marking it.
Quick check: compare sync quality state transitions with late/early and missed-window spikes; verify trace ring logs quality state alongside cycle index.
Fix: gate cyclic scheduling on quality states, define explicit degraded-mode rules, and mark holdover entry/exit in counters and trace.
Pass criteria: when quality is “good,” missed=0 and p99 jitter ≤ X; when degraded, behavior follows documented fallback limits (X) and is always marked.
Packet capture looks clean, but field jitter is high—metric definition wrong or observation point is not on the hardware path?
Likely cause: capture is not aligned to hardware tap points, or counters/denominators differ between tools (window vs. cycle vs. time buckets).
Quick check: validate exported tap ID and metric denominator; compare hardware counters (late/early/missed) to software estimates within the same epoch.
Fix: standardize metric definitions, bind all measurements to epoch+cycle index, and use hardware-path counters as the source of truth.
Pass criteria: tool-to-tool delta ≤ X and hardware counters show p99 jitter ≤ X with missed=0 under the same scenario.
High load shows few drops, but motion quality degrades—late/early increases or commit latency drifts?
Likely cause: packets arrive, but boundary timing slips: commit is late or service latency grows, increasing phase error without visible drops.
Quick check: inspect late/early rate and commit-latency bucket during the load window; confirm missed remains 0.
Fix: reduce internal service latency variance (DMA priority, cache/bus contention), and reserve cyclic processing budget against load bursts.
Pass criteria: late/early ≤ X per X cycles, commit p99 latency ≤ X, missed=0 in sustained high load.
Short anomaly after configuration update—was schedule table hot-switch missing version alignment?
Likely cause: schedule epoch activated mid-boundary, or staging table mismatched the active IO/queue state when switching.
Quick check: locate an epoch switch event in trace; verify it occurs exactly at a boundary and includes old/new epoch IDs.
Fix: use dual-table staging, validate table checksum/signature, and enforce boundary-only activation with rollback on first anomaly.
Pass criteria: post-update transition yields missed=0 and late/early ≤ X for X consecutive cycles after switch.
Diagnostic alarms are frequent but performance is unchanged—thresholds too sensitive or missing event debounce?
Likely cause: alarm triggers on noise-level variance or lacks debounce/cooldown, causing alert storms without real determinism loss.
Quick check: inspect alarm reason histogram and debounce/cooldown counters; verify late/early and missed remain within targets.
Fix: tune thresholds to X based on baselines, add debounce windows and cooldown caps, and suppress duplicate alarms per cycle.
Pass criteria: alarm rate ≤ X per hour while determinism counters (missed, late/early) stay within limits (X).
One port triggers late events more often—port queue isolation incomplete or mirroring/capture consuming resources?
Likely cause: per-port queues share a bottleneck, or mirror/export path competes for DMA/CPU on that port.
Quick check: compare per-port late/early, per-port watermark, and mirror/export enable flags; verify whether late spikes align with capture activity.
Fix: enforce per-port isolation to the arbitration point, rate-limit mirroring/export, and reserve cyclic bandwidth per port.
Pass criteria: per-port p99 jitter ≤ X with mirror/export enabled; port-to-port delta ≤ X and missed=0.
Throughput is lower than expected at the same cycle—acyclic is over-limited or cyclic window is too conservative?
Likely cause: token bucket/limits throttle acyclic more than intended, or cyclic window leaves too little usable time for required payload.
Quick check: read limit-hit rate and acyclic depth; compare configured window utilization vs. observed payload per cycle (bound to epoch).
Fix: recalibrate shaping parameters to required payload, adjust window allocation conservatively, and keep determinism guard-band intact.
Pass criteria: payload per cycle ≥ X while cyclic p99 jitter ≤ X and missed=0 for X consecutive cycles.
