Boost + Ideal-Diode Path Power OR-ing ICs — Seamless Source Priority & Holdup
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This page focuses on a power path where a regulated boost stage coexists with a low-loss bypass using ideal-diode OR-ing to deliver seamless switchover, priority, holdup, and reverse blocking. With PGOOD chaining and controlled gate slew, it avoids dips and tug-of-war during transitions; back-to-back MOSFETs and appropriate current-sense schemes suppress reverse flow and inrush. We outline OR-ing / ideal-diode / power-mux / boost controller IC choices across seven leading brands plus practical validation methods.
Definition & Principle
Definition
Boost with Bypass / OR-ing adds a low-drop bypass path alongside the regulated boost channel. An ideal-diode / OR-ing controller driving back-to-back MOSFETs selects the preferred path and enforces reverse-current blocking, preserving load continuity during source or mode handovers.
Applicable Scenarios
- Dual-supply systems (primary/backup)
- Battery-to-load holdup / brownout ride-through
- Camera / wireless / MCU continuity paths
- Automotive small systems with hot-plug
- Industrial gateways using supercap backup
Operating Principle
Priority. The OR-ing controller regulates a small forward drop (VFD ≈ 15–25 mV), so the leg with lower effective drop conducts first.
Seamless switchover. Chain PGOOD from the actual load rail and shape the OR-ing gate with a controlled slew (RC) to minimize overlap time and avoid dips or tug-of-war. See Design Rules.
Reverse blocking. Use back-to-back N-MOS (common-source) to suppress reverse current; during pre-biased startup, clamp/sequence the gate to prevent false turn-on. Details in FET & Sensing.
Holdup. A load-side reservoir (supercap/electrolytic) provides short-term energy across brownouts or switchover gaps; size it per the holdup formula and add 20–30% margin (see holdup sizing).
Architecture: Boost + Low-Loss Bypass (Ideal-Diode OR-ing)
Layered Architecture
- Inputs: primary/backup (or modes), TVS/filter, UVLO.
- Boost path: synchronous preferred; SS/COMP, feedback & loop compensation.
- Bypass path: ideal-diode / OR-ing controller + back-to-back MOSFETs for low-loss pass.
- Merge node: two legs in parallel to the load rail; load-side reservoir & decoupling.
- Sensing & protection: OCP/OCL, thermal, reverse-current detection, PGOOD chain, diagnostics.
Key Relationships
- Priority formation: effective forward drop + OR-ing gate regulation select the active leg.
- Seamless switchover: SS, PG, gate slew, pre-bias handling, and current limiting act together.
- Reverse blocking: B2B FETs plus some ICs’ reverse-I detection and fast turn-off.
- Loop de-coupling: separate boost compensation poles/zeros from OR-ing gate-control bandwidth.
Design Rules: Seamless Switchover, Priority & Holdup
1) Holdup Sizing & Margin
- Formula: C ≈ 2·Pload·thold / (Vhi² − Vlo²).
- Guard-band: multiply for efficiency η and ESR/temperature derating → +20–30%.
- Goal: load-rail dip < X mV; recovery < Y ms during ride-through.
2) Priority Setting
- Use OR-ing controllers with adjustable forward drop or gate regulation.
- Ensure main leg’s effective drop < bypass; fine-tune using trace length / small series R.
- Derive PGOOD from the actual load rail as the truth criterion.
3) Seamless Switchover Timing
- PG chain: upstream-stable → downstream-enable; threshold based on load rail.
- Gate slew: shape dv/dt via RC or internal current-limited drivers.
- Overlap window: minimize parallel-conduction time to avoid inrush and tug-of-war.
4) Pre-Bias & Reverse Blocking
- During pre-biased startup, prevent unintended VGS forward bias: clamp/sequence the gate.
- B2B MOSFET selection: trade RDS(on) (loss/drop) vs Qg (switch loss/drive).
- Reverse-I detection / fast turn-off must specify threshold and propagation delay.
5) Thermal & SOA
- Hot-plug / large-C inrush → verify MOSFET SOA for the pulse profile.
- Copper area / vias for heat-spreading; apply derating in sealed enclosures.
- High-frequency gate ringing → add small series R / damping network.
FET & Current Sensing — RDS(on) / Qg · Reverse Blocking · Thermal Design
Select MOSFETs and sensing methods for boost-with-bypass OR-ing paths: trade RDS(on) vs Qg, implement common-source back-to-back devices for reverse blocking, and validate thermal/SOA margins.
FET selection essentials
- RDS(on) vs Qg: trade conduction loss (~ I²·R) against switching loss (~ Qg·fs·Vdrive); match gate-driver current and frequency.
- Back-to-back topology: common-source is typical; keep layout symmetrical with minimum loop area and shared gate damping.
- Package & thermals: check θJA, copper area, vias, and airflow; verify hotspots and uniformity via IR thermography.
Current sensing options
- Precision: shunt + amplifier with Kelvin routing — for protection/measurement; account for I²·R loss.
- Simplified: RDS(on) sensing — good for foldback/OCP, but accuracy drifts with temperature and tolerance.
- Reverse current: some OR-ing/ideal-diode ICs include detection + fast turn-off; confirm threshold and propagation delay.
Thermal & SOA checklist
- Hot-plug / large-C inrush → verify MOSFET SOA for pulse profile (I(t), VDS(t)).
- Heatsinking: copper area + vias; apply derating in sealed enclosures.
- High-frequency gate ringing → add small series R / damping; reduce gate-loop area.
IC Selection Matrix (7 Brands)
Unified fields for cross-brand comparison of boost, ideal-diode / OR-ing, and power-mux controllers. Fill PN data later — the layout hides empty values.
Texas Instruments
Boost controllers (sync), ideal-diode / OR-ing / power-mux controllers; strong PGOOD chaining, SS/UVLO headroom, ΔV regulation. Good documentation for reverse-I behavior and timing.
- Combos: Boost + ideal-diode driver / power-mux
- Watch: ΔV adjust, pre-bias handling, PG thresholds
STMicroelectronics
Synchronous boost plus standalone ideal-diode drivers; focus on adjustable VFD and reverse-current specs; packages suited for thermal spreading.
- Combos: Boost + ideal-diode driver
- Watch: VFD range, reverse-I threshold/delay
NXP (Automotive)
Boost + OR-ing / PMIC mux solutions with diagnostics; AEC-Q100 options and windowed PGOOD; attention to load disconnect and transient immunity.
- Combos: Boost + power mux / OR-ing
- Watch: AEC-Q100 grade, diagnostics pins
Renesas
High-efficiency external-FET boost plus ideal-diode control; strong pre-bias gate clamping and gate-protection guidance.
- Combos: Ext-FET boost + ideal-diode
- Watch: pre-bias clamps, PG timing
onsemi
Controllers with smartFET options; evaluate ISO pulse/transient robustness and SOA under inrush and holdup discharge pulses.
- Combos: Controller + smartFET path
- Watch: ISO pulses, SOA checks
Microchip
Compact boosts plus power-mux / ideal-diode controllers emphasizing low drop priority and board-level efficiency.
- Combos: Compact boost + mux
- Watch: low-drop priority behavior
Melexis
Power continuity around sensing systems; stable rails via ideal-diode paths, with diagnostics suited to sensor interfaces.
- Combos: Regulator + ideal-diode path
- Watch: sensor-friendly diagnostics
Paste this into your spreadsheet and fill real part numbers later. Field order is fixed; leave “—” for unknowns.
Validation: Waveforms · Conditions · Pass Criteria
Execute a structured matrix covering seamless switchover, reverse blocking, inrush/thermal, and loop stability. Record Vout, path currents, gate, and PG; export lightweight images (2:1 PNG ≤50 KB) and CSV with key channels.
Seamless Switchover
- Cases: Main→Backup, Backup→Main, brownout 1–50 ms
- Record: Vout, IpathA/IpathB, Gate, PG
- Pass: dip < X mV; recovery < Y ms; no reset / artifacts / frame drop
Reverse Blocking
- Cases: pre-biased start, load back-feed, asymmetric sources
- Pass: Irev < threshold; no unintended gate turn-on
Inrush & Thermal
- Cases: hot-plug / large-C startup, holdup discharge
- Pass: MOSFET SOA satisfied; junction T < limit; no thermal shutdown
Loop Stability
- Cases: load step / input step / across temperature
- Pass: no sub-harmonic; overshoot & ripple within spec
<Case>_<Chs>_<Fs>_<Date>.(png|csv).
| Condition | Record | Pass Criteria | Notes |
|---|---|---|---|
| Main→Backup / Backup→Main / Brownout 1–50 ms | Vout, IpathA, IpathB, Gate, PG | Dip < X mV; recovery < Y ms; no reset/artifacts/frame drop | PG from load rail; gate slew RC tuned |
| Pre-biased start / Load back-feed / Source asymmetry | VGS, Irev, Vout | Irev < threshold; gate not falsely enabled | Reverse-I detection threshold & delay verified |
| Hot-plug / Large-C power-up / Holdup discharge | I(t), VDS(t), Tj | FET SOA satisfied; Tj < limit; no thermal trips | Check ESR heating; duty worst-case |
| Load step / Input step / Temperature sweep | Vout ripple & overshoot, loop behavior | No sub-harmonic; ripple/overshoot within spec | Compensation vs OR-ing bandwidth separation |
Application Examples & Parameter Decision Paths
Each card summarizes objective → design decisions → validation. Micro-flows (inline SVG) show how to size holdup, set VFD and gate slew, and confirm results.
Example 1 — Camera chain, no frame drop
- Objective: within 16.7 ms frame gap, Vout dip < X mV
- Decisions: set VFD, RC gate slew, PGOOD order, Chold margin
- Waveforms: Vout, Gate, PG, Iload before/after switchover
| Parameter | Value |
|---|---|
| Vin / Vout / Iout | — |
| Pload / thold | — |
| ΔVtarget / η | — |
| Chold (calc / actual) | — |
| ΔVmeasured | — |
Example 2 — Industrial gateway with supercap backup
- Objective: ride through 20–50 ms outages
- Decisions: compute Chold from Pload, Vhi→Vlo then +30% margin; SOA/ESR checks
- Verification: brownout steps, cold/hot start, −20~70 °C sweep
| Parameter | Value |
|---|---|
| Pload / thold | — |
| Vhi → Vlo / η | — |
| Chold (+30%)/ ESR | — |
| Result (no-drop window) | — |
Example 3 — Automotive mini-system hot-plug
- Objective: survive ISO pulses / transients without damage
- Decisions: B2B FET SOA, pre-bias clamp, gate damping
- Validation: ISO pulse set, vibration & temp cycling, diagnostic reporting
| Parameter | Value |
|---|---|
| ISO pulses / transient set | — |
| B2B FET part / SOA headroom | — |
| Clamp & damping values | — |
| Result (pass/fail) | — |
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Engineering FAQ — OR-ing / Boost / Bypass
Fifteen concise answers (45–60 words each) to the most common questions about seamless switchover, priority, reverse blocking, holdup, stability, and validation. Links jump to the relevant sections for deeper context.
How do we avoid load dips and transients during seamless switchover?
Reference the load rail for PGOOD, then shape the OR-ing gate with a defined slew (RC or current-limited driver). Minimize the overlap window between legs, and assert downstream enables only after the load voltage is stable. Verify dip and recovery against targets in Design Rules and Validation.
How is OR-ing priority set reliably, and how do we prevent “tug-of-war”?
Use OR-ing controllers with adjustable forward drop or gate regulation. Ensure the main leg has the lowest effective drop; fine-tune by trace length or a small series resistor. Keep loop bandwidths separated to avoid control interaction. See Architecture and Design Rules.
Do we always need back-to-back MOSFETs? Can a single MOSFET block reverse current?
Back-to-back devices are preferred for robust reverse-current blocking and pre-bias scenarios. A single MOSFET works only when body-diode conduction is acceptable or reverse flow is explicitly allowed by the system. Evaluate thresholds and delays if the controller provides reverse-I detection. See FET & Sensing.
Why does pre-biased startup cause false turn-on, and how do we clamp/sequence the gate?
External bias can lift VGS unintentionally through parasitic paths. Clamp the gate to source, control dv/dt, and order enables so downstream rails are valid before upstream handover. Validate with pre-bias power-up tests and confirm no unintended conduction. Refer to Design and Validation.
How do we size holdup capacitors from power, time, and Vhi → Vlo, and what margin is sensible?
Use C ≈ 2·Pload·thold / (Vhi² − Vlo²), then add 20–30% for efficiency, ESR, and temperature derating. Check ripple and thermal rise, and confirm ride-through in brownout steps. See the formula card in Design Rules.
RDS(on) sensing vs shunt: what accuracy and application boundaries should we expect?
RDS(on)-based sensing has significant temperature and lot variation, making it suitable for protection and foldback rather than metering. Shunt + amplifier with Kelvin routing delivers predictable accuracy at the cost of I²R loss. Choose per error budget and bandwidth. See FET & Sensing.
Which node should drive PGOOD to avoid “false good” indications?
Derive PGOOD from the actual load rail, not only from the boost or OR-ing nodes. Use a threshold window that reflects downstream requirements, and chain enables so each stage waits for the real, settled rail. See sequencing notes in Design Rules.
How do we tame inrush and gate ringing for hot-plug or large-cap startup?
Limit dv/dt with gate slew control, add a small series gate resistor with damping, and respect MOSFET SOA under the expected pulse. Verify with current and VDS captures and a thermal check. Refer to Validation and FET & Sensing.
How do we verify back-to-back MOSFET SOA against holdup discharge pulses?
Capture I(t) and VDS(t), compute instantaneous power and energy, and confirm the trajectory stays within the device SOA across temperature. Validate repeated pulses and worst-case duty. See the SOA illustration and test matrix in Validation.
How do we keep the boost loop stable when the OR-ing gate is modulating?
Separate bandwidths so the boost compensation poles/zeros sit away from the OR-ing gate-control dynamics. Maintain phase margin under load and input steps, and avoid cross-coupling that invites oscillation. See Architecture and Design Rules.
What should we consider for AEC-Q100 and diagnostic pins in this architecture?
Prefer controllers and drivers with AEC-Q100 options, diagnostic status, and windowed PGOOD. Route status lines robustly, and validate transient immunity. Align reporting with system fault management. See brand notes in IC Selection Matrix.
How do brownout thresholds and holdup targets translate into pass criteria?
Define a permitted Vout dip (mV) and recovery time (ms), require no resets or visual/data artifacts, and demonstrate ride-through across the brownout window. Accept only if all channels meet limits across temperature. See Validation and Design Rules.
How do we achieve lower drop priority without sacrificing efficiency (RDS(on) vs Qg)?
Lower RDS(on) reduces conduction loss and improves priority, but switching loss grows with Qg·fs·Vdrive. Match the gate-driver current and frequency profile, and consider thermal limits. Use the loss balance guidance in FET & Sensing.
Will EMI/ripple get worse, and what universal mitigations apply here?
Tighten high-di/dt loops, place capacitors with short returns, and tune compensation to avoid peaking. Separate bandwidths, add RC snubbers where ringing persists, and validate with ripple/EMI scans. Cross-check timing in Design and loop results in Validation.
Where is the boundary with the Power-Mux topic to avoid solution conflicts?
This page focuses on low-drop priority paths, seamless switchover, and reverse blocking using ideal-diode OR-ing. If you require multi-source arbitration, soft-limit modes, or controlled disconnect behavior, defer to the Power-Mux page. Keep cross-links clear to prevent overlap.
