Inverting Buck-Boost (−V Rail): Design, Layout, IC Guide

Q: How do I estimate duty and device stress?

Q: Where should crossover sit vs the RHPZ and ESR zero?

Set crossover comfortably below the right-half-plane zero: fC ≤ fRHPZ/5. Place a compensator zero near the power pole; use the ESR zero to lift phase if beneficial. Verify phase margin 45–60° across VIN/IOUT corners with PWM-only (no PFM/spread-spectrum) during Bode sweeps.

Inverting Buck-Boost (−V Rail) — Intro

An inverting buck-boost converts a positive input into a regulated negative rail with a single inductor and a ground-referenced switch node. It excels at −3.3 V/−5 V/−12 V supplies for op-amps, sensor bias, and mixed-signal cards. Stability is constrained by a right-half-plane zero (RHPZ) and by hand-off between constant-voltage (CV) and constant-current (CC) behavior. Robust designs implement soft-start, pre-bias protection, and tight hot-loop layout to prevent reverse discharge and start-up glitches. Start by checking VIN range vs target −VOUT, stress across switch/diode (≈ VIN + |VOUT|), RHPZ-aware compensation, and CC limit sized for safe analog biasing.

Principle

Ideal transfer (CCM) |V_OUT| = ( D / (1 − D) ) · V_IN (sign is negative by inversion)

Duty trend As |V_OUT| increases, D → 1 and device stress rises ≈ V_IN + |V_OUT|.

Inductor ripple ΔI_L ≈ ( V_IN · D ) / ( L · f_S ) (watch the DCM corner at light load).

RHPZ ω_RHPZ ≈ ( I_OUT · (1 − D)² ) / ( L · |V_OUT| ) lowers allowable crossover; grows with load current.

Output pole ω_PO ≈ 1 / ( R_LOAD · C_OUT ) • ESR zero ω_ZESR ≈ 1 / ( R_ESR · C_OUT )

Compensation Choose f_C well below ω_RHPZ; place a compensator zero near the power pole and account for ESR zero lift. Coordinate the outer CV loop with CC clamp/loop to avoid oscillation at the boundary.

Compensation target: set crossover below the right-half-plane zero; account for ESR zero lift.

Example. From +12 V to −12 V at 0.5 A using L = 10 µH and D ≈ 0.5: ΔI_L ≈ (12 · 0.5)/(10e−6 · f_S). For f_S = 500 kHz, ΔI_L ≈ 1.2 A_pp. As load increases, ω_RHPZ rises, so keep f_C comfortably lower and verify with loop-gain injection.

Architectures

Single-inductor inverting 2-switch inverting Synchronous vs diode Peak vs valley current limit Low-side shunt / DCR / high-side sense Dual loops: CV (outer) + current (inner/limit)

Single-Inductor Inverting Buck-Boost

Smallest BoM and footprint; straightforward CV+CC implementation, suitable for −3.3/−5/−12 V rails ≤≈1 A.

Pros: Compact, simple control, easy to add foldback/CC clamp.
Trade-offs: Device stress ≈ V_IN + |V_OUT|; RHPZ limits bandwidth; diode loss unless synchronous.
Use when: Bias rails for op-amps/sensors; moderate load; tight space.

2-Switch Inverting

Higher efficiency and improved CC behavior for heavier loads or larger |V_OUT|.

Pros: Lower rectifier loss; better thermal headroom; robust CC region.
Trade-offs: More components, tighter layout/drive timing, compensation detail ↑.
Use when: −12/−15 V at higher current; thermal margins are critical.

Synchronous vs Diode

Diode: Quick design, lower cost; loss = I · V_F; good at light/intermittent loads.
Synchronous: Efficiency ↑ at heavy load; requires reverse-current control and safe dead-time.

Rule-of-thumb: Compare I·V_F vs I²·R_DS(on). Choose diode for light/peaky loads, sync for sustained heavy load.

Current Sensing

Low-side shunt: Simple, large signal; requires Kelvin and PGND noise control.
Inductor DCR: Low loss; RC model & temperature compensation needed.
High-side/NEG shunt: Needs diff-amp; check common-mode and headroom.
Limit style: Valley reduces sub-harmonic risk; Peak is intuitive but edgy near boundaries.

Dual Loops: CV + Current

Outer CV loop sets −V; inner current-mode loop stabilizes power stage.
CC function as clamp or dedicated loop; tune the hand-off to avoid oscillation.
PFM/burst at very light load may hinder loop measurement; consider PWM-only during validation.

Topology overview: single-inductor is compact; 2-switch improves efficiency and CC behavior at higher current.

Design Rules

Inductor Sizing

Target ripple: ΔI_L ≈ 20–40% · I_L(avg) at mid-VIN.
ΔI_L ≈ ( V_IN · D ) / ( L · f_S ) ⇒ L ≈ ( V_IN · D ) / ( ΔI_L · f_S )

Peak check: I_PK ≳ I_OUT · ( |V_OUT| / V_IN ) + ΔI_L/2. Ensure core saturation rating ≥ 1.2× I_PK.

At very light load, DCM/skip alters dynamics—limit bandwidth and validate loop stability in PWM-only mode if needed.

Switches & Diodes

Voltage stress: both sides ≈ V_IN + |V_OUT|; choose ≥20–30% margin.
Current stress: size for conduction RMS and I_PK; consider thermal rise with copper spreading.
Diode choice: Schottky favored; check I_avg ≥ I_OUT, T_j at worst case; fast-recovery noise matters for EMI.
Synchronous: gate timing prevents reverse discharge; limit reverse current; optimize dead-time without sacrificing rectification integrity.

Output Network

Combine low-ESR bulk with small HF MLCC near the negative output return. Keep NEG ground local and route with care to avoid polluting analog ground.

ω_ZESR ≈ 1 / ( R_ESR · C_OUT )

Kelvin: Sense V_OUT− and the return of C_OUT with Kelvin traces to the controller’s feedback pins.

Compensation

ω_RHPZ ≈ ( I_OUT · (1 − D)² ) / ( L · |V_OUT| )

Crossover target: f_C ≤ f_RHPZ/5 with phase margin ≥ 45–60°.

Place compensator zero near the power pole; leverage ESR zero to lift phase where appropriate.
Use adequate slope compensation in current-mode; narrow bandwidth near mode boundaries.
Validate with injection (see Validation section): document f_C, PM, GM across VIN/IOUT corners.

_PO f_ZESR f_C f_RHPZ Set f_C well below f_RHPZ

Place crossover below the RHPZ; use ESR zero to assist phase where it helps.

Soft-Start & Pre-Bias

Use reference ramp and/or current clamp for predictable inrush and glitch-free startup.
Block reverse discharge paths (body diode/sync FET) when −V is pre-biased before start.
Sequence with UVLO/OVP awareness; log startup profile with/without load.

Soft-start with a current clamp prevents overshoot; pre-bias protection avoids negative rail discharge at start.

CC Loop / Current Limit

Options: foldback, true constant-current, or power-limit. Define accuracy and thermal envelope.
Valley vs peak limit: valley eases boundary behavior; peak is intuitive but can overshoot near transitions.
Coordinate CV↔CC boundary (I_LIM vs V_REF) and add hysteresis/bandwidth shaping if “ping-pong” occurs.

Protections

UVLO / OVP / OCP / SCP / OTP — OCP should be cycle-by-cycle.
Short-to-ground on −V: verify foldback curve and thermal shutdown.
Negative discharge isolation: ideal-diode FETs or back-to-back FETs; snubber to tame SW ringing.

f_C ≤ f_RHPZ/5 Phase margin ≥ 55° preferred Voltage margin ≥ 30% I_sat ≥ 1.2× I_PK PWM-only during loop tests

Layout & EMI

Minimize the hot loop: SW → rectifier (D/sync FET) → C_OUT → switch. Keep it triangular and tiny.

Single-point ground: Tie PGND and AGND at the IC ground island; keep FB/COMP inside AGND.

Kelvin & snubber: Kelvin sense the shunt and C_OUT return; place RC snubber close to SW path.

Keep the SW–rectifier–Cout loop tiny, tie PGND–AGND at one point, and Kelvin-sense Cout/shunt into the controller.

Snubber & Damping

Use an RC snubber from SW to PGND to tame ringing. Start with small C and sweep (e.g., 100–680 pF) while observing spike reduction and efficiency.

Heuristic: choose R near the SW-node impedance; place RC close to the switch and rectifier with a short return to PGND.

Input/Output Decoupling

Input RMS current is “boost-like”; rate input capacitors accordingly. Place small HF MLCCs at the switch input and between rectifier and Cout to form the shortest HF return.

Layout Checklist

Hot loop traces are short and compact; SW copper limited to what is thermally needed.

PGND and AGND meet at a single tie near the IC; FB/COMP remain inside AGND island.

Shunt and Cout returns Kelvin-sensed to the controller; FB reference and Cout return share the same point.

RC snubber placed adjacent to SW and rectifier; short, direct return path to PGND.

HF MLCCs placed to close the HF loop; input capacitors sized for RMS current.

Provision test pads; use loop probe/short ground spring; never reference SW node as ground.

Validation

Test Matrix

Startup & pre-bias: cold start with/without load; pre-biased −V; shutdown/restart.
CV→CC transitions: slow ramp and step into CC; stability and recovery.
Short & overload: hard/soft shorts; foldback, thermal trip, recovery conditions.
Line/load transients: VIN dips/surges; load steps in CV and CC regions.
Thermal: steady-state at 25/55/85 °C; component hot-spots and derating.
Loop gain (Bode): injection points; disable spread-spectrum; PM and f_C across corners.

Record soft-start profile with/without pre-bias; ensure reverse discharge is blocked and current clamp limits inrush.

CV→CC — Slow Ramp

Increase load until reaching I_LIM; observe voltage/current hand-off. Tune hysteresis or bandwidth if “ping-pong” oscillation appears at the boundary.

CV→CC — Step

Apply +ΔI step from CV region to force CC, then step back. Measure settling time and undershoot/overshoot; ensure stability in both directions.

Insert a 10–50 Ω injection resistor in the COMP/FB path; use an isolation transformer; disable spread-spectrum and PFM during loop-gain measurements.

Validation Checklist

Startup and shutdown show no negative-rail discharge; soft-start limits inrush with/without pre-bias.

CV↔CC hand-off has no sustained oscillation; recovery time meets target.

Short-to-ground behavior matches foldback plan; thermal shutdown and auto-restart verified.

VIN dips/surges and load steps satisfy ΔV/V and settling time requirements in CV and CC regions.

Hot-spots identified (diode vs sync FET, SW node, shunt); junction temps within limits with margin.

Across VIN/IOUT corners, phase margin ≥ 45–60° and f_C ≤ f_RHPZ/5; results logged.

Measurement Log (copy-ready)

VIN: _______ V    VOUT−: _______ V    IOUT: _______ A    fS: _______ kHz
COMP values: R= _______ Ω, C= _______ nF  |  fC: _______ kHz  PM: _______ °
Modes: PWM-only (Y/N)  Spread-spectrum OFF (Y/N)  Temp: _______ °C
Startup: clean (Y/N)   Pre-bias reverse discharge (Y/N)
CV→CC hand-off: stable (Y/N)  settle: _______ μs  overshoot: _______ %
Short: foldback curve logged (Y/N)   thermal trip at: _______ °C
Line/load: ΔV/V= _______ %   settle: _______ μs
Notes: ____________________________________________________________________

IC Selection Guide

Optimize selection by VIN, target −V, IOUT, efficiency/thermal limits, CC needs, rectification (Sync/Diode), and AEC-Q100 requirements. Use the matrix to filter, then jump to a brand bucket or a quick-pick scenario.

VIN: 5–6 VVIN: 9–18 VVIN: 6–40 V VOUT−: −3.3 VVOUT−: −5 VVOUT−: −12/−15 V I_OUT: ≤0.2 A0.2–1 A≥1 A Rect: DiodeRect: SyncCC: Clamp/True-CC Pre-bias SafePFM OffAEC-Q100

_OUT Rect (Sync/Diode) CC (Clamp/True-CC) PFM Off (test) AEC-Q100

Filter strategy: start from VIN and target −V, size for current, then decide rectification, CC behavior, PFM setting, and AEC-Q100.

−5 V @ 100 mA — Op-Amp Bias

Low noise, small size, light-load efficiency.

VIN: 5–12 VRect: DiodeSoft-startPre-bias SafeLow I_q

−12 V @ 500 mA — Analog Cards

Thermals & efficiency dominate.

VIN: 9–18 VRect: SyncCC: Foldback/True-CCf_S ≥ 400 kHz

−3.3 V Tracking +3.3 V

Sequencing & tracking with PG.

TrackingPG/RESETRef-ramp SSPre-bias SafePFM Off

Fixture CC Mode — Protect DUT

Stable CC region, calibrated limit.

True-CC / Precise clampValley limitPWM-onlyExpose COMP

AEC-Q −12/−15 V

Wide VIN, cranking, EMC options.

AEC-Q100VIN: 6–40 VSpread-spectrum On/OffOVP/UVLOSync

Cost-Sensitive −5 V @ 200–300 mA

BOM priority; acceptable diode loss.

Rect: DiodeBasic SSMedium I_qActive lifecycle

Comparison Matrix (Fields)

Use these fields to evaluate controllers/regulators for inverting buck-boost −V rails.
Electrical	Topology	Control	Start & Loops	Protections	Analog UX	System	Commerce	Notes
VIN 5–18 V VOUT− −3.3…−12 V I_OUT up to 0.5 A f_S 300 kHz–2 MHz Eff. mid/heavy load points	Single-inductor Rect: Diode	Current-mode PFM (switchable) Slope comp	Soft-start: ref-ramp Pre-bias safe CC: Clamp	UVLO / OCP (cycle) / OVP / SCP / OTP Neg. discharge block	PG/RESET Rail tracking Vref acc. noted	I_q low QFN/SOIC θJA reference	Active Good availability Cost: $$	Layout: small hot loop; PWM-only for Bode.
VIN 6–40 V VOUT− −5…−15 V I_OUT 0.5–2 A f_S 200 kHz–600 kHz Eff. optimized for heavy load	2-switch inverting Rect: Sync	Current-mode PWM-only (test) Spread-spectrum (switchable)	Soft-start: ramp + I-clamp Pre-bias safe CC: Foldback/True-CC	UVLO/OVP/OCP(SCP)/OTP Reverse current limit	PG/RESET Tracking/Sequencing Diagnostic flags	AEC-Q100 options QFN/HTSSOP θJA/θJC listed	Active Automotive supply Cost: $$$	Thermal copper required; snubber near SW.

Tip: keep PFM off during loop-gain tests; set f_C ≤ f_RHPZ/5; ensure OCP is cycle-by-cycle.

Brand Buckets (Capabilities by Series)

TI

Wide VIN & series depth; current-mode, spread-spectrum, rich PG/tracking; multiple AEC-Q.

Sync & DiodePFM OffPre-bias SafeAEC-Q100

ST

Controller + integrated options; EMI-friendly; industrial & auto lines.

Wide VINSync/DiodeSpread-spectrum

NXP

Automotive/industrial focus; EMC & diagnostics strong.

AEC-Q100DiagnosticsSync favored

Renesas

Low-noise analog bias orientation; refined startup/loop behavior; auto variants.

Pre-biasTrackingPFM Off

onsemi

Efficiency & thermal emphasis; power devices synergy; auto-grade options.

SyncThermal headroomAEC-Q100

Microchip

Straightforward designs; extensive eval resources; long lifecycle.

Diode/SyncSoft-startDocs/EVM

Melexis

Automotive/ sensor interface contexts; diagnostics & temp drift control.

AEC-Q100Diagnostics

Weighting guidance for shortlist decisions. Adjust as your application priorities shift.

Quick FAQ

When to prefer synchronous over a diode? Choose sync for sustained heavy load or tight thermal budgets. For light/intermittent loads, a diode is simpler and often adequate.

How to spot pre-bias-safe ICs? Look for controlled startup paths and reverse-discharge blocking in the datasheet; verify with a pre-biased test.

PFM off? Disable PFM during loop-gain and EMI validation; re-enable only if light-load efficiency is critical and stability is confirmed.

AEC-Q100 vs industrial? AEC-Q100 adds automotive stress/EMC/diagnostic criteria; ensure VIN range and spread-spectrum options suit your EMI plan.

FAQs

When is an inverting buck-boost better than a charge pump?

Choose an inverting buck-boost once load current exceeds a few tens of milliamps, the input varies widely, or strict regulation/EMI control is required. Closed-loop duty control maintains −V across line/load. Charge pumps excel at light loads and fixed ratios, but scale poorly with current and ripple.

How do I estimate duty and device stress?

Where should crossover sit vs the RHPZ and ESR zero?

Set crossover comfortably below the right-half-plane zero: f_C ≤ f_RHPZ/5. Place a compensator zero near the power pole; use the ESR zero to lift phase if beneficial. Verify phase margin 45–60° across VIN/IOUT corners with PWM-only (no PFM/spread-spectrum) during Bode sweeps.

How to ensure a clean CV↔CC hand-off?

Align the CC threshold with the CV loop’s maximum controllable current. Near the boundary, reduce bandwidth and add small hysteresis if “ping-pong” occurs. Valley current limiting usually transitions more smoothly than peak. Test both slow ramps and steps into/out of CC; log settling and thermal limits.

What soft-start works best with pre-biased −V?

Use a reference ramp combined with a current clamp. Block reverse discharge through body diodes or sync FETs until control is active. Record startup with and without pre-bias; any negative glitch indicates insufficient blocking or clamp headroom. Consider back-to-back FETs or an ideal-diode controller.

Valley vs peak current limit—why prefer valley?

Valley limiting mitigates sub-harmonic tendencies at high duty and yields smoother CV→CC transitions. Peak limiting is intuitive yet can overshoot as ripple adds to the command. If peak mode is required, increase slope compensation and lower crossover near the limit to avoid chatter.

How do I Kelvin-sense the shunt and Cout return?

Use four-terminal routing: carry the shunt’s sense traces separately back to the amplifier/AGND, not through power vias. Kelvin the Cout return to the feedback reference point so the controller senses the same node the load sees. Keep FB/COMP entirely within the AGND island.

How big should the snubber be—where do I start?

Start small and sweep: 100–680 pF with a resistor near the SW-node impedance. Place RC tight to the switch/rectifier and return directly to PGND. Tune by observing ringing reduction versus efficiency/temperature. Over-snubbing raises loss without meaningful EMI benefit.

Why does input RMS look “boost-like”, and how do I size Cin?

The inverting buck-boost draws pulsating current from VIN similar to a boost stage, increasing input capacitor RMS stress. Choose low-ESR bulk plus small HF MLCC close to the switch, and verify RMS/temperature limits. Keep loop area tight to reduce conducted EMI and ripple injection.

How do I track −3.3 V with +3.3 V?

Use a controller with tracking/soft-start that accepts a ramped reference or dedicated tracking pin. Tie PG/RESET and sequencing so both rails rise together and meet POR timing. Confirm pre-bias-safe behavior and disable PFM during validation to avoid skewed timing measurements.

What changes in DCM or with PFM enabled?

In DCM, plant dynamics shift and the effective RHPZ behavior changes, complicating compensation. PFM/burst improves light-load efficiency but disrupts repeatable loop measurements. Validate stability in PWM-only mode first; then enable PFM and re-check output ripple, audio-band noise, and transient response.

How do I test short-to-ground on the negative rail safely?

Use a low-value power resistor for “soft short” before a true short; monitor current limit, foldback, and temperature. Ensure cycle-by-cycle OCP and reverse-discharge blocking. After removal, confirm clean recovery to CV without latch-up or oscillation; log worst-case thermal rise.

Spread-spectrum on or off during loop-gain measurements?

Turn spread-spectrum off for Bode plots. Frequency dithering smears phase/gain and hides crossover/peaks. Use fixed PWM, then re-enable spread-spectrum for EMI work and confirm the margin still meets target. Document both states in your report to avoid confusion later.

Where are thermal hotspots, and how do I predict them quickly?

Expect heat at the rectifier or sync FET, the main switch, and the snubber network. Estimate loss with I·V_F (diode) or I²·R_DS(on) (sync), plus switching/snubber dissipation. Use copper pours and vias under hotspots; validate with IR imaging at typical and CC conditions.

How accurate can the CC loop be for analog bias, and how to calibrate?

Accuracy depends on shunt tolerance, amplifier offset/drift, and sense filtering. Use a precision shunt, Kelvin routing, and temperature-aware gain calibration. Characterize error over current and temperature; if needed, implement a trim resistor or digital calibration to meet bias-current limits without nuisance limiting.

Inverting Buck-Boost (−V Rail): Principles, Design Rules, and IC Selection