Telemetry & Health: V/I/T, Black-Box Events, and Lifetime Counters

Capture Vout (±1% dc), Iout (±3% dc), and case/board temperature (±2 °C typical) with a power-good status and a min/max window. Add a 200–400 ms pre-trigger buffer and an 800 ms post window for events. This covers brown-outs, overloads, thermal drift, and user-visible resets.

Pick Rsh so Vfs = Imax × Rsh meets your monitor’s full-scale (typically 50–100 mV for low loss). Ensure light-load resolution ≥ 5–10 LSBs after gain. Check self-heating: P = I²Rsh at worst case. Use Kelvin routing and consider PWM-immune CSAs to avoid ripple bias.

Use a fast analog comparator for threshold qualification (tens of microseconds) and log via ADC at 1–10 Hz health rate. Latch min/max in hardware with a debounce of 1–5 ms. The comparator prevents aliasing; the slow stream preserves history without flooding storage.

Split paths at the sense node: fast comparator with its own RC and reference handles protection; buffered, bandwidth-limited path feeds the ADC. Do not load PG nodes. Keep grounds independent until a star point; match input impedances to minimize cross-coupling and delay skew.

Use a supercap “last-gasp” path: on brown-out IRQ, shrink the snapshot, commit an atomic tuple (header→payload→CRC), and set an integrity marker. On boot, scan for valid tuples by CRC and monotonic sequence. Keep the commit within a fixed energy budget and time bound.

Bin cumulative stress—A·s, °C·s above a reference, ripple exposure—then compute a weighted score with hysteresis (Green/Amber/Red). Include fault-hours and retried events. Calibrate thresholds from fleet data so flags predict RMAs with low false positives. Log the mapping and revision.

For field triage, 200–400 ms pre-trigger typically captures the causal load or VIN sag; pair with ~800 ms post window. Ensure fixed-rate ticks and a monotonic counter. For faster rails, keep hardware min/max in parallel so you don’t miss sub-buffer transients.

DCR works for trend and protection but struggles with ±3% dc accuracy over temperature and tolerance unless you calibrate R and L and control thermal tracking. Use matched networks and temperature compensation; keep a shunt for acceptance tests or absolute energy accounting.

Place RC anti-aliasing at the sense buffer, add a short digital debounce (1–3 switching periods), and use a programmable blanking window around mode transitions. Prefer CSAs with PWM rejection and route the sense pair tightly to suppress capacitive pickup from the SW node.

Adopt a rolling journal with round-robin pages and severity-aware caps (e.g., last 64 critical, 32 major, 16 warnings). Commit summaries periodically, events on demand. Keep erase count balance within 10%. Store page headers and CRC so recovery is deterministic after power loss.

PMBus gives standardized pages, scaling, and tooling; it adds complexity and code size. A minimal I²C map is lighter and can expose “min/max since last read” with auto-clear. For one rail and tiny MCUs, I²C is efficient; for fleets and tooling, PMBus scales better.

Append a device-scoped HMAC-SHA256 over the normalized payload (CSV line or CBOR bytes) including ts_ms, monotonic tick, and firmware revision. Keep the key in protected storage; verify server-side. Include a CRC for transport errors and a counter to prevent replay.

It can redistribute ripple energy and slightly change peak timing. Hardware min/max still works if your anti-alias and blanking are set for the broadened spectrum. For precision, increase measurement dwell or use EWMA windows large enough to smooth frequency dither effects.

Use a shared monotonic tick sourced from a common oscillator and mark events with both ts_ms and tick. Periodically discipline drift using a sync pulse or host-broadcast checkpoint. On merge, align by tick, then refine by wall clock to handle wrap and resets.

Prioritize cumulative charge (A·s), thermal exposure above reference (°C·s), fault-hours, and retried-event counts. Add ripple-stress bins per mode. These correlate with connector fatigue, capacitor aging, and MOSFET stress. Track firmware revisions so counter trends map cleanly to design changes.