Introduction & Scope
Wideband high-PSRR LDOs preserve ripple rejection up to 10 kHz–10 MHz, scrubbing switching-regulator residue so sensitive analog rails stay clean. This page focuses on selection, layout, and validation that keep PSRR high under real load, spread-spectrum, and temperature.
Scope: wideband PSRR only (10 kHz–10 MHz). For low-noise, ultralow-Iq, DDR VTT/Vref, high-voltage, or RF bias topics, see sibling pages.
Why Wideband PSRR
Switching rails carry base, harmonics, beat, and spread-spectrum energy that often lands in 10 kHz–10 MHz. Layout parasitics and ground return can bypass the LDO so remote nodes see higher ripple. A wideband high-PSRR LDO plus correct integration keeps the rail clean.
Spectrum realities
Base & harmonics (fsw,2f,3f), beat |f1−f2|, burst/PFM, spread-spectrum → energy spreads into 10 kHz–MHz.
System coupling
Long traces, poor AGND-PGND tie, ESR drift, and bad Kelvin sense erode PSRR at the remote node.
What to specify
PSRR @ 10 kHz / 100 kHz / 1 MHz / 5 MHz / 10 MHz under fixed VIN, VOUT, ILOAD, and Cout/ESR.
Hold it in the real world
Verify with sweep injection, load steps, cable A/B, and spread-spectrum on/off; measure at remote node.
- Specify PSRR at 10 kHz / 100 kHz / 1 MHz / 5 MHz / 10 MHz under fixed VIN, VOUT, ILOAD, Cout/ESR.
- Measure at remote node; compare spread-spectrum on/off; include load-step and cable A/B.
- Keep Cout at the load; single-point AGND-PGND; avoid creating an inner loop at sense RC.
Mechanisms Behind PSRR
Inside an LDO, the error amplifier (EA), loop bandwidth, transmission zeros/poles, and package/ESR effects together set how far PSRR extends into the MHz range and why it may collapse on real boards.
EA & UGF
gm-EA and higher UGF improve mid/high-band PSRR but tighten stability; verify phase margin >45° (prefer >60°) with target Cout/ESR.
ESR Zero
An ESR zero can lift mid-band PSRR; drift with bias/temperature moves the zero and can reduce MHz suppression.
Package/Parasitics
Lead/trace inductance with Cout may form MHz bumps; bad AGND–PGND return pollutes EA reference.
Sense & Feedforward
Avoid turning the sense RC into a hidden inner loop; use feedforward only within the stable ESR window.
Data-Sheet Reading Guide
Read PSRR plots with conditions first (VIN, VOUT, ILOAD, Cout/ESR, temperature, package). Extract values at 10 kHz · 100 kHz · 1 MHz · 5 MHz · 10 MHz, then check hold under VIN/ILOAD/Temp and package/board differences.
Reading steps (copy & run)
- Confirm conditions: VIN, VOUT, ILOAD, Cout/ESR, temperature, package/board.
- Extract PSRR at 10 kHz · 100 kHz · 1 MHz · 5 MHz · 10 MHz.
- Check hold under VIN/ILOAD sweeps and temperature corners; compare packages.
- Spot artifacts near ESR zero and any MHz bump from package/trace parasitics.
- Write a spec: Cout/ESR window, stability margin, remote-node verification method.
| PN (Brand) | Test Conditions (VIN/VOUT/ILOAD/Cout-ESR/Temp/Package) | PSRR@10k | @100k | @1M | @5M | @10M | Notes |
|---|---|---|---|---|---|---|---|
| — | VIN= — , VOUT= — , ILOAD= — , Cout/ESR= — , Temp= — , Pkg= — | — dB | — dB | — dB | — dB | — dB | ESR window / UGF hint |
Design Rules
Keep wideband PSRR by aligning compensation, feedback, feedforward, and the Cout/ESR window with stability targets. Design for the MHz range, then verify at the remote node.
Compensation
Target UGF for bandwidth; keep phase margin >45° (prefer >60°) with the intended Cout/ESR window.
Feedback (FB)
Place the divider close to the LDO and a clean AGND; avoid long traces that introduce unwanted zeros/poles.
Feedforward
Use to lift mid-band; ensure it does not create an MHz peak. Tune with the comp network, not against it.
Cout & ESR Window
Specify min/typ/max Cout and effective ESR under bias/temperature; place Cout at the load (≤10 mm).
Checklist
- Target UGF for MHz PSRR; verify PM >45° with intended Cout/ESR.
- Place FB divider near LDO; clean AGND; short traces.
- Use feedforward to lift mid-band; no MHz peaking.
- Specify min/typ/max Cout and effective ESR; Cout at the load.
- Measure at the remote node; compare spread-spectrum on/off.
Ripple Sources & Tracking
Switching rails contain base & harmonics, beat, burst/PFM, and spread-spectrum energy. Mark what is in-band (attenuated by the LDO) vs out-of-band (needs layout/shielding or a secondary filter).
Base & Harmonics
fsw, 2f, 3f… If peaks fall in-band, set UGF/ESR window to cover; if out-of-band, reduce coupling or filter.
Beat
|f1−f2| often lands 10 kHz–100s kHz. Phase/clock plan first; then spread if needed.
Burst / PFM
Envelope and sub-harmonics raise low-mid band. Add minimum load or adjust mode boundaries.
Spread-Spectrum
Smears energy; may leak out-of-band. Compare on/off at the remote node before deciding.
| Freq / Feature | Amplitude @ Local | Amplitude @ Remote | In-band / Out-of-band | Condition (Spread/Load/Temp) | Likely Cause | Action |
|---|---|---|---|---|---|---|
| — (e.g., 500 kHz, 2f) | — | — | In-band / Out-of-band | Spread on/off; load step %; temp | Package bump / long trace / ESR | Adjust UGF/ESR; shorten trace; shield |
Mitigation decisions
- In-band high → tune comp/UGF, correct ESR window, add remote Cout.
- Out-of-band high → reroute/shorten trace, shield, add secondary filter, or shift fsw.
- Beat → change phase/clock plan first, then consider spread.
- Burst/PFM → raise min load or stabilize mode boundary.
Stability & Loop Interaction
Keep wideband PSRR intact by preventing hidden inner loops and extra zeros/poles. Sense/FB RC must not become another loop; align ESR zero, UGF, and remote Cout so the main loop stays dominant.
Do: Single-Point AGND
Tie EA reference at one point to PGND. Keep high-current return out of the EA path.
Do: Remote Cout
Place Cout at the load. Ensure total ESR/ESL stays within the stability window.
Don’t: Sense RC Inner Loop
If you filter FB, keep fRC ≳ 5×UGF or move it before the clean reference node.
Don’t: Stack Resonances
Avoid placing ESR zero or trace/package resonance near UGF (no MHz bump).
Quick self-check
- UGF/PM measured at target Cout/ESR (PM >45°, prefer >60°).
- No sense/FB RC forming an extra loop (fRC ≳ 5×UGF).
- ESR zero and remote resonance not near UGF; no MHz bump.
- Single-point AGND; EA reference path is ripple-free.
- Remote-node PSRR verified vs spread on/off and load steps.
Application Scenarios
Six common analog domains benefit from 10 kHz–10 MHz PSRR. For each, specify key frequency points, layout essentials, and a remote-node validation plan before part selection.
Imaging ADC / Reference
Band: 1–5 MHz + spurs
Min spec: PSRR ≥ X dB @ 100k/1M/5M; PM >60°
Layout: Cout at ADC pin; quiet AGND
Validation: FFT at remote node; exposure switch
Low-Noise Preamp
Band: 10 kHz–1 MHz
Min spec: PSRR ≥ X dB @ 10k/100k/1M
Layout: FB near LDO; star AGND
Validation: EIN vs spread on/off
Sensor Bridge / Front-End
Band: 10 kHz–500 kHz
Min spec: PSRR ≥ X dB @ 10k/100k/500k
Layout: Kelvin to bridge; split CM
Validation: temp corners; zero drift vs step
PLL / Clock
Band: 100 kHz–10 MHz
Min spec: PSRR ≥ X dB @ 100k/1M/10M
Layout: isolate from RF loop
Validation: phase-noise sidebands
IF / Baseband
Band: 100 kHz–5 MHz
Min spec: PSRR ≥ X dB @ 100k/1M/5M
Layout: orthogonal to RF path
Validation: ACP/adjacent-channel ratio
Precision Ref / Buffer
Band: 10 kHz–1 MHz (+ spur)
Min spec: PSRR ≥ X dB @ 10k/100k/1M
Layout: star return; short trace
Validation: line/load regulation vs temp/spread
| Scenario | Key Band | PSRR Targets (10k / 100k / 1M / 5M / 10M) | Layout Essential | Validation Note |
|---|---|---|---|---|
| Imaging ADC / Ref | 1–5 MHz + spur | — / — / — / — / — dB | Cout at ADC pin; star AGND | Remote FFT; exposure switch |
| Low-Noise Preamp | 10 kHz–1 MHz | — / — / — / — / — dB | FB near LDO; short trace | EIN vs spread |
| Sensor Bridge | 10 kHz–500 kHz | — / — / — / — / — dB | Kelvin sense; split CM | Temp corners; zero drift |
| PLL / Clock | 100 kHz–10 MHz | — / — / — / — / — dB | Isolate from RF loop | Sidebands vs spread |
| IF / Baseband | 100 kHz–5 MHz | — / — / — / — / — dB | Orthogonal routing | ACP comparison |
| Precision Ref / Buffer | 10 kHz–1 MHz | — / — / — / — / — dB | Star return; short trace | Line/load vs temp |
Validation Playbook
Validate wideband PSRR at the remote node: sweep injection, compare remote vs local spectra, run load steps, repeat with cable/fixture A/B, and scan thermal hotspots. Log Vload error and compensation % for A/B decisions.
1) Injection Sweep
Inject small-signal; capture UGF/PM and PSRR baseline up to 10 MHz.
2) Remote vs Local
FFT both nodes and compute ΔPSRR; keep probe/ground identical.
3) Load Steps
10–50% Iload; log overshoot/settling and spread on/off delta.
4) Cable A/B
Swap cables/fixture; confirm peaks are not test artifacts.
5) Thermal Hotspots
Scan EA/pass/Cout/load; correlate MHz bumps with ΔT.
| Freq / Feature | Amp @ Local | Amp @ Remote | In-band / Out-of-band | Condition (Spread/Load/Temp) | Likely Cause | Action |
|---|---|---|---|---|---|---|
| 500 kHz (2f) | — | — | In-band | Spread off; 20% step | Trace ESL / ESR window | Tune UGF/ESR; add remote MLCC |
| 5 MHz (bump) | — | — | Out-of-band | Spread on; 40% step | Package/trace resonance | Shorten route; shield; 2nd filter |
| Case | Comp % | UGF / PM | PSRR @ 100k/1M/5M/10M | Vload error (mVpp) | ΔT (°C) |
|---|---|---|---|---|---|
| Baseline | 0% | — / —° | — / — / — / — dB | — | — |
| After tuning | +10% | — / —° | — / — / — / — dB | — | — |
Pass criteria (copy & use)
- UGF/PM meet target under intended Cout/ESR; no MHz bump near UGF.
- ΔPSRR(remote−local) meets scenario goals at 10k/100k/1M/5M/10M.
- Vload error within limit on 10–50% load steps; no long tail.
- Results repeat with cable/fixture A/B and spread on/off.
- No thermal hotspot correlated with spectral peaks.
Layout Checklist
Preserve wideband PSRR with single-point AGND–PGND tie, tight decoupling at the load, Kelvin sense, and shielded routing. Verify with the same remote-node metrics used in validation.
G1: AGND–PGND One Point
Tie near the reference pin; keep high-current return off the EA path.
G2: Tight Decoupling
Place MLCC between LDO and load pins; Cout ≤10 mm from the load.
G3: Kelvin Sense
Sense remote node with paired traces; guard to AGND where needed.
G4: Routing & Shielding
Orthogonal power vs sensitive RF/analog; add ground fence/plane.
G5: Parasitics
Check Ltrace×Cout resonance; offset ESR zero from UGF.
Layout self-check (copy & use)
- AGND–PGND tied at one point near reference; EA path is quiet.
- MLCC loop between LDO and load is tight; Cout ≤10 mm from load.
- Kelvin sense to the remote node; short, parallel, guarded traces.
- Power vs sensitive routing is orthogonal/isolated with ground fence.
- Ltrace×Cout resonance kept away from UGF; no MHz bump.
Mini IC-Selection Pointers (Seven Brands)
Example PNs added for quick screening; final choices must be verified against official datasheets and your stability/PSRR validation plan. Avoid cross-page overlap by keeping notes scenario-specific.
| Brand | Use_Cases | PSRR_Targets (10k/100k/1M/5M/10M dB) | Output_Noise | Iq_Typ | Vin / Vout Range | Iout_Max | Dropout@Iout | Stability_Window (C/ESR) | Features | Temp_Grade | Package | Notes (Example PN) | Datasheet_URL |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Texas Instruments | Imaging ADC / Reference | ≥80 / ≥70 / ≥50 / ≥40 / ≥35 | ultra-low | low | wide / 0.6–5.5 | 1 A | typ 150 mV | MLCC; ESR window per DS | wide-band EA; PG | -40~+125 | WSON | TPS7A94 — RF/PLL/Imaging wideband PSRR | TI PDF |
| Low-Noise Preamp | ≥70 / ≥65 / ≥45 / ≥35 / ≥30 | ultra-low | low | wide / 0.6–5.5 | 1 A | typ 150 mV | MLCC; ESR window per DS | enable; PG | -40~+125 | WSON | TPS7A94 — mic/AFE sensitive rails | TI page | |
| Sensor Bridge | ≥70 / ≥65 / ≥45 / ≥35 / ≥30 | ultra-low | low | wide / 0.6–5.5 | 1 A | typ 150 mV | MLCC; ESR window per DS | remote sense ready | -40~+125 | WSON | TPS7A94 — Kelvin sense layout | TI PDF | |
| PLL / Clock | ≥75 / ≥70 / ≥50 / ≥40 / ≥35 | ultra-low | low | wide / 0.6–5.5 | 1 A | typ 150 mV | MLCC; ESR window per DS | low spur | -40~+125 | WSON | TPS7A94 — sideband sensitive | TI page | |
| IF / Baseband | ≥65 / ≥60 / ≥45 / ≥35 / ≥30 | very low | low | wide / 0.6–5.5 | 1 A | typ 150 mV | MLCC | PG; enable | -40~+125 | WSON | TPS7A52 — higher current alt | TI page | |
| Precision Ref / Buffer | ≥75 / ≥65 / ≥45 / ≥35 / ≥30 | ultra-low | low | wide / 0.6–5.5 | 1 A | typ 150 mV | MLCC | soft-start | -40~+125 | WSON | TPS7A94 — ref/buffer cleanup | TI PDF | |
| STMicroelectronics | Imaging ADC / Reference | ≥70 / ≥60 / ≥40 / ≥30 / ≥25 | very low | very low | 1.5–5.5 / fixed | 250 mA | low | ceramic; ESR per DS | enable | -40~+125 | DFN/SOT | LDLN025 — high PSRR & low noise | ST PDF |
| Low-Noise Preamp | ≥65 / ≥55 / ≥38 / ≥28 / ≥22 | very low | very low | 1.5–5.5 / fixed | 250 mA | low | ceramic | PG opt | -40~+125 | DFN/SOT | LDLN025 — mic/AFE | ST PDF | |
| Sensor Bridge | ≥65 / ≥55 / ≥38 / ≥28 / ≥22 | very low | very low | 1.5–5.5 / fixed | 250 mA | low | ceramic | remote friendly | -40~+125 | DFN/SOT | LDLN025 — Kelvin sense routing | ST PDF | |
| PLL / Clock | ≥70 / ≥60 / ≥40 / ≥30 / ≥25 | very low | very low | 1.5–5.5 / fixed | 250 mA | low | ceramic | VCO friendly | -40~+125 | DFN/SOT | LDLN025 — clock rails | ST PDF | |
| IF / Baseband | ≥60 / ≥50 / ≥35 / ≥25 / ≥20 | low | very low | 1.5–5.5 / fixed | 500 mA | mod | ceramic | LDLN050 alt | -40~+125 | DFN | LDLN050 — higher current alt | ST PDF | |
| Precision Ref / Buffer | ≥70 / ≥60 / ≥40 / ≥30 / ≥25 | very low | very low | 1.5–5.5 / fixed | 250 mA | low | ceramic | enable | -40~+125 | DFN/SOT | LDLN025 — ref/buffer cleanup | ST PDF | |
| NXP | Imaging ADC / Reference | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.3–5.5 / fixed | 150 mA | mod | ceramic | enable | -40~+85/125 | TSOP5 | LD6805 — high-PSRR LDO family | NXP PDF (dist.) |
| Low-Noise Preamp | ≥58 / ≥52 / ≥34 / ≥24 / ≥18 | low | low | 2.3–5.5 / fixed | 150 mA | mod | ceramic | — | -40~+85/125 | TSOP5 | LD6815 — family alt | NXP PDF (dist.) | |
| Sensor Bridge | ≥58 / ≥52 / ≥34 / ≥24 / ≥18 | low | low | 2.3–5.5 / fixed | 150 mA | mod | ceramic | — | -40~+85/125 | TSOP5 | LD6805 — remote clean rail | NXP PDF (dist.) | |
| PLL / Clock | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.3–5.5 / fixed | 150 mA | mod | ceramic | — | -40~+85/125 | TSOP5 | LD6805 — clock rails | NXP PDF (dist.) | |
| IF / Baseband | ≥55 / ≥50 / ≥32 / ≥24 / ≥18 | low | low | 2.3–5.5 / fixed | 150 mA | mod | ceramic | — | -40~+85/125 | TSOP5 | LD6815 — baseband alt | NXP PDF (dist.) | |
| Precision Ref / Buffer | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.3–5.5 / fixed | 150 mA | mod | ceramic | — | -40~+85/125 | TSOP5 | LD6805 — ref/buffer alt | NXP PDF (dist.) | |
| Renesas | Imaging ADC / Reference | ≥70 / ≥60 / ≥40 / ≥30 / ≥25 | very low | low | 2.3–6.5 / fixed | 300 mA | mod | 1–10 µF; ESR ≤0.2Ω | BP pin | -40~+85/125 | DFN/SOT | ISL9001A — high PSRR, BP for low noise | Renesas PDF |
| Low-Noise Preamp | ≥65 / ≥58 / ≥38 / ≥28 / ≥22 | very low | low | 2.3–6.5 / fixed | 300 mA | mod | 1–10 µF | BP pin | -40~+85/125 | DFN/SOT | ISL9001A — mic/AFE | Renesas page | |
| Sensor Bridge | ≥65 / ≥58 / ≥38 / ≥28 / ≥22 | very low | low | 2.3–6.5 / fixed | 300 mA | mod | 1–10 µF | BP pin | -40~+85/125 | DFN/SOT | ISL9001A — remote bridge rails | Renesas PDF | |
| PLL / Clock | ≥70 / ≥60 / ≥40 / ≥30 / ≥25 | very low | low | 2.3–6.5 / fixed | 300 mA | mod | 1–10 µF | BP pin | -40~+85/125 | DFN/SOT | ISL9001A — clock rails | Renesas page | |
| IF / Baseband | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.3–6.5 / fixed | 300 mA | mod | 1–10 µF | BP pin | -40~+85/125 | DFN/SOT | ISL9001A — baseband | Renesas PDF | |
| Precision Ref / Buffer | ≥70 / ≥60 / ≥40 / ≥30 / ≥25 | very low | low | 2.3–6.5 / fixed | 300 mA | mod | 1–10 µF | BP pin | -40~+85/125 | DFN/SOT | ISL9001A — ref/buffer cleanup | Renesas page | |
| onsemi | Imaging ADC / Reference | ≥65 / ≥60 / ≥40 / ≥30 / ≥25 | very low | very low | 1.9–5.5 / fixed | 450 mA | mod | 1 µF ceramic | low noise, high PSRR | -40~+125 | TSOP/XDFN | NCV8161 — RF/analog | onsemi page |
| Low-Noise Preamp | ≥60 / ≥55 / ≥38 / ≥28 / ≥22 | very low | very low | 1.9–5.5 / fixed | 450 mA | mod | 1 µF ceramic | — | -40~+125 | TSOP/XDFN | NCV8161 — mic/AFE | onsemi page | |
| Sensor Bridge | ≥60 / ≥55 / ≥38 / ≥28 / ≥22 | very low | very low | 1.9–5.5 / fixed | 450 mA | mod | 1 µF ceramic | Kelvin friendly | -40~+125 | TSOP/XDFN | NCV8161 — bridge rails | onsemi PDF | |
| PLL / Clock | ≥65 / ≥60 / ≥40 / ≥30 / ≥25 | very low | very low | 1.9–5.5 / fixed | 450 mA | mod | 1 µF ceramic | — | -40~+125 | TSOP/XDFN | NCV8161 — clock rails | onsemi page | |
| IF / Baseband | ≥58 / ≥53 / ≥35 / ≥25 / ≥20 | low | very low | 1.9–5.5 / fixed | 450 mA | mod | 1 µF ceramic | — | -40~+125 | TSOP/XDFN | NCV8161 — baseband | onsemi PDF | |
| Precision Ref / Buffer | ≥65 / ≥60 / ≥40 / ≥30 / ≥25 | very low | very low | 1.9–5.5 / fixed | 450 mA | mod | 1 µF ceramic | — | -40~+125 | TSOP/XDFN | NCV8161 — ref/buffer | onsemi page | |
| Microchip | Imaging ADC / Reference | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.5–5.5 / fixed | 300 mA | mod | ceramic | auto-discharge | -40~+125 | DFN | MIC5504 — compact high-PSRR | Microchip page |
| Low-Noise Preamp | ≥58 / ≥52 / ≥34 / ≥24 / ≥18 | low | low | 2.5–5.5 / fixed | 300 mA | mod | ceramic | auto-discharge | -40~+125 | DFN | MIC5504 — mic/AFE | Microchip page | |
| Sensor Bridge | ≥58 / ≥52 / ≥34 / ≥24 / ≥18 | low | low | 2.5–5.5 / fixed | 300 mA | mod | ceramic | auto-discharge | -40~+125 | DFN | MIC5504 — bridge rails | Microchip page | |
| PLL / Clock | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.5–5.5 / fixed | 300 mA | mod | ceramic | auto-discharge | -40~+125 | DFN | MIC5504 — clock rails | Microchip page | |
| IF / Baseband | ≥55 / ≥50 / ≥32 / ≥22 / ≥18 | low | low | 2.5–5.5 / fixed | 300 mA | mod | ceramic | auto-discharge | -40~+125 | DFN | MIC5504 — baseband | Microchip page | |
| Precision Ref / Buffer | ≥60 / ≥55 / ≥35 / ≥25 / ≥20 | low | low | 2.5–5.5 / fixed | 300 mA | mod | ceramic | auto-discharge | -40~+125 | DFN | MIC5504 — ref/buffer | Microchip page | |
| Melexis | Imaging ADC / Reference | (pair with external high-PSRR LDO) | — | — | — | — | — | — | Sensors often integrate regulators | — | — | Use TI/ST/Renesas LDO upstream; e.g., MLX90290 integrates regulator | Melexis PDF |
| Low-Noise Preamp | (use external LDO) | — | — | — | — | — | — | — | — | — | Pair with wideband PSRR LDO upstream | Melexis site | |
| Sensor Bridge | (use external LDO) | — | — | — | — | — | — | — | — | — | Kelvin to sensor ground domain | Melexis site | |
| PLL / Clock | (use external LDO) | — | — | — | — | — | — | — | — | — | External LDO recommended | Melexis site | |
| IF / Baseband | (use external LDO) | — | — | — | — | — | — | — | — | — | External LDO recommended | Melexis site | |
| Precision Ref / Buffer | (use external LDO) | — | — | — | — | — | — | — | — | — | Use wideband PSRR LDO upstream | Melexis site |
Frequently Asked Questions
What PSRR numbers matter for imaging ADC rails at 1–5 MHz?
Prioritize remote-node PSRR at 1 MHz and 5 MHz, verified with identical probe setup on local vs remote nodes. Set scenario targets (e.g., ≥X dB @1 MHz, ≥Y dB @5 MHz) and confirm stability via UGF/PM from injection sweeps. See Application Scenarios and Validation.
How do I read PSRR plots across frequency, VIN ripple, load, and temperature?
Compare curves vs frequency at fixed load and VIN first, then observe shifts with load/temperature. Identify knees where attenuation drops. Align ESR zero below UGF and confirm the same bandwidth in your test. Start at Data-Sheet Guide and Design Rules.
Where should sense/FB RC sit so it won’t form a hidden inner loop?
Keep the RC before a clean reference node or place its corner at least five times the loop UGF (fRC ≧ 5×UGF). Avoid remote RC returning through noisy grounds. Validate by load-step settling and PSRR around the knee. See Stability.
Does spread-spectrum on the DC-DC help or hurt in-band PSRR?
It flattens narrow spurs but can push energy into your LDO’s effective band. Compare spectra with spread on/off at the remote node and check ΔPSRR vs targets. Keep MHz bump away from UGF. See Ripple Tracking and Validation.
What is a safe ESR/Cap window to keep wideband attenuation?
Use the vendor’s stability window for Cout and ESR, placing the ESR zero comfortably below UGF. Verify with injection sweeps and remote FFT; if you see a MHz bump, shift ESR or reduce trace inductance. See Design Rules.
How do I size Cout and route Kelvin sense for maximum PSRR?
Place Cout at the load with a tight MLCC loop; sense the remote node using short, paired traces and optional AGND guard. Keep power and sensitive routes orthogonal. Confirm ΔPSRR(remote-local) improvement. See Layout.
Which metrics decide pass/fail in validation?
Judge UGF/PM against targets, ΔPSRR(remote−local) at 10k/100k/1M/5M/10M, and Vload error on 10–50% steps. Repeat with cable A/B and spread on/off to confirm robustness. See Validation.
When do I need a differential-sense LDO vs a standard LDO?
Use differential-sense when remote routing adds significant drop/inductance or the load is highly ripple-sensitive (imaging, PLL). It maintains regulation at the remote node and improves PSRR consistency. Check EA bandwidth and stability window. See Mechanisms and IC-Selection.
Can a post-LDO RC/LC filter help without risking instability?
It can attenuate out-of-band content but may add poles/zeros near UGF. Place the filter so its corner avoids the control bandwidth and verify with injection sweeps and remote FFT. Watch for longer settling tails. See Stability and Design Rules.
How do temperature and load current shift PSRR knees?
Higher temperature and heavier load often push the knee lower and reduce peak attenuation. Compare PSRR curves across corners and confirm with your remote-node setup. Adjust ESR window or UGF as needed. See Data-Sheet Guide and Scenarios.
How do I compare vendors with different PSRR bandwidths?
Normalize conditions: same VIN ripple level, load, temperature, and measurement bandwidth. Interpolate at your scenario points (10k/100k/1M/5M/10M) and validate at the remote node. Use a common pass/fail checklist. See Data-Sheet Guide and IC-Selection.
How do I avoid test-fixture artifacts (cable A/B) that fake a MHz bump?
Repeat tests with two cable/fixture setups, keeping probe geometry identical. If a peak shifts with the fixture, treat it as an artifact. Shorten routes, add shielding, or adjust termination to confirm. See Validation.
What PSRR targets are realistic for PLL/clock rails?
Aim for robust attenuation at 100 kHz and 1 MHz, then quantify at 10 MHz if the clocking chain is sensitive. Sidebands drive audible/visible artifacts; validate with phase-noise measurement tied to the remote rail. See Scenarios.
Does feedforward improve wideband PSRR or only load transients?
Feedforward mainly helps transient response; its wideband PSRR impact depends on pole/zero placement. If it creates a near-UGF zero, you may degrade stability. Validate via injection and remote FFT after enabling feedforward. See Mechanisms and Design Rules.
How do I plan AEC-Q100 variants and temperature grades without changing stability?
Keep the same Cout/ESR window and verify PSRR at temperature corners. If package or grade changes parasitics, re-check UGF/PM and remote ΔPSRR. Prefer parts with documented stability windows across grades. See IC-Selection and the LDO hub.
