Introduction & Scope
Use a post-reg LDO after a buck when you must attenuate specific spectral lines—at fsw, 2fsw, or beat notes—beyond what the buck + LC can achieve, and when the VDO × Iload power loss and thermal rise are within budget.
Spectral Problem Definition
The target is not broadband noise but lines in the spectrum: fsw, 2fsw, beat notes (|f1−f2|), and spread-spectrum energy. Size PSRR at those frequencies, then check Ploss = VDO × Iload and stability under ripple.
Selection Criteria
Decide with PSRR@f targets and thermal/efficiency limits: compute required attenuation at fsw, 2fsw, and beat notes; then check Ploss=VDO×Iload, ΔT and η. Verify Iq at light load and Iout headroom.
- Compute PSRR_req(f) from V_in_ripple(f) and V_out_allow(f); check at f_sw / 2f_sw / beat.
- Thermal: P_loss = VDO × I_load; ΔT ≈ P_loss × RθJA (verify on board).
- Efficiency: η_total ≈ η_buck × (V_out/(V_out+VDO)) (first-order).
- Iq at light load (battery/idle) and I_out headroom at temperature.
- If cand < req at any f → try lower-VDO LDO / add LCπ / force PWM / re-phase source.
Stability Under Ripple
Under ripple at fsw/harmonics/beat, keep the loop stable: stay inside the vendor C/ESR window, mind phase margin near target f, and ensure pre-bias safety, active discharge and reverse-current behavior are correct.
- Keep inside the vendor C/ESR window (consider DC bias and temperature).
- Phase margin ≥ 45–60° near f_sw / 2f_sw / beat; verify under injected ripple.
- Pre-bias safe, Active Discharge, and Reverse-Current behavior confirmed at power-up/down.
- Light-load mode changes (PFM↔PWM) should not trigger ringing or PG chatter.
Verification Playbook
Verify spectral residuals and PSRR@target frequencies across load, then confirm thermal and efficiency. Finish with an A/B comparison and a release matrix.
- Spectrum: before/after at f_sw, 2f_sw, beat; fixed RBW/window; note I_load & temperature.
- PSRR@f: 10% / 50% / 100% I_load (room + high-T).
- Thermal: P_loss = VDO × I; ΔT ≈ P_loss × RθJA; η_total impact.
- Stability: ripple-in, C/ESR window, pre-bias safe, AD/RCB, PG chatter.
- A/B: compare PSRR@f, P_loss, ΔT, η, pre-bias, BOM, layout complexity.
Mini IC Matrix (Real Parts)
Real, production LDOs commonly used as post-reg after buck. Focus on PSRR at target frequencies, VDO, Iout, Iq, and stability window. Final selection must follow the datasheet.
| Brand | PN | I_out(max) | V_in(min/max) | V_out(range) | VDO@I (note) | I_q (typ) | PSRR@f tag | Stability window (C/ESR) | Pre-bias / AD / RCB | Pkg / RθJA | Notes (Post-Reg fit) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| TI | TPS7A94 | ≈1 A | datasheet | datasheet | low; check at load | low | Suitable @f_sw/2f_sw/1 MHz* | MLCC window | Pre-bias Y / AD opt / RCB note | see DS | Low-noise, high-PSRR line; good for clock/RF rails. |
| TI | TPS7A85A | ≈4 A | datasheet | datasheet | very low | moderate | Check @1 MHz | C/ESR per DS | Pre-bias Y / AD opt | see DS | High current post-reg; watch ΔT. |
| TI | TPS7A8300 | ≈2 A | datasheet | datasheet | low | low | Suitable @f_sw/2f_sw* | MLCC window | Pre-bias Y | see DS | Popular for mixed-signal rails. |
| TI | TPS7A20 | ≈1 A | datasheet | datasheet | low | very low | Check @1 MHz | C/ESR per DS | Pre-bias Y | see DS | Compact, low noise; good general post-reg. |
| ST | LD39200 | ≈2 A | datasheet | datasheet | low | moderate | Suitable @f_sw; Check @1 MHz | MLCC/ESR window | Pre-bias Y / AD option | see DS | Stronger for higher current post-reg rails. |
| ST | LDLN050 | ≈50 mA | datasheet | datasheet | very low | very low | Suitable @1 MHz* | MLCC window | Pre-bias Y | see DS | Low-noise small rails (clocks/PLLs). |
| ST | LDLN300 | ≈300 mA | datasheet | datasheet | low | low | Suitable @f_sw; Check @2f_sw | MLCC window | Pre-bias Y | see DS | General purpose post-reg for analog zones. |
| Renesas | ISL80101A | ≈1 A | datasheet | datasheet | low | moderate | Suitable @f_sw; Check @1 MHz | C/ESR per DS | Pre-bias Y | see DS | Robust transient; watch high-f PSRR region. |
| Renesas | ISL78322 | auto-grade | datasheet | datasheet | low | low | Check @1 MHz | Automotive window | Pre-bias Y | see DS | AEC-Q; good for harsh env post-reg. |
| onsemi | NCV8161 | ≈250 mA | datasheet | fixed/adj (DS) | low | very low | Suitable @f_sw; Check @beat | MLCC window | Pre-bias Y / AD opt | see DS | Automotive small rails (MCU/RF). |
| onsemi | NCP167 | ≈700 mA | datasheet | adj (DS) | low | low | Check @1 MHz | C/ESR per DS | Pre-bias note | see DS | Balance PSRR/efficiency for mid-current. |
| onsemi | NCP718 | ≈300 mA | datasheet | fixed/adj (DS) | low | very low | Suitable @f_sw; Check @2f_sw | MLCC window | Pre-bias Y | see DS | Cost-friendly general post-reg. |
| Microchip | MIC5504 | ≈300 mA | datasheet | fixed (DS) | low | very low | Check @1 MHz | Small MLCC | Pre-bias note | see DS | Compact, good for tight spaces. |
| Microchip | MIC5353 | ≈1 A | datasheet | fixed/adj (DS) | low | low | Suitable @f_sw; Check @beat | MLCC window | Pre-bias Y | see DS | 1 A class; budget ΔT carefully. |
| Microchip | MCP1826S | ≈1 A | datasheet | fixed/adj (DS) | moderate | low | Check @high-f | C/ESR per DS | Pre-bias note | see DS | Robust; confirm high-f PSRR vs need. |
*PSRR suitability tags are for screening. Use the Verification Playbook to confirm at your f_sw / 2f_sw / beat and operating conditions.
FAQs (PAA style)
Engineer-tone answers (45–70 words each). Each gives a decision rule, quick formula, and a copy-paste checklist tied to post-reg after buck use only.
When should I add an LDO after a buck?
Add post-reg if residual at target bands exceeds your allowables, or sensitive rails need isolation. Compute PSRR_req(f)=20·log10(Vin_ripple/Vout_allow) at fsw, 2fsw, and beat. If any PSRR_req is above the candidate’s curve (de-rated for load/temperature), use LDO or LCπ. Checklist: target-band limits, PSRR curves, VDO·I thermal budget.
How do I calculate PSRR targets at fsw/2fsw/beat?
Measure or estimate ripple spectrum at the LDO input, define allowed output levels per band, then compute PSRR_req(f). Use RBW and window consistently across runs. De-rate datasheet PSRR by 5–15 dB for real boards and cross-load. Checklist: Vin_ripple(f), Vout_allow(f), PSRR_req table, de-rate margin, cross-load points (10/50/100%).
Does spread-spectrum make post-reg easier or harder?
It lowers peaks but widens energy, so a narrow PSRR notch helps less. Verify integrated noise over the dither band and check worst-case sub-peaks. Rule: keep phase margin ≥45–60° near the dither band. Checklist: dither width, PSD before/after, PSRR vs frequency sweep, stability at edges, PG chatter.
LCπ vs LDO—when to choose which? Can I combine them?
Use LCπ when loss must be minimal and ripple is narrowband; use LDO when broadband attenuation and isolation are required. Combo: LCπ first to reduce amplitude, then LDO with modest VDO. Guard against resonance and startup interaction. Checklist: attenuation split, Q damping (RC), LDO ESR window, startup order.
How do I budget ΔT and efficiency hit from VDO?
Use P_loss=VDO×I_load, then ΔT≈P_loss·RθJA and η_total≈η_buck·Vout/(Vout+VDO). Set limits per hotspot and system efficiency. If ΔT or η exceeds budget, try lower-VDO LDO, reduce I_load through duty, or shift attenuation to LCπ. Checklist: VDO@I, RθJA, hotspot cap, η floor.
Light-load battery mode: when does Iq become unacceptable?
If P_q=I_q·Vin exceeds 10–20% of total rail power in standby, switch to a lower-Iq LDO or gate the LDO with load-dependent enable. Consider pre-reg PWM-only mode if it reduces beat content. Checklist: I_q at temp, enable policy, wake-latency tolerance, A/B life-estimate with duty cycle.
Will pre-bias cause lock-up? What features do I need?
Choose parts marked pre-bias safe and verify AD (active discharge) and RCB (reverse-current behavior) in power-up/down tests. Delay PG until regulation is solid. Checklist: pre-bias waveform, AD slope, RCB limits, PG delay vs downstream thresholds, reverse flow during faults.
How to avoid resonance or instability with Cout/ESR under ripple?
Stay inside the vendor C/ESR window, account for MLCC DC-bias and temperature, and add a small RC damper if ringing appears. Keep margin near target bands. Checklist: effective C at bias, ESR window, ripple-in stability test, damper footprint, phase-margin spot checks at fsw/2fsw/beat.
PFM↔PWM transitions cause spikes or PG chatter—what to do?
Force the pre-reg into PWM in sensitive states or widen the LDO’s stability margin around the transition band. Debounce PG and verify with injected ripple. Checklist: mode pin policy, transition frequency vs PSRR valley, PG debounce, pre-bias test, spread-spectrum interaction.
If PSRR near 1 MHz is short, what should I try first?
First, move attenuation to the source: force PWM, shift phase, or raise fsw if feasible. Second, add LCπ with damping. Third, pick an LDO whose PSRR peak aligns with the band. Checklist: source controls, LCπ Q, candidate PSRR map, ΔT/η impact after changes.
Will multiple post-reg rails create local hotspots?
Yes—VDO·I converts to heat at each rail. Spread loads, route copper under packages, and place sensors near worst rails. Rule: keep hotspot <105 °C unless derated. Checklist: VDO map per rail, copper/thermal vias, airflow note, IR image at 50/100% loads, aggregation of ΔT.
How do I run a 48-hour A/B loop and reach a release decision?
Day 1: spectrum before/after, cross-load PSRR at target bands. Day 2: thermal/efficiency, ripple-in stability, pre-bias start/stop. Fill a matrix: PSRR@f, P_loss, ΔT, η, PG behavior, BOM/complexity. Gate: all bands meet PSRR_req and ΔT/η within budget. Output: Qualified/Conditional/Rejected.
When should I abandon post-reg and fix noise at the source?
If any target band needs >60–70 dB attenuation beyond feasible LDO curves, or ΔT/η penalty breaks system limits, fix the buck: mode/phase/frequency, compensation, or layout. Checklist: infeasible PSRR_req, ΔT over cap, η floor hit, source-side knobs inventory, fallback LCπ plan.
What do “PSRR@f tag / Stability window / Pre-bias” mean in the matrix?
PSRR@f tag screens suitability at your bands; confirm with measurement. Stability window states valid C/ESR ranges and notes for damping. Pre-bias lists start/stop safety and AD/RCB behavior. Checklist: match tags to fsw/2fsw/beat, pick C_out in-window, verify pre-bias/PG timing.
Share fsw/ripple allowables/Imax/package & thermal context (PWM/PFM/spread). You’ll get an A/B plan and a release matrix.
