EMI & Layout for Low Dropout Regulators (LDOs)
← Back to Low Dropout Regulators (LDOs)
1) Introduction & Scope (for LDO rails)
An LDO itself is not a switching source, but it can see upstream switching noise, can see ground voltage drops, and can see cable/automotive transients coming in from the connector. If the layout around the LDO is loose, these disturbances will leak straight to the sensitive load, no matter how good the PSRR in the datasheet is.
The purpose of this section is to help the LDO actually reach its datasheet PSRR/noise level by tightening the input/output loops, isolating the grounds, and putting the right filter in front of the device. We stay strictly at board / device level: nearby copper, caps, filter cells, sense traces.
This is not a full EMC/EMI certification guide (no CISPR/ISO test descriptions here). It is a layout and placement checklist to make LDO rails stable and quiet even when powered from a noisy or automotive source.
2) EMI Sources Around an LDO
Around a low dropout regulator, noise does not only come from the LDO itself. It mainly comes from what feeds it, from how big the current loops are, and from how the ground returns are mixed. Adding an LDO after a switching regulator does not magically remove all switching spikes if the layout is poor.
1) Upstream switching spikes
Fast dI/dt from a buck or noisy harness couples through the VIN pin when the last filter cap is not close to the LDO. Fix: TVS/π up front + local VIN MLCC.
2) LDO load transients
A wide output loop makes the OUT node radiate or inject into nearby traces. Fix: keep the OUT cap right at the LDO and route the load return short.
3) Asymmetric / noisy GND
Mixing power return and signal return will couple noise into FB/ADJ/EN. Fix: star GND at the LDO, keep sense pins local.
4) External cable / automotive transient
Long cables and vehicle harnesses inject fast events. Fix: put TVS / π filter before the LDO so the device only sees the cleaned rail.
3) Shortest IN / OUT Loops (Core Layout Rule)
Even though an LDO is linear, loop size still matters. Both the input and output capacitors must form tight, local loops with the LDO GND so that upstream switching spikes, local load steps, and harness noise do not spread across the board.
The input side must look like a small triangle: VIN → input MLCC → GND. The output side must look like the same triangle: VOUT → output MLCC → GND. If you add a C–L–C π filter in front of the LDO, the last capacitor of the π must sit close to the LDO, otherwise the LDO will still “see” the noise.
Smaller loop → lower stray inductance → less coupling into FB/EN/sense lines → easier to achieve datasheet-level PSRR/noise.
4) Star Grounding for LDO + Sensitive Loads
When an LDO feeds sensors, ADC references, or camera/lighting modules, not all ground returns should share the same noisy path. The LDO GND pad can act as a local star point: power ground from the upstream regulator joins here, and signal ground from the sensitive load also joins here. This way, switching currents do not pollute the reference seen by FB/EN/sense pins.
In tight automotive or camera modules where copper is limited, it is even more important to use “star thinking” instead of pouring one large ground. A single via or thermal pad can be the meeting point, as long as the power and signal returns are kept separate before that point.
1) Local star at LDO
Treat the LDO GND pad or exposed pad as the local star. Both power and signal returns terminate here.
2) Power ground path
Upstream DC/DC or π-filter return flows through the power ground path, away from FB/EN. Join at the star only.
3) Signal/sensor ground
Sensor, ADC, REF, MCU bias grounds run in a quieter path and join the LDO at the same star point.
5) Shield / Separate Sensitive Nodes
After we shorten the input/output loops and separate the grounds, the remaining EMI risk is what gets directly coupled into sensitive pins. On an LDO, the typical sensitive nodes are FB, ADJ, EN, PG/RESET, and SNS. These must be routed short, inside, and next to ground so that high dI/dt traces and switching nodes cannot inject noise.
Keep the feedback divider close to the LDO body, do not let it “float” far away. If the board is crowded with switching inductors or wide power traces, put a ground guard trace or ground copper on one side of the sensitive trace to shield it. This step is what makes your later “PSRR / Noise” pages actually valid on real hardware.
Sensitive nodes
FB, ADJ, EN, PG/RESET, SNS — these should stay in a quiet zone.
Routing rules
Route short, go to inner layer when needed, avoid SW/IND/high dI/dt traces.
Guard / shield
Add a ground line or copper on one side to isolate from noisy copper.
FB resistors
Place FB divider close to the LDO package; do not move it to the load.
6) TVS / π Filtering Up Front
When an LDO is powered from a noisy or automotive source (long cable, vehicle harness, upstream switching converter), do not feed the device directly. Clamp first, filter second, regulate last. The typical front-end order is:
Connector → TVS → π (C–L–C) → LDO VIN
The TVS is placed close to the connector to catch fast transients. The π filter then attenuates the remaining conducted noise. The last capacitor of the π must sit close to the LDO VIN pin, otherwise the filter will not deliver a clean rail to the regulator. Remember: an LDO is for linear regulation, not for absorbing surge energy.
7) Thermal vs EMI vs Layout Trade-offs
For LDOs on automotive or high-power boards, it is natural to spread copper for heat. But a single, unpartitioned copper pour can carry switching noise from the power region right into the LDO’s sensitive side (FB/EN/SNS). The rule is: copper can be large, but must be segmented — power island vs signal island, then join at a single LDO star.
Use via curtains, slots, or narrow ground bridges to keep the power return and the signal return apart. Keep hot/high dI/dt elements (inductors, FETs, pulsing copper) away from the LDO VIN and exposed pad, especially when ambient is high and OTP may trigger earlier.
Thermal spreading and EMI control are not in conflict — they just need copper zoning: big copper for heat, plus boundaries to stop noise from leaking into the signal zone.
8) Validation & Lab Checklist
To prove that the layout choices above (short loops, star ground, shielded nodes, front-end π) are working, do a fast bench validation. Probe with a short ground spring, compare signals with and without the π filter, apply load steps, and write the layout/filtering requirements into the BOM notes so procurement and external PCB shops honor them.
1) Power-up probing
Scope VIN and VOUT at the LDO pins with a short ground clip. Check spikes and repeatability.
2) A/B π filter
Measure with π in, then remove/short the π and measure again to prove the filter is effective.
3) Load step
Step 10–50% load, observe overshoot/undershoot and recovery; watch FB/EN for coupling.
4) Optional LISN
If available, do a quick board-level conducted noise check (not certification).
BOM / fabrication notes (paste into RFQ)
Layout: VIN/VOUT small triangles to LDO GND; split copper (power vs signal) with via curtain/slot; single local star at LDO EP.
Filtering: Connector → TVS → π (C-L-C) → LDO VIN; TVS must be by connector; π final C must be by LDO.
Sensitive: FB/ADJ/EN/PG/SNS routed short & inner; ground guard on one side; avoid SW/IND/high dI/dt traces.
Thermal: copper may be large but isolate power island from signal island; do not pack hot/high dI/dt near LDO VIN.
Validation: scope VIN/VOUT with short ground spring; A/B π filter; load step 10–50% rated I; save screenshots & scope setup.
9) Seven-Vendor Tie-In (LDO Layout-Relevant Features)
Many LDOs from the seven core automotive / industrial vendors actually say the same layout things we described in this page: keep input/output capacitors close, shield FB/EN/SNS, add front-end filtering for harness/long cables, and separate power from signal ground. Below is a vendor-to-part mapping you can reuse across your LDO subpages.
Texas Instruments (TI)
TPS7A66-Q1, TPS7A69-Q1, TPS7B83-Q1, TPS7A16-Q1
Layout notes: FB is high-impedance, keep close; VIN MLCC is mandatory; for battery/noisy inputs, pre-filter before VIN.
STMicroelectronics (ST)
LDL40, L99VR03, LD1117S33CTR
Layout notes: input capacitor close to VIN; when used off automotive battery, clamp and filter first; output capacitor at the regulator pin.
NXP
UJA1169TK, UJA1169ATK/X, MC33903, MC33905
Layout notes: harness → TVS → π (C–L–C) → LDO/VEXT; protect against reverse/short events; keep sensing/signal pins in the quiet island.
Renesas
ISL78310, RAA214290, ISL80510, ISL80505
Layout notes: output MLCC must be close to OUT; single local star at the LDO EP; follow transient layout drawings to match datasheet.
onsemi
NCV8730, NCV8114ASN330T1G, NCV4274
Layout notes: automotive front-ends require input bypass + surge handling; keep PG/RESET and EN away from SW/IND; final input cap near VIN.
Microchip
MCP1799, MIC5332, MIC39101-2.5BM
Layout notes: for 12–45 V sensor bias use TVS/π up front; output capacitor must sit at LDO; shield EN/PG lines to keep camera/sensor stable.
Melexis
MLX90393, MLX81200, MLX81339
Layout notes: place decoupling in the quiet island with the LDO; route sensor supply and sensitive pins away from high dI/dt copper.
10) CTA
Need us to check whether your LDO is sitting right after a switching regulator or inside an automotive harness? Tell us and we will keep the TVS / π stage and the “last C near LDO” note in the layout.
This is useful for: TI TPS7Axx-Q1, ST LDL/L99VR, NXP SBC with VEXT, Renesas ISL78xxx, onsemi NCV LDOs, Microchip high-VIN bias LDOs, Melexis sensor supply.
Submit your BOM (48h)We will review LDO layout notes and keep EMI/filtering requirements in your BOM for procurement / PCB vendor.
Frequently Asked Questions: LDO EMI & Layout
All Q&A below stays inside this page’s scope: small-board LDO rails that are fed from a switching regulator or an automotive/long-harness source, and how to keep the layout from killing datasheet PSRR/noise.
Why is my LDO still noisy after a switching regulator?
Because the LDO only rejects noise within its PSRR band and with tight loops. If VIN–C–GND is long, the front-end spikes couple straight into the regulator. Add a capacitor right at VIN and consider a C–L–C before the LDO.
Do I really need a π filter before an LDO?
You do when the LDO sits behind an automotive harness, long cable, or a noisy DC-DC. TVS clamps the surge; the π filter kills the fast edges. If the source is on the same PCB, very close, and loops are already small, the π can be optional.
How close should the LDO input/output capacitors be?
Form a small triangle on the same layer: LDO VIN → input MLCC → GND, and LDO OUT → output MLCC → GND. The farther the cap, the more parasitic L and the worse the transient/EMI performance.
What is star grounding in a small LDO board?
Use the LDO pad/EP as the local star. Power return (from DC-DC/harness) and the quiet return (ADC/sensor) both meet there, so switching currents do not flow through the sensitive ground.
How do I shield the LDO feedback/sense pin from the SW node?
Route FB/ADJ/SNS short, keep it away from SW/IND/high dI/dt copper, and run a ground guard on one side. Place the feedback divider right next to the LDO so nothing can inject noise mid-way.
Can I use only TVS without π filter in automotive harness?
TVS is for big/slow transients. It does not clean switching edges and HF noise on the line. In cars, a C–L–C right before VIN and the last C at the LDO pin is the safer recipe.
Why does my LDO output ring on load steps?
Most cases: output loop is too large or the output MLCC is too far. The extra ESL lets the step energy ring. Move the cap in, shorten the return, re-test.
Can an LDO remove switching spikes completely?
No. LDOs are not surge absorbers. They reject a band of ripple/noise. Spikes must be clamped (TVS) and filtered (π) before they reach the LDO.
Can I place the π filter far from the LDO?
The first C can stay by the connector/DC-DC, but the last C of the π has to sit next to the LDO VIN. Otherwise the filtered line will pick up noise again.
Why do camera or sensor LDOs need a quiet island?
Because their loads are small and sensitive. Put LDO + OUT MLCC + sensor decoupling together and keep high-current copper and SW nodes out of that area.
What happens if the PCB fab moves my input capacitor?
Your effective loop gets bigger → you see more spikes → your LDO looks worse than the datasheet. That’s why layout rules must be written into the BOM/fab notes.
Do I need separate grounds for LDO and ADC?
Separate paths, one star. Route power/noisy return away from the sensor return, then tie both at the LDO. This is the practical way on small boards.
How do I verify the layout changes actually reduced EMI?
Probe VIN/VOUT with short ground before/after adding the π or moving the caps. If you have a LISN, capture a simple board-level plot and store the screenshot with the BOM.
When should I tell the supplier my LDO sits after a switching regulator?
Whenever VIN is coming from DC-DC or from an automotive harness. They will keep the TVS/π and “last C by LDO” in the BOM instead of dropping them as cost-down items.
Does high-PSRR automatically fix poor layout?
No. Those PSRR numbers were taken with tight loops and correct capacitors. If the board adds parasitics or couples noise into FB/EN, you will not meet the datasheet curves.
