← Back to Low Dropout Regulators (LDOs)
This page is about LDOs used after a switching regulator to supply sensitive AFE / precision reference rails, not about general-purpose or automotive or rad-tolerant LDOs. We focus on noise, PSRR in the actual switching band, and small load-step behaviour.
Introduction & Scope
In many mixed-signal boards, the typical upstream is a buck (300 kHz, 450 kHz, or even 2 MHz). The typical downstream is an ADC, sensor AFE, or a precision reference IC. A “low-noise” LDO that only shows excellent PSRR at 100 Hz or 1 kHz is often not enough for this chain.
We also explicitly exclude the following from this page to avoid overlap with your other LDO pages: automotive-grade / AEC-Q100 topics, radiation / space hardening, and ultralow-Iq / harvesting LDOs. If you need those, route to their dedicated pages.
- Problem 1: many “low-noise” LDOs lose PSRR in the 10 kHz–1 MHz band, which is exactly where the buck lives.
- Problem 2: AFE/ADC loads are pulse-like (sample/hold, wake-sleep), so the LDO must not pass a visible step to the reference rail.
- Problem 3: precision rails care about temp drift; many generic LDOs don’t guarantee it.
Center idea: “Use an LDO that still has PSRR where your DC-DC switches, and that keeps load-step disturbance low enough for the AFE / reference to stay accurate.”
Noise & PSRR Requirements for AFE
AFE and precision references do not look at one noise number only. They see the integrated output noise plus the residual switching ripple that the LDO fails to reject. That is why we must evaluate both noise (with bandwidth!) and PSRR at the real switching frequencies.
Different AFE/ADC noise budgets
High-resolution ADCs and sensor AFEs can easily be affected by tens of µV. Your LDO noise must stay below the noise of the device you power; otherwise the LDO becomes the dominant source.
Low-freq vs mid/high-freq PSRR
100 Hz / 1 kHz PSRR is good for mains/slow noise, but your buck is at 10 kHz–1 MHz. Keep only LDOs that still have 40–60 dB in that range.
Read the datasheet like this:
- Find your upstream switching frequency (e.g. 450 kHz).
- Look up the LDO’s PSRR curve at that frequency. If it’s missing, ask the vendor.
- Make sure the integrated output noise (1 Hz–100 kHz or 10 Hz–100 kHz) + “PSRR leftover” still fits your AFE’s noise budget.
Must-check parameters for this page:
- Output noise (µVrms) with bandwidth specified
- PSRR @ 100 Hz / 1 kHz / 10 kHz / 100 kHz / 1 MHz (as available)
- Line transient / load transient rejection (to catch ADC sampling steps)
- Temperature / drift behaviour if powering a precision reference
Key takeaway: a single “low-noise” spec is not enough — you must see the PSRR where the switcher actually works, or the AFE will still see ripple.
Selection Criteria (Noise / Tempco / Load-step)
For AFE / precision-reference rails, keep exactly four mandatory fields in the LDO matrix: noise (with bandwidth), PSRR at the switcher band, temperature drift and grade, and load-step disturbance. Everything else is optional.
1) Noise (with BW)
State µV RMS and the measurement bandwidth (1 Hz–100 kHz or 10 Hz–100 kHz). If the datasheet shows only one number, request the curve.
2) PSRR @ real frequency
Check 10 kHz–1 MHz to match the upstream DC-DC. Target ≥ 40–60 dB around the actual switching point.
3) Tempco / grade
Distinguish instrumentation / V-grade from standard industrial. Always show drift together with the temperature range.
4) Load-step response
Log both ΔV and recovery time for ADC-like pulses (for example 5 → 50 mA or 10 → 80 mA). The AFE should not see a step.
AFE LDO matrix header (copy/paste):
Brand | PN | Vin (min/max) | Vout (set/range) | Iout (max) | Noise (µV RMS, BW) | PSRR @ 10k / 100k / 1M | Tempco (ppm/°C, grade) | Load-step (ΔV, tREC) | Notes
Stability & Load-Step Interaction
Precision rails become tricky when three things meet: the LDO’s own Cout / ESR requirement, the AFE’s local decoupling right at the pin, and pulsed loads (ADC sampling, AFE gain switching, MCU wake-up). Change any of them → validate again.
Keep the LDO baseline
Start from the datasheet Cout and ESR class. That is the reference point for phase margin and transient plots.
Add AFE decoupling carefully
A 100 nF / 1 µF right at the AFE pin is good for the AFE but it changes what the LDO “sees”. Re-check transient.
Stop the pulse from coming back
If ADC/MCU pulses still show at the reference node, add a small R/RC only on the AFE branch and keep a single-point ground.
Engineer checklist: scope at the LDO pin and at the AFE pin; log ΔV and tREC; then repeat after moving/adding local caps; if ringing appears, relax ESR or isolate the AFE branch.
Testing & Validation for Precision Rails
Precision LDOs powering AFE / references must be validated in four mandatory tests: output noise, PSRR at at least three frequencies, pulsed loads, and temperature points in chamber. Optional but strongly recommended: end-to-end chain from SWPS → LDO → AFE.
1) Output noise
Integrate 10 Hz–100 kHz (or 1 Hz–100 kHz). Log µVRMS together with BW and load current.
2) PSRR sweep
Measure at 10 kHz, 100 kHz, 1 MHz to match the switching converter band. Keep test caps same as datasheet.
3) Pulsed loads
AFE/ADC-style steps (for example 5 → 50 mA, 10 → 80 mA, 1 → 30 mA) and record ΔV + tREC at LDO pin and AFE pin.
4) Temperature points
Chamber at −40 °C / +25 °C / +85 °C / +105 °C; log VOUT drift and noise to prove the tempco grade.
Small-batch A/B rule: take 2 pcs from the same brand / same PN and 2 pcs from an alternative brand, run exactly the 4 tests above, then keep the rail that shows the smallest ΔV in pulse test and the highest PSRR @ 100 kHz.
Mini IC Matrix (AFE / Precision LDO)
Fixed fields for all seven brands. If the brand has no standalone precision LDO, the row still stays but points to “general-purpose LDO + RC + layout hardening”.
| Brand | PN / Family | Noise (µV RMS, BW) | PSRR @ 10k / 100k / 1M | Temp grade | Load-step log | Notes |
|---|---|---|---|---|---|---|
| TI | TPS7A4700RGWT, TPS7A85A :contentReference[oaicite:0]{index=0} | 4.4–6 µV RMS, 10 Hz–100 kHz | ~70 dB / ~60 dB / >40 dB (typ.) | −40 to +125 °C | 5 → 50 mA, ΔV ≤ 15 mV, tREC ≤ 200 µs | Best for very clean post-DC/DC rails and RF/ADC supplies. |
| ST | LDLN025M33R, LDLN050PU33R :contentReference[oaicite:1]{index=1} | 6.5 µV RMS, 10 Hz–100 kHz | 80 dB @ 1 kHz; 45–55 dB @ 100 kHz | −40 to +125 °C | 1 → 30 mA, ΔV ≤ 20 mV | Tiny SOT-23-5, good for sensor-front-end cards. |
| NXP | LD6806CX4/25H, LD6835K/33H :contentReference[oaicite:2]{index=2} | ≈30 µV RMS, 10 Hz–100 kHz | High at LF, falls above 1 MHz → verify vs your converter | −40 to +85 / +125 °C (check lot) | 5 → 50 mA, ΔV ≤ 25 mV | Ask for noise curves; some docs give only one value. |
| Renesas | ISL80510IRAJZ, ISL80505 :contentReference[oaicite:3]{index=3} | ≈75 µV RMS, 10 Hz–100 kHz | 58 dB @ 1 kHz, good transient behavior | −40 to +125 °C | 10 → 80 mA, ΔV ≤ 25 mV, fast recovery | Good when you also need programmable soft-start. |
| onsemi | NCP164AMX330, NCV59745 :contentReference[oaicite:4]{index=4} | Ultra-low noise, < 10 µV RMS class | High PSRR up to RF/HS comms | −40 to +125 °C (automotive for NCV59745) | 5 → 100 mA, ΔV ≤ 20 mV | Use when current ≥ 300 mA or automotive qual needed. |
| Microchip | MIC5504-3.3YM5-TR, MIC94310-4YM5-TR :contentReference[oaicite:5]{index=5} | Low-noise 300 mA class (needs CBY check) | ≈60 dB @ 1 kHz, verify above 100 kHz | −40 to +125 °C | 1 → 30 mA, ΔV ≤ 25 mV | Good for small sensor boards; auto-discharge helps AFE. |
| Melexis | MLX90825, MLX91230 (internal regulators only) :contentReference[oaicite:6]{index=6} | — (not a standalone precision LDO) | — | Automotive temp, sensor-focused | Test end-to-end on the Melexis board | Use TI / ST / onsemi LDO + RC + tight layout next to the Melexis sensor rail. |
Application Notes (Typical Hookups)
These three wiring patterns cover the most common precision-rail cases: a switcher that needs clean-up before an ADC, a branch where the voltage reference must be cleaner than the AFE rail, and a mixed rail where MCU wake/sleep causes load steps. Keep the LDO’s recommended caps, then add isolation only on the noisy branch.
1) DC-DC → LDO → ADC
Use this when an upstream buck/boost feeds several loads but the ADC needs a cleaner 3.3 V or 5 V. Place bulk + HF caps right at the LDO input, then keep the LDO-to-ADC trace short. Always probe at both ends: LDO OUT and ADC VDD.
- Input to LDO: 10 µF + 100 nF to swallow the switcher’s ripple.
- Output of LDO: use the datasheet Cout (e.g. 4.7–10 µF, low ESR).
- At ADC pin: add 100 nF local decoupling right at the device.
- Validation: pulse ADC-like load (5 → 50 mA) and confirm no back-injection to LDO input.
2) DC-DC → LDO → Voltage Reference → AFE
Use this when the reference must be quieter than the main AFE rail. Split the branches after the LDO. The reference branch gets a small R/RC and the shorter trace; the AFE branch can have more caps and longer routing.
- After LDO, split into Ref branch and AFE branch.
- Ref branch: add 1–10 Ω or RC to stop AFE bursts from coming back.
- Keep ref branch ground close to LDO ground; do not share long return.
- Log noise on both branches → show that ref stays lower.
3) MCU Wake / Sleep Load-Step Clamp
When the MCU shares the same low-noise LDO with the AFE, its wake-up current or power-mode switching can kick the rail. Put a small series element or RC only on the MCU branch and keep the AFE branch as the straight one.
- LDO OUT → straight to AFE / reference devices.
- LDO OUT → MCU branch passes through R/RC or a small load switch to slow the edge.
- Validate with scope at AFE pin while MCU wakes; AFE should not see the step.
Frequently Asked Questions
Why does my ADC still see ripple even though the LDO datasheet shows high PSRR?
Datasheet PSRR is taken with standard caps and single-frequency injection. Your board has real switcher ripple, longer traces, extra caps at the ADC, and sometimes beat frequencies. Measure PSRR at the exact switching band and with your final capacitor set to match reality.
Which noise is more important — LDO noise or the voltage reference noise?
In a “DC-DC → LDO → reference → AFE” chain, protect the reference first. The LDO should be quiet enough not to mask the reference’s own noise. Then isolate the AFE branch with a small R/RC so AFE load bursts cannot corrupt the reference node.
Does low-noise always mean low Iq?
No. Ultra-low-noise or high-PSRR LDOs often spend extra quiescent current on reference filtering and internal amps. For AFE rails, noise/PSRR wins over Iq. If quiescent is the hard constraint, use a dedicated ultralow-Iq LDO page instead of this precision route.
Will oversizing or changing the output capacitor make transients worse?
It can. The datasheet Cout/ESR window is where phase margin was checked. Adding very low-ESR caps right at the AFE pin may shift the zero/pole and show ringing or a larger step. Every cap change → repeat noise, PSRR (3 points), and AFE-style load pulses.
Can I use two LDOs in series for a very clean AFE rail?
Yes, if you have a reason: the first LDO blocks switcher ripple, the second provides ultra-low noise or low tempco. Stagger their dropouts, keep each output cap local, and place the second LDO closest to the AFE. Efficiency will drop, so verify on the final board.
Can I feed the AFE directly from the DC-DC if the DC-DC has “good ripple”?
Usually no. “Good ripple” on the switcher is still orders of magnitude higher than what a 16-bit or 24-bit front end wants. A post-LDO or at least an RC/LC post-filter is safer. Keep the LDO because it also isolates AFE load kicks from getting back to the switcher.
How close should the LDO be placed to the ADC / AFE?
As close as your layout allows, then still add a local 100 nF at the ADC pin. Long traces add inductance that makes pulse loads look worse. If the LDO can’t be close, isolate the far AFE branch with a small R/RC so the LDO still “sees” its original output cap.
What bandwidth should I use when I report the LDO output noise?
Use the datasheet’s bandwidth (commonly 10 Hz–100 kHz or 1 Hz–100 kHz) and explicitly write it next to the µV RMS number. A single “10 µV RMS” without BW is not comparable. If you need lower-frequency accuracy (bridge sensors), extend the LF window.
Why does the LDO ring when the ADC samples?
Because the ADC pulse current is hitting a node that now has two capacitors in series: the LDO’s Cout and the AFE local cap. That can create an extra pole/zero and reduce phase margin. Keep the AFE cap small, or add a tiny series R in the AFE branch to damp it.
Can I share one LDO between the MCU and the AFE?
You can, but clamp the MCU branch. Put the AFE on the straight, quiet branch and put RC / load switch / small R only on the MCU branch. Then test wake/sleep and watch the AFE pin. If the AFE still moves, give the MCU its own cheap LDO.
What should I log in my small-batch validation report?
Log four things: integrated noise (with BW), PSRR at 10 k / 100 k / 1 MHz, AFE-like pulse test (ΔV and tREC) at two points, and temperature drift at −40 / +25 / +85 °C. Do it for 2 pcs per brand so you can compare and keep the best one.
What if the supplier can’t provide a full noise or PSRR curve?
Then you must measure it on your bench using the capacitors and load that the AFE will actually see. Mark that line in the BOM as “tested-to-fit” instead of trusting the single number. For sensitive AFEs, lack of a curve is a real selection risk.
Can I add a ferrite bead after the LDO for extra isolation?
Yes, but treat it like an extra series element in the loop. Put the bead on the noisy branch (MCU/logic), not on the precision branch. After adding the bead, repeat transient and PSRR tests because it can interact with the output capacitor.
Why does PSRR get worse at high temperature?
Because the internal error amp gain and pass element both change with temperature, so the same LDO that looked strong at +25 °C can leak more ripple at +85 °C. That is why we said: run PSRR at three frequencies and at several temperatures, not just room.
When should I stop tuning LDOs and just use a dedicated precision reference IC?
If the AFE datasheet asks for sub-10 µV RMS or ppm-level drift, and you already added RC, layout isolation, and two-stage LDO but still see noise, it’s time to place a reference IC on a short, clean branch. Keep the LDO to feed it, but let the reference set the final noise floor.
