Multi-Cell Charger Controller ICs for 2S

Q: What takes priority: input DPM or charge current (ICHG)?

DPM takes priority to protect the source from collapse or oscillation. Only the headroom preserved by DPM is allocated to ICHG and short passive-balance windows. This order keeps acoustics civil and prevents loop hunting. If performance looks slow, inspect DPM duty and reasons before raising ICHG.

Q: Why does fast-charge current hunt in CC?

Hunting usually means an aggressive loop meeting DPM throttling, switching-node ringing, or slow sense filtering. Log DPM duty first, then examine gate waveforms, the SW node, and the sense RC time constant. Reduce loop bandwidth or add damping until the response is repeatable under DPM action.

Q: Why is the last 1% slow—or does it end too early?

The CV tail depends on float accuracy, termination method, and temperature windows. For long tails, trim float error and consider hybrid termination (dI/dt plus a timer). For premature stops, reduce ripple at the sense ADC and lower ITERM. Keep passive balance to short tail windows to avoid fighting the loop.

Q: When should passive balancing run, and will it slow charging?

Run trims in the CV tail or brief CC gaps, with modest bleed current and limited concurrency. Stagger activity if thermals are tight. Coordinated with DPM and ICHG, well-scheduled windows have minimal impact on total time while keeping ΔV tight so packs finish together. Repeated outliers are diagnostic.

Q: How do JEITA bands change charge speed and lifetime?

JEITA limits current and sometimes voltage in cold and hot bands to protect plating margins and cycle life. Implement smooth derating rather than steps to avoid noise and perception issues. Validate bands on the real thermistor path, not only bench air, and expect slower charge at extremes by design.

Q: How do I choose a shunt and keep readings accurate across temperature?

Pick a low-µΩ, low-TCR, four-terminal shunt, route true Kelvin sense away from switching edges, and add a small RC before the ADC. Synchronize sampling with PWM when possible. Calibrate at two or three points across temperature and store the coefficient with a version tag in logs.

Q: Which gate-driver choices cut EMI without killing efficiency?

Balance drive strength against MOSFET Qg, keep reliable dead time, and enable a Miller clamp to prevent false turn-on. If ringing persists, add a compact snubber and shorten driver-to-gate loops. Slightly slower edges often reduce DPM interventions and improve metering fidelity.

Applications & Use Cases

Multi-cell charger controllers for 2–6S lithium packs orchestrate the full pre-charge → fast-charge (CC) → CV termination → recharge flow while exposing balance hooks for passive cell equalization, coordinating with external gate drivers for the power stage, and closing the loop with current limiting & metering. In real products, constraints are shaped by long dock cables and line-drop, harsh duty cycles, thermal headroom, and compliance—all of which demand IIN_DPM to protect the input source, ICHG management under thermal derating, and verifiable charging logs.

Across sectors—power tools & outdoor (4–6S), drones & robotics (3–6S), portable medical carts (2–4S), and industrial docks (2–4S)—the goals are consistent: safe recovery from low-voltage states, stable CC even with fluctuating sources, efficient CV tails, and traceability for field quality. Passive balancing typically operates in CV tails or CC gaps to trim ΔV between cells without fighting the main current loop, while shunt-based metering provides the audit trail that engineering and compliance teams rely on.

This page focuses on the controller viewpoint: where the hooks are, how power is budgeted (IIN_DPM first), and how to frame logs, thresholds, and windows for practical validation. If you need end-to-end selection help, share your target pack, input source, and thermal envelope— we’ll return three BOM options (cost-down / standard / high-margin).

Quadrant map — how 2–6S controllers align to power vs. cell-count across four common sectors. Minimal labels; details in the text.

Sectors: Tools · Drones · Medical · Industrial

Power Tools / Outdoor (4–6S)

Pack icon with balance pads and input power control. Minimal in-image text; see copy for context.

High-power 4–6S tools demand fast turnarounds without stressing docks or long cables. A capable controller keeps CC stable under input fluctuations, protects the source with IIN_DPM, and prevents restarts or acoustic noise. In the CV tail, recovery is efficient and predictable, while passive balance trims cell mismatch without fighting the main loop. Shunt-based metering yields per-cycle energy and temperature peaks for warranty analytics and fleet maintenance.

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Drones / Robotics (3–6S)

Concept: CV-tail balancing windows and a protected input limit; logs support field analytics.

Frequent cycling pushes 3–6S drone packs to the limits of cell consistency and thermal budget. Controllers allocate power with IIN limits to prevent source collapse, then schedule passive balancing in CV tails or CC gaps to shave ΔV without inducing heat spikes. With shunt-based metering, teams can correlate charge-back energy and temperature peaks to flight logs, shortening root-cause analysis and improving fleet health over time.

Portable Medical Carts (2–4S)

Quiet, compliant charging with temperature windows, derating, and auditable logs.

Medical carts prioritize quiet, traceable charging and strict JEITA temperature windows. The controller’s derating keeps ICHG within safe thermal envelopes while EMI-friendly layouts avoid noise in sensitive wards. Audit-grade logs capture stage transitions, reasons for limits (DPM vs. thermal), and temperature peaks to support compliance and service records in clinical settings.

Industrial Docks / Terminals (2–4S)

Power budgeting view: input first, then charge and balance; aware of long, lossy harnesses.

Industrial docks run 24/7 with wide input ranges and long harnesses. The controller applies IIN_DPM to avoid source collapse, budgets power between the system, charge current, and balancing, and tolerates line-drop with appropriate targets. Separate system rails keep operations alive even when packs are deep-discharged, while logs and thresholds simplify service during shift turnover.

What It Is (Definition & Boundaries)

A multi-cell charger controller (2–6S) is the coordination brain for lithium packs, steering the pre-charge → fast-charge (CC) → CV termination → recharge sequence while protecting sources and cells. It exposes balance hooks for passive equalization, works with external gate drivers to command a synchronous power stage, and supervises current limiting & metering so power is budgeted predictably. Typical inputs include per-cell voltage sense, a pack NTC for JEITA temperature windows, and fault/status lines to help designers produce auditable charge logs.

Interfaces are pragmatic: upstream I²C/SMBus/IRQ for configuration, health, and logging; downstream gate-drive pins for high-side/low-side MOSFETs in a buck or buck-boost stage; cell and pack sensing; and an input-side guardrail via IIN_DPM (input current/power limit). In operation, IIN_DPM comes first, preventing source collapse or acoustic noise; remaining power is allocated to ICHG and, when windows allow, passive balance (often in CV tails or CC gaps). A high-side shunt metering path closes the loop for traceability and warranty analytics.

This page focuses on the controller viewpoint. It does not cover USB-C/PD negotiation, single-cell chargers (linear/switching/charge-pump), active balancing algorithms, primary/secondary pack protection, or the system VSYS rail. Here you’ll find the conceptual state machine, a metrics table, a troubleshooting matrix, a high-level block diagram, and downloadable checklists. Need end-to-end help? Share your pack and constraints — we’ll return three BOM options (cost-down / standard / high-margin).

System Block Diagram

At a high level, the path runs VIN → input filter/TVS → multi-cell charger controller → external synchronous power stage (buck or buck-boost) → PACK (2–6S). Side paths complete the picture: balance hooks connect to per-cell bleed legs for passive equalization; a high-side shunt-metering path feeds the MCU for logs; and a pack NTC enables JEITA temperature windows and derating. Upstream, I²C/SMBus/IRQ carries configuration, status, and fault events; downstream, gate-driver outputs command the HS/LS MOSFETs.

Power budgeting follows a simple rule: IIN_DPM first. The controller safeguards the source against collapse or oscillation; the remaining envelope is allocated to ICHG, while passive balance is scheduled in CV tails or short CC gaps so it does not fight the main charge loop. In many systems, the system rail is powered by a separate DC/DC from the pack; that VSYS path is outside this page’s scope but is shown conceptually for context. The diagram below prioritizes names and signal directions over device-level detail, acting as a shared reference for the state-machine, balancing, and metering sections that follow.

Map this to my pack

High-level flow: VIN → controller → gate-driven power stage → 2–6S pack. Side paths show passive balance hooks and shunt metering to MCU/logs. Principle: IIN_DPM first, then allocate to ICHG and balancing when windows allow.

Jump ahead: State Machine · Balance Hooks · Current Limit & Metering

Charging State Machine

A multi-cell charger controller for 2–6S packs is best understood as a compact state machine that sequences pre-charge → fast-charge (CC) → CV termination → recharge, with guard conditions that continuously check input validity, temperature windows, and pack health. From the controller’s viewpoint, progress through the phases is not merely a timer; it is a negotiation among three forces: IIN_DPM to protect the source, ICHG to meet target current, and—where windows permit—short bursts of passive balance that trim ΔV between cells without destabilizing the main loop. The instrument panel behind this is shunt-based metering, which makes every transition explainable and auditable.

Entry & Pre-Charge. The machine arms once VIN is valid, the pack and cell map are recognized, and the NTC/JEITA window allows charging. Pre-charge serves two goals: recover deeply discharged cells safely and, where permitted, bring up a limited system rail for minimal functions. Current is kept deliberately small, and logs should record timestamp, lowest cell voltage at entry, input source identity, and the reason for exit (voltage recovered, time limit reached, or temperature window change). A clean pre-charge history helps service teams distinguish genuine pack ageing from wiring or connector issues.

Fast-Charge (CC) with DPM. In CC, stability depends first on IIN_DPM—the controller must defend the adapter or dock from collapse and acoustic noise caused by long cables and line-drop. When DPM throttles the envelope, ICHG is reduced accordingly; if thermal headroom narrows, derating layers on top, and JEITA windows may further limit current in colder or hotter zones. Good telemetry at this stage includes the average and peak ICHG, the fraction of time DPM was active, and the hottest sensor reading. That data turns a “it charges slowly” complaint into a power-budget conversation your team can actually win. For the budgeting lens, see Current Limit & Metering.

CV & Termination. Reaching the target pack voltage moves the machine into CV, where current naturally decays. Termination strategies vary—dI/dt, a hold-time, or a combination with ΔV stability—but the CV tail is where user perception and factory consistency are most sensitive. Too aggressive and you risk premature stop with underfilled packs; too conservative and users experience “endless last percent.” This is also the natural home for passive balance: short, timed windows that bleed slightly higher cells without fighting the decaying CV current. When balance runs, annotate it in the log with start/end, trigger reason (ΔV, time window), and the maximum temperature observed.

Recharge & Hysteresis. After termination, the controller watches for a defined fall-back threshold and a hysteresis band that prevents chatter from small voltage rebounds or load transients. Recharge should log Δt since termination, estimated ΔSOC, and the brief reason code (storage bleed, transport, system draw). In fleets, this trio reduces “mystery overnight drains” to a pattern you can test and fix.

Fault & Recovery. All along, the state machine guards for input brownout, short-circuit events, over/undertemperature, sense faults, and unexpected disconnects. The safe response is to exit into a protected state, capture a concise snapshot (state, voltages, currents, temperatures, and DPM status), and only re-enter via the same attach/entry checks that began the journey. Because the machine is small and deterministic, a single page of logs can reconstruct the charge—exactly the transparency factory and field teams need.

Two-lane sketch of the controller’s logic: guards gate entry; actions progress from Pre → CC → CV → Termination → Recharge. Principle: IIN_DPM first; short balance windows sit in CV tails or CC gaps. See also Balance Hooks and Current Limit & Metering.

Balance Hooks

Balance hooks are the controller’s logical connection points to each cell’s passive bleed leg (typically a small MOSFET and resistor). The goal is simple: reduce per-cell ΔV/ΔSOC spread over time so the pack behaves consistently across cycles. Passive balancing does not “refill” energy—it trims the taller cells so the whole string finishes together. On this page we focus on these hooks and their scheduling; active balancing and protection FET strategies live on other pages.

When and how to schedule. The most practical windows are the CV tail and short gaps during CC. In CV, main charge current is decaying, so tiny bleed currents do not fight the loop. In CC, use short, measured bursts between regulation updates. Triggers can be a ΔV threshold, a ΔSOC estimate, a fixed cadence, or a hybrid of these. Budgeting follows the same hierarchy as charging: IIN_DPM first (protect the source), then ICHG, then—only when headroom exists—balance. Keep bleed power modest, stagger cells if thermals are tight, and never let balancing mask a sick cell that repeatedly lags the group.

Instrumentation and logs. Treat balancing as a first-class event: record start/stop timestamps, trigger reasons, cumulative time and estimated energy, and the hottest temperature observed. Pair these with shunt metering so you can reconcile “energy in” versus “energy bled” and flag anomalies. Over weeks of data, you will see whether consistency is improving (ΔV distribution narrowing) or if a subset of packs needs service. Proper logs also turn field complaints—“charge stalls at the end”—into a clear, defensible narrative.

Boundaries and hand-offs. Hooks and passive windows are the controller’s domain. If your design requires energy re-distribution, cell-level protection actions, or pack-side diagnostics, hand the topic off to the corresponding pages and architectures. Here we stay with the controller: small windows, modest currents, clean logs, and predictable thermals that keep the CV tail civil.

Per-cell passive bleed pictogram with a ΔV monitor badge. Run balancing in CV tails or short CC gaps, and only after budgeting IIN_DPM and ICHG. See Current Limit & Metering.

Gate Drivers

In a multi-cell charger architecture, the gate driver sits between the controller and the switching power stage, translating logic-level intent into clean, repeatable control of the high-side and low-side MOSFETs. Whether the topology is buck or buck-boost, the goal is the same: switch efficiently without shoot-through, maintain controlled dead time, and keep dv/dt events from provoking false turn-on. The driver also shapes how audible the hardware sounds, how warm the MOSFETs run, and how gracefully the charge loop behaves through CC and the CV tail.

Practical tuning starts with drive strength vs. Q_g and switching frequency. Stronger drive reduces transition losses but can excite ringing; series gate resistors and a Miller clamp help set the sweet spot. Preventing shoot-through relies on robust high/low-side interlock and consistent dead time across temperature and unit variance. Where ringing appears, a compact snubber across the switching node can tame it. Layout matters: keep the driver-to-gate loops short and symmetrical, minimize the Lx loop area, and give the FETs wide copper for current and heat. Keep sense and control traces away from the switching edges to preserve metrology quality.

Coordination with the controller is continuous. The driver’s slew choices affect input stress and therefore how often IIN_DPM must intervene; they also shape the decay profile in CV. When the charger logs the fraction of time under DPM, typical ICHG during CC, and the hottest component temperatures, it becomes clear whether gating choices are delivering the intended efficiency without compromising stability. Treat the driver, MOSFETs, inductor, and layout as one system: a small improvement in switching behavior can pay back as calmer current, cleaner metering, and a quieter, cooler product.

High-level chain: controller commands the gate driver, which shapes HS/LS switching into the inductor-capacitor stage feeding the pack. Badges highlight practical tuning knobs—dead time, Q_g, a Miller clamp, and a snubber—to balance efficiency, stability, and EMI.

Current Limit & Metering

Power budgeting in a charger is a matter of priority. IIN_DPM—the input current/power guard—comes first to prevent the source from collapsing or oscillating under long cables, tight adapters, or variable docks. Only within the headroom it preserves does the loop deliver the target ICHG. Users often notice the effect at the edges: a charger that stays calm under awkward wiring, and a CV tail that decays predictably instead of hunting. Treat DPM and charge current as cooperative layers rather than competing rules; the result is a charger that is resilient to the real world.

Implementing DPM begins with a clear definition of what “source protection” means in your product. Some designs use a fixed input current ceiling; others aim for an input power window. Guard decisions should react smoothly to input droop and resume gently to avoid audible steps. During bring-up, calibrate against the worst case: the longest cable you expect, the hottest enclosure you ship, and the lowest input voltage you allow. If your dock or harness is long, add line-drop compensation so the algorithm understands that falling input voltage is sometimes a wiring story, not a source collapse. Record how often DPM is active and why—those breadcrumbs turn field questions into evidence.

ICHG, by contrast, is the “how fast” knob for the pack itself. It lives under the DPM umbrella and yields when thermal headroom narrows or when the JEITA window asks for restraint. In colder bands, modest current preserves lithium plating margins; in hotter bands, de-rating protects cycle life and the rest of the product. Taken together, DPM + ICHG ensure that CC is stable and that the CV tail is not a surprise. If your system rail (VSYS) is decoupled from the charge path, the user experience improves further: background tasks can continue even when the pack is deeply discharged, and the charger can focus on recovery without brown-outs.

Metering is where the math meets auditing. A high-side shunt in the main path—typically a low-ohmic, low-TCR, four-terminal part—gives the controller a truthful view of current and power. Use Kelvin routing, keep the sense pair away from the switching node, and add a small RC to tame ripple before the ADC. Calibrate at two or three points across your operating range and apply a temperature coefficient so readings remain stable from cold start to hot soak. During balancing windows, keep metering active so the log can reconcile “energy in” with “energy bled,” catching both configuration errors and ageing cells that consistently need trimming.

Good logs are compact but specific: state transitions with timestamps, the proportion of time under DPM, average and peak ICHG during CC, the hottest temperature observed, and a simple descriptor of the CV tail shape. That record lets engineering explain charge time, customer support dismiss myths, and quality teams spot drifting harnesses or weak adapters. In validation, exercise the stack under worst cables, cold and hot chambers, planned input interruptions, and long CV tails. If the charger remains calm and the numbers line up with expectation, your budgeting is right.

The diagram summarizes how input power is gated by DPM and then allocated to system load, charge current, and balancing, with metering on the main path.

Budgeting overview: the input is guarded by DPM, then power is allocated to the system, the charge current (ICHG), and balancing. Thermal de-rate, JEITA windows, and line-drop compensation influence the envelope. A high-side shunt feeds MCU/logs so behavior is auditable.

Key Metrics

Acceptance-oriented metrics for a 2–6S charger controller
Metric	What it means	Typical 2–6S range / type	Design intent / test	Log field
Input Guard (DPM)
DPM type	Guard style for the source	Input current or input power	Choose guard aligned to adapter/dock limits; verify smooth engage/release	Guard mode, reason codes
DPM latency	How fast the guard reacts/recovers	ms-class behavior	Prevent audible steps; no oscillation with long cables	Active duty %, entry/exit timestamps
Line-drop comp.	Offsets wiring voltage loss	Slope/offset model	Calibrate on longest harness at min VIN / hot enclosure	Comp profile id
Charge Control
ICHG (max / stability)	Target charge current and its steadiness	Controller-limited	Hold CC without hunting under DPM; bounded overshoot	Avg/peak ICHG, CC variance
CV accuracy (pack)	Pack voltage regulation near full	Controller/ADC dependent	Consistent CV tail; user-perceived last-percent stability	CV hold time, tail shape
Termination method	Stop criterion at end of CV	dI/dt / timer / hybrid	Balance capacity vs. time; avoid premature stop	Method id, trigger stamp
Recharge threshold	Re-entry point after rest	ΔV / ΔSOC + hysteresis	No chatter on small rebounds or load spikes	Δt since term, ΔSOC est.
Balance Hooks
ΔV thresholds	Start/stop window for trimming	Small per-cell ΔV band	Windows in CV tail or short CC gaps	ΔV at start/stop
Balance current	Bleed magnitude per cell	Modest, thermally safe	Stagger cells; limit concurrency	Per-cell time/energy
Concurrency policy	How many cells can bleed	Single / limited parallel	Protect thermals and EMC	Concurrent count
Thermal / JEITA
JEITA map	Band-specific current/voltage rules	Cold / cool / warm / hot bands	Reflect real NTC path, not lab ideal	Band code at entry/exit
Derating slope/cap	How current eases with heat	Smooth curve preferred	No step noise; stable user feel	Derate duty %
Hot-spot policy	Sensor placement philosophy	FET/inductor/board	Protect true hot nodes, not air	Max temperature
Metering / Logging
Shunt spec	Truth source for current	Low-µΩ, low-TCR, 4-terminal	Kelvin routing; ripple RC	Shunt id / coef.
ADC window	Sampling in a noisy world	Sync to switching	Reject ripple without lag	Sampling mode
Log granularity	How fine events are recorded	State changes + counters	Reconstruct charge and tail	State, DPM %, ICHG, temp

*All values are illustrative. Tune to your pack, input source, wiring, and thermal envelope.*

Visual checklist — the controller’s acceptance topics revolve around DPM first, then ICHG and CV behavior, with ΔV-based passive balance, JEITA mapping, and auditable logs closing the loop.

The table frames metrics as acceptance criteria rather than raw numbers. Because real products face long cables, variable docks, and shifting temperatures, the controller must guard the input first (DPM) and only then allocate envelope to ICHG and balance. CV accuracy and the feel of the tail drive user perception of “full,” while ΔV windows keep cells arriving together without fighting the main loop. Thermal and JEITA policies should reflect the pack’s true heat path, not just lab readings. Finally, metering and logs make every decision explainable: state changes, DPM duty, current statistics, and hot spots reconstruct a charge session without guesswork. Treat these fields as a compact contract among design, test, and service.

Design Essentials

Prioritize DPM, then allocate. Stabilize the source first, then distribute the remaining envelope to charge current and, when windows allow, passive balance. Tune engage and release so they are quiet and free of oscillation. Track how often DPM is active and how quickly it exits; those two signals predict both user feel and adapter stress.
Calibrate on worst cables and lowest VIN. Build your limits around the longest harness, minimum acceptable input voltage, hottest enclosure, and typical connector wear. Add line-drop compensation so falling VIN is not always treated as a failing source. Validate recovery at cold and hot extremes to avoid surprises in the field.
Tune CC stability with telemetry. Use logs to quantify average and peak ICHG, DPM duty, and short-term ripple. If CC hunts, lower bandwidth or add damping until the loop is predictable under DPM action. Favor repeatability over headline current; consistency wins the service conversation.
Shape the CV tail with intent. Choose termination rules (dI/dt, timer, or hybrid) that align with capacity targets and user expectations. Too early underfills packs; too late creates the “last 1% forever” problem. Reserve short windows for passive balance so trimming does not fight the decaying CV loop.
Schedule passive balance, don’t fight the loop. Run trims in CV tails or brief CC gaps, keep bleed current modest, and limit concurrent cells. Stagger activity if thermals are tight. If the same cell repeatedly needs trimming, treat that as a diagnostic signal rather than turning up bleed power.
Thermal derating that feels civil. Implement a smooth slope rather than hard steps. Monitor the hottest devices—not just air—and log how much time is spent derating. Protect acoustics and touch temperature first; a slightly longer charge that stays quiet and cool earns trust.
Map JEITA bands without guesswork. Model the full NTC path and confirm each band against real pack geometry. Document the current and voltage policy per band so firmware, test, and service read the same map. Resist lifting lab-bench numbers into production without accounting for heat-soak and airflow.
Meter where it matters; calibrate across temperature. Place a low-ohmic, low-TCR shunt in the main path with true Kelvin routing and an RC at the ADC input. Calibrate at two or three points and store the coefficient so readings stay trustworthy from cold start to hot soak.
Lay out for quiet switching and honest sensing. Keep driver-to-gate loops short and symmetric, minimize the Lx loop, and give MOSFETs copper to spread heat. Route sense pairs away from edges and planes tied to the switching node. Add a compact snubber if ringing persists.
Validate with meaningful logs. Exercise worst-case cables, cold/hot chambers, planned input interruptions, long CV tails, and balance concurrency. Record state transitions, DPM duty, current statistics, hot spots, and a descriptor of the CV tail. If the narrative is clear, support can resolve issues without guesswork.

Summary graphic — prioritize the input guard, then allocate to charge and trimming; keep thermal and JEITA policies real, meter honestly, lay out quietly, and let the logs tell the story.

Troubleshooting Matrix

Symptom → Cause → Checks → Action (2–6S charger controller)
Symptom	Phase	Likely Cause	What to Check	Fix / Action	Notes
Input & DPM
Adapter buzz or brown-out	Any	DPM threshold/latency too aggressive; line drop unmodeled	DPM duty%, entry/exit stamps; VIN droop vs cable length; source rating	Smooth DPM slope; enable line-drop comp; cap ICHG when guard active	Validate on longest cable at min VIN
DPM chattering	Any	Guard hysteresis too small; recovery too fast	Oscilloscope at VIN/Lx; log DPM toggles	Increase hysteresis/holdoff; add small input RC/LC if needed	Watch acoustics after change
CC Stability
Charge current hunts	CC	Loop bandwidth too high; driver ringing	ICHG ripple, SW node ringing, gate waveforms	Reduce bandwidth; add gate-R/Miller clamp; snubber if persistent	Correlate with DPM duty%
Large overshoot at CC entry	Pre→CC	Soft-start too steep; sense RC too slow	ICHG step response; sense RC cutoff	Tune soft-start; re-size RC for phase margin	Re-run hot/cold
CV & Termination
“Last 1% forever”	CV	CV accuracy off; termination too late	Float accuracy; tail shape; ITERM setting	Trim float; use hybrid dI/dt + timer; keep a short balance window	Log tail descriptor
Premature termination	CV→Term	Sense noise; ITERM too high	ADC window vs switching; shunt routing	Filter ripple; lower ITERM; sync ADC to PWM	Check recharge hysteresis
Balance Hooks
Pack warms during balance	CV tail	Bleed current too high; cells trimmed in parallel	Per-cell energy/time; board thermals	Stagger cells; cap concurrent trims; reduce bleed	Tie windows to CV tail
Thermal / JEITA
Abrupt fan/noise on heat	Any	Derating stepwise	Temp vs ICHG profile	Use smooth slope; widen bands	Protect feel & acoustics
Metering & Logs
Current readback drifts	Any	Shunt TCR; calibration sparse	Cold/room/hot deltas; shunt spec	Store temp coeff; 2–3-point trim	Kelvin routing mandatory
Gate Drivers / EMI
False HS turn-on	Any	dv/dt Miller injection	Gate waveforms; SW node slew	Miller clamp; raise gate-R; snubber	Check symmetry

*Start with logs: DPM duty & reasons, ICHG stats, CV tail shape, temperature peaks and JEITA band transitions. Stabilize input first, then CC/CV loop, then allow balance windows.*

Minimal flow — read the logs, stabilize the input guard, tune CC/CV behavior, apply balance windows, then validate against temperature and JEITA.

This matrix favors a log-first workflow. Because the charger constantly arbitrates between source limits, charge targets, heat, and balancing, the fastest path is to confirm DPM duty and reasons, then quantify CC steadiness and the CV tail. Only after the input guard is quiet should you retune bandwidth and soft-start; balancing belongs in short, staggered windows near the CV tail to avoid fighting the main loop. Thermal policy should be smooth rather than stepwise, and JEITA bands must reflect the actual NTC path. Honest metering and a short list of fields—state transitions, DPM duty, current statistics, hot spots, and a tail descriptor—turn service conversations from guesswork into clear narratives.

Typical Applications & BOM Essentials

Real packs live at the intersection of cables, heat paths, and duty cycles. Instead of sizing parts for a single peak, choose the BOM so it behaves gracefully across your worst cable, lowest VIN, and hottest enclosure. Guard the source first (DPM), then allocate envelope to ICHG; open short, staggered windows for passive balance near the CV tail. Keep metering honest so logs reconcile “energy in” with “energy bled,” and make layout decisions that protect both efficiency and measurement integrity.

Power Tools, 4–6S

Select FETs by R_DS(on) × thermal and Q_g × driver strength; aim for quiet edges, not just fastest edges. Inductor I_sat and ripple set loss and acoustics—don’t chase tiny ripple if it drives switching loss. Use a low-µΩ, low-TCR shunt with true Kelvin. Add TVS sized for cable unplug events and connectors whose AWG and plating match cycle count. Gate-R, a Miller clamp, and a compact snubber tame SW ringing so DPM doesn’t misdiagnose input trouble.

Drones/Robotics, 3–6S

Fast turnarounds magnify ΔV drift: give balance hooks short, staggered slots in CC gaps and the CV tail. Favor inductors with honest saturation and keep switching frequency in a range that surviving thermals can support at altitude. JEITA mapping should reflect the real pack thermistor path in moving air. Maintain logs of DPM duty, ICHG mean/peak, and balance energy per cell for fleet health.

Medical/Industrial, 2–4S

Prioritize acoustics and traceability. Implement smooth thermal derating; avoid audible current steps. Use a four-terminal shunt and synchronize ADC windows with PWM edges to reduce ripple aliasing. Place NTCs where heat actually flows—often near FETs or the inductor rather than free air. Keep a concise log schema so quality teams can reconstruct charge sessions without a microscope.

BOM map — choose FETs by loss & drive, inductors by saturation & ripple, a low-µΩ/TCR shunt for honest metering, NTC/JEITA where heat really flows, TVS for cable events, and gate-network parts to calm ringing.

Reference ICs & Cross-Alternatives (Series-Level)

Start with cell count and topology, then confirm input guarding (current vs power DPM), metering hooks, JEITA mapping, and balance windows. NVDC “system first” architectures behave differently from direct VSYS drive; validate against your state machine and budgeting strategy on this page.

Representative multi-cell charger controllers (series-level)
Manufacturer	Series / Part Examples	Cell Count	Topology	Notable Hooks / Features	Comparable Series
Texas Instruments	bq24610 / bq24650 (standalone); bq25710, bq24770 (NVDC)	1–6S (bq2461x/650); 1–4S/1–4S NVDC	Buck; Buck-Boost NVDC	DPM guard, power-path options, SMBus/I²C control	Renesas ISL9241/ISL9238; ROHM BD99950MUV
Analog Devices (LTC)	LTC4020, LTC4015, LTC4000-1	Multi-cell (configure float; covers 2–6S and beyond)	Buck-Boost; Buck; Controller adds MPPT/PowerPath	Rich telemetry (LTC4015), MPPT (4000-1), wide VIN	TI bq2461x / bq2571x families
Renesas (Intersil)	ISL9241 / ISL9238 / ISL95521B; RAA489118	2–4S typical; up to ~30V packs (RAA489118)	Buck-Boost, NVDC/HPB (Turbo)	AMON/BMON/PSYS monitors, USB-C/PD friendly	TI bq2571x; ROHM BD99950MUV
ROHM	BD99950MUV (2–3S NVDC); BD99954GW/BD99954MWV (1–4S)	2–4S	Buck-Boost NVDC	Notebook-class system power path; SMBus control	Renesas ISL9241; TI bq24770
Monolithic Power Systems	MP2759 (1–6S); MP2762A (2S NVDC, USB-PD)	1–6S / 2S	Buck / Buck-Boost NVDC	Integrated FETs, power path, multi-phase variants	TI bq2571x; Renesas ISL9241
onsemi	ADP3808A (3–4S Li-ion charger, legacy)	3–4S	Buck	Classic CCCV controller; availability varies	LTC4020; TI bq2461x
Microchip	MCP73213 (2S linear); MCP19124/25 (configurable digital-analog PWM controllers)	2S; multi-cell via external power stage	Linear; Controller-based (buck/SEPIC/etc.)	Programmable algorithms; cell balancing via firmware	LTC4000-1; TI bq2461x

*Series and examples are a starting point. Confirm exact cell count, NVDC vs direct VSYS, input guard method, telemetry, and compliance to your thermal/JEITA policy.

A series-first search trims the field quickly: pick the cell count and decide whether you need NVDC (stable system rail) or a direct VSYS path. Next, match input guard philosophy—current-based DPM is simpler, power-based often tracks adapters better. Telemetry changes what you can validate: families like LTC4015 expose enough data to prove CC/CV stability and the CV tail, while notebook-class NVDC parts add PSYS/AMON/BMON for budgeting. Finally, align balance hooks and JEITA: some families provide flexible windows and band maps; others assume tight notebook policies. Use this table as an on-ramp, then size FETs/inductors/shunts with your cable, VIN, and enclosure realities.

Want a compact cross-reference tailored to your pack and topology? Ask for a series-level CSV starter.

FAQ

What takes priority: input DPM or charge current (ICHG)?

DPM comes first. It protects the source from collapse or oscillation under long cables, undersized adapters, or docks. Only the headroom preserved by DPM is allocated to ICHG and, later, brief passive-balance windows. This order keeps acoustics civil and prevents loop hunting. If performance looks slow, check DPM duty and reasons before raising ICHG. See Current Limit & Metering.

Why does fast-charge current hunt in CC?

Most CC hunting is a bandwidth and stimulus issue: a loop tuned too aggressively meets DPM throttling, switching-node ringing, or slow sense filtering. Start by logging DPM duty, then inspect gate waveforms, the SW node, and the sense RC time constant. Reduce loop bandwidth or add damping until the response is repeatable under DPM action. See Gate Drivers and Troubleshooting.

Why is the last 1% slow—or does it end too early?

The CV tail reflects float accuracy, termination policy, and temperature windows. If the tail feels endless, trim float error and consider a hybrid termination (dI/dt plus a guard timer). If termination is premature, check ripple at the sense ADC and lower ITERM. Keep passive balance to short windows in the tail so it doesn’t fight the loop. See Charging State Machine.

When should passive balancing run, and will it slow charging?

Schedule trimming in the CV tail or short CC gaps. Use modest bleed current, limit concurrent cells, and stagger activity if thermals are tight. When coordinated with DPM and ICHG, balance windows barely affect total time yet keep ΔV under control so packs finish together. Persistent outliers are diagnostic, not a reason to raise bleed power. See Balance Hooks.

How do JEITA bands change charge speed and lifetime?

JEITA maps limit current and, sometimes, voltage in cold and hot bands to protect lithium plating margins and cycle life. Implement smooth derating rather than step changes to avoid acoustics and perception issues. Validate bands on the real thermistor path, not just bench air. Expect slower charge in extreme temperatures by design. See Current Limit & Metering.

How should I choose recharge thresholds to avoid chatter?

Use a ΔV or ΔSOC trigger with explicit hysteresis and a short hold-off. That prevents re-entry from small rebounds or system transients. Log the time since termination, estimated ΔSOC, and the reason code so you can correlate patterns with storage, transport, or background loads. See Charging State Machine.

What causes adapter buzz or brown-out on long cables?

Long harnesses add line drop and resonance. If DPM engages with little hysteresis or recovers too fast, the system can oscillate or sing. Model line drop, apply compensation, and use a gentler DPM slope. Check input filtering and confirm the adapter’s rating at temperature. Always validate with the longest cable at minimum VIN. See Troubleshooting.

How do I choose a shunt and keep readings accurate across temperature?

Select a low-µΩ, low-TCR, four-terminal shunt; route true Kelvin sense away from switching edges and add a small RC before the ADC. Synchronize sampling with PWM where possible. Calibrate at two or three points across temperature and store the coefficient with a version tag in logs. See Current Limit & Metering and Key Metrics.

Which gate-driver choices cut EMI without killing efficiency?

Balance drive strength against MOSFET Qg, maintain reliable dead time, and enable a Miller clamp to prevent false turn-on. If ringing persists, add a compact snubber and keep driver-to-gate loops short and symmetric. Slightly slower edges often reduce DPM interventions and improve metering fidelity. See Gate Drivers.

What should I log for field diagnostics and warranty?

Record state transitions, DPM duty and reasons, ICHG average/peak, hot-spot temperatures, a CV-tail descriptor, and per-cell balance energy. Include firmware and calibration versions. With those fields, you can reconstruct a session, separate wiring or adapter issues from ageing cells, and resolve claims without guesswork. See Troubleshooting and Key Metrics.

Multi-Cell Charger Controller for 2S–6S Battery Packs