A primary protector (also called a pack FET front-end) is the very first hard-protection device in a battery-powered system. Its job is simple but strict: cut off OC/OV/SC faults before the charger, eFuse, or BMS host has to deal with them. This ensures that downstream power-path, charging controllers, or gauging ICs always see a safe, pre-filtered input, even when the external power source or the load behaves badly.
In other words: this device acts first. It sits between the input (port or battery) and the rest of the system. Every other protection (secondary eFuse, charger-internal safety, BMS-level diagnostics) is assumed to operate after this primary cut. That is why we treat it as a separate topic instead of mixing it with charger or multi-cell BMS content.
Upstream first, downstream later
The primary protector removes dangerous energy right at the entry point, so chargers/eFuses don’t need to survive every abnormal event.
Why it needs its own page
OC/OV/SC, MOSFET gate driving, thermal trip and debounce are often not delivered together in one IC across all brands, so small-batch replacement can easily break one piece of the chain.
What we do not discuss here
No CC/CV, no JEITA, no multi-cell balancing — these are kept in their own charging/BMS chapters to avoid intent overlap.
Primary protector or pack FET placed at the front of the battery path to cut off OC/OV/SC faults before the charger or BMS.
A primary protector makes all of its decisions on top of three fault channels: over-current (OC), short-circuit (SC), and over-voltage (OV). These channels do not fire the same way: SC is microsecond-level and must turn the MOSFET off immediately; OC usually integrates over a small time window; OV is often a fixed or latched threshold. Because vendors ship different blanking, filter and threshold defaults, any cross-brand replacement in small-batch builds must be re-tested.
This section only explains when the protector trips and which output it asserts. It does not explain MOSFET gate-current sizing, thermal derating or charger termination. Those are intentionally kept out to avoid overlapping with charging/BMS chapters.
OC (Over-Current)
Handles sustained or quasi-sustained overloads (from a few ms to hundreds of ms). A timer or integration window is common so that short inrush events do not trip OC. Some devices fix the OC level; others let you set it with a resistor — sourcing must check which type you are buying.
SC (Short-Circuit)
Handles instant faults (µs). Normally drives the MOSFET gate directly to protect FET and battery. This path is the most likely to false-trip because of connector sparks, motor start-ups or switching spikes — later chapters will apply debounce/filtering.
OV (Over-Voltage)
Handles abnormal input voltage or back-feed. Some ICs implement latch + manual clear; if your board does not have a host to clear it, swapping to such a device will break your design.
Common priority is SC > OC > OV so the fastest and most dangerous fault wins first and pulls the gate down. A few devices, however, prioritize OV to protect the port/source. Therefore, when you replace the original primary protector with a different brand or with an automotive-grade variant, always confirm the fault-priority table — do not assume it is SC > OC > OV.
Relation to charging pages: we only state here that the charger/buck should see a safe input after this protector. We do not describe CC/CV, JEITA thermal control, or multi-cell charger controllers.
OC, SC and OV detection feeding a primary protector logic with priority to SC and gate-off output for the pack MOSFET.
MOSFET Gate Driving & Pack FET Topologies
The primary protector does not just detect OC/SC/OV — it must also push and pull the pack MOSFET gate fast enough so the fault is actually removed from the battery path. This is where many small-batch designs fail: the detection works, but the FET is large or back-to-back, the gate-drive current is too small, and the short-circuit is not cut fast enough.
This section explains why the IC needs a built-in driver, how single FET vs back-to-back FET changes the drive requirement, what to check for high-side layouts, and how to write a simple BOM remark so purchasing does not downgrade gate-drive capability when switching brands.
Why the IC must drive
SC is a µs-level event. If gate turn-off is left to a slow or external driver, the pack FET stays on longer and the battery still sees the fault energy.
Single vs back-to-back
Single FET is easy to cut; back-to-back (source-to-source) gives reverse isolation but needs more gate current. Some brands cannot drive two big FETs cleanly.
High-side considerations
Pack-front protectors are often high-side. That means a gate-boost or high-side driver is needed. Some ICs integrate it, others require an external driver.
When you choose a larger, lower-RDS(on) MOSFET, its gate charge (Qg) increases. To keep the SC turn-off fast, the primary protector must be able to sink that charge in the same short time window. If the driver current is lower than the Qg needs, the FET turns off slowly and the SC protection becomes unreliable.
BOM remark (keep this when sourcing):
“Primary protector shall be able to drive back-to-back N-channel MOSFETs on the pack high side. Gate-drive current must be sufficient to meet the SC turn-off time of the reference design. Do not replace with versions with lower gate-drive current.”
Primary protector IC driving back-to-back MOSFETs on the pack high side, highlighting the gate-current requirement for fast SC turn-off.
This section does not cover power MOSFET selection (RDS(on), package, copper spreading). That topic lives in the battery protector hardware page to avoid overlap.
Thermal Trip & Derating Hooks
Not every primary protector ships with the same thermal strategy. Some only monitor their own die temperature, some accept an external NTC close to the pack FET, and some can react to an external thermal warning from the charger/host. When sourcing a replacement device, this is often where behavior silently changes — and it becomes pain point for small-batch production.
Internal sensor
Easy and cheap. But it measures the IC package, not the MOSFET. If the FET is off-chip, the IC may never see the real hot spot.
External NTC
Placed near the FET or copper pour, it reflects the actual dissipation. Best option when the FET is large or off-board.
Host / charger input
Some protectors just take a thermal-warning pin from upstream. If the new brand does not have this pin, logic must move to MCU.
Once temperature is known, the protector can react in two main ways:
Derate: first reduce the allowed current, then disconnect if heat continues. This keeps the system alive.
Trip: open the pack FET immediately once a thermal threshold is hit. Some devices require power-cycle or MCU clear to recover.
Sourcing check: “Does the replacement device support NTC-based derating, or is it trip-only? Does it auto-restart after over-temp, or does it require MCU/power-cycle to clear?”
Thermal trip and derating flow for a primary protector using both NTC and internal temperature sensing.
This section does not cover system-level thermal runaway protection or multi-node pack sensing. Those belong to higher-level BMS pages.
Debounce & False-Trip Immunity
This section addresses the most common field complaint for primary protectors: “SC/OC keeps tripping even though nothing is really shorted.” In small-batch designs this usually happens right after a brand swap, because the new device has a shorter or fixed blanking time and the board-level inrush/connector noise is not filtered anymore.
To make the protector robust, we need IC-side debounce (blanking, multi-sample, peak suppression) and system-side debounce (clean ground routing, staggered inrush, optional MCU confirmation). All of them should be recorded in the BOM so purchasing does not buy a “short-blanking” version by accident.
Cable / adapter plug-in
Connector sparks and unsymmetrical rise cause narrow spikes → looks like SC.
High dv/dt buck start-up
Shared line with another DC/DC or charger → protector sees noisy current envelope.
Motor / inductive loads
Startup = one or more current bumps → without debounce they look like shorts.
Vehicle-port wobble
Automotive jacks vibrate → series of micro-dropouts → many protectors will trip.
IC-side debounce
Blanking time (hundreds of ns – few µs)
Multi-sample and use max/avg of 2–3 reads
Peak suppression / small RC in front of sense
System-side debounce
Sense pin on a clean analog return
Stagger inrush of charger vs protector check
MCU 2nd confirmation for non-critical trips
When changing brands, verify:
Is the blanking fixed or programmable?
If fixed, is it shorter than the original part?
Are OC and SC using the same or different blanking times?
If programmable, what is the method (resistor / I²C / EEPROM)? → must go into BOM.
BOM remark (anti-false-trip):
“Primary protector debounce shall be ≥ X µs to avoid SC false trips caused by adapter inrush. Do not replace with devices that have fixed shorter blanking.”
Debounce and filtering in a primary battery protector to prevent false SC/OC trips during inrush or connector events.
For small-batch or prototype-level BMS builds, you cannot just “buy any protector”. You must first lock functions (OC/OV/SC + MOS gate drive + debounce/filtering + thermal hook), then look at package/grade/lead time, and finally write a BOM note to forbid low-debounce or no-drive variants. This section converts the previous technical chapters into sourcing rules.
Recommended selection order
Must have OC / OV / SC full protection channels.
Must have MOSFET gate drive (single or back-to-back).
Debounce / filtering must be programmable or long enough for your inrush.
Thermal trip / thermal input is preferred.
Then consider package, grade (industrial / automotive), lead time.
Small-batch tips
Ask for industrial/non-automotive grade first to get samples faster. Switch to AEC-Q parts once layout is frozen.
Prefer common packages
QFN / TSSOP packages reduce board changes when swapping TI ↔ ST ↔ onsemi.
Write it in the PO
“Send the version with integrated MOS gate drive” — some series have no-drive siblings that look the same.
Decision tree for small-batch procurement and cross-brand alternatives of a primary protector or pack FET device.
Reference parts from 7 core vendors
These are real, public device families that can be used directly or as close alternatives for the “Primary Protector / Pack FET” role. Always re-validate gate-drive capability, debounce policy, and thermal hooks.
Power-distribution/high-side with OC+thermal — good for low-voltage packs.
Melexis
MLX91221/MLX91220 · MLX91230/31 · MLX81115/81113
Sensor/automotive front-ends — pair with external MOS driver to form a full primary protector.
BOM wording:
“Accept TI / ST / NXP / Renesas / onsemi / Microchip / Melexis devices that provide OC/OV/SC, MOS gate drive, debounce/filtering, and thermal trip (preferred). If the selected device has fixed shorter debounce, add board-level RC or MCU confirmation.”
Integration to Charger / Gauging / BMS Host (Hooks Only)
This chapter is just about hooks — how the primary protector tells the rest of the system that it cut the pack. We do not re-explain charger algorithms, SoC estimation, or BMS networking. The goal is to make SC/OC/OV events visible to the charger, to the BMS host, and to the gauging path so they do not misinterpret the disconnection.
Report events upward
SC / OC / OV → FAULT → to MCU / BMS host. Prefer HW FAULT + readable status register.
Stop charging after protect
If a single-cell charger is in front, tie FAULT to its safety/disable pin so it enters safe mode.
Tell the gauging path
Gauge must know “this was a protection cut-off”, not a natural discharge to empty.
When a multi-cell AFE (TI, NXP, Renesas) is used and the primary protector is external/high-side, the AFE or the BMS host must recognize this external cut-off. Otherwise it may flag a pack-disconnect / harness-open fault.
System hooks from a primary protector to charger, BMS host and gauging IC to keep fault events consistent.
This section intentionally does not define CAN/UDS/logging formats. Those belong to upper-level BMS/system pages.
Validation & BOM Remarks (Must-Do Tests)
Whenever you swap brands or run a small-batch build, you must repeat a short but targeted validation set. The purpose is to confirm that the new device still: 1) detects SC/OC/OV at the right point, 2) turns the pack FET off fast enough, and 3) reports a usable FAULT. Then you freeze these findings into the BOM so the warehouse cannot later stuff in a “detection-only” variant.
Adapter / DC plug-in
Check false-trip susceptibility with real cable + real adapter. Observe FAULT stability.
High-current / inrush
Make sure OC timer does not shut the pack off during charger start-up.
Motor / inductive on-off
Proves your debounce is long enough for spikes and dI/dt from real loads.
Intentional SC / OC
Capture gate-off slope, FAULT width, and recovery behavior (auto/manual).
Thermal / hot air
Verify NTC or internal OT actually triggers derate/trip and how it recovers.
Waveforms / data to capture
Trigger point — actual current/voltage when protection fires.
Gate turn-off slope — is the MOSFET being shut fast enough for SC?
FAULT width & recovery — auto-retry vs power-cycle vs MCU clear.
BOM remarks (copy/paste)
Strict version
“Primary protector / pack FET shall provide OC/OV/SC detection with programmable or ≥X µs debounce, integrated MOS gate drive for back-to-back FETs, and thermal trip with auto-restart or MCU clear. Do not replace with detection-only or latch-only parts without written approval.”
Relaxed version
“Primary protector may be sourced from TI / ST / NXP / Renesas / onsemi / Microchip / Melexis families with equivalent OC/OV/SC, MOS drive and debounce. If fixed shorter debounce or trip-only thermal is used, board-level RC or host confirmation shall be added. Cut-Tape / Partial Reel allowed for proto lots.”
Supplier checklist: (1) Confirm it is the version with debounce/filtering enabled; (2) Provide thermal trip / OT threshold code; (3) State if recovery is auto or requires power-cycle; (4) Small-batch: Cut-Tape / Partial Reel is acceptable.
Validation waveforms for primary protector tests including SC, OC and thermal trip with gate-off timing.
The following FAQs focus only on this page’s topic: a primary protector / pack FET placed at the very front of the battery path, with OC/OV/SC detection, MOSFET gate drive, debounce/filtering and thermal hooks. Questions about charging algorithms, gauging math or vehicle CAN logging are intentionally excluded here.
Does the primary protector have to be from the same brand as the charger IC?
No. Brand match is optional. What must match are: the OC/OV/SC ranges, the FAULT voltage level, and the “stop charging on protect” hook. When you swap brands, re-verify the blanking time so the new protector does not trip on the old adapter’s inrush.
How fast should the SC turn-off be for a pack high-side FET?
For real short circuits you want a µs-class turn-off, limited mainly by your MOSFET gate charge and the protector’s gate-drive current. If you chose large back-to-back FETs, capture the waveform to confirm the driver still forces a fast and symmetrical gate pull-down.
What to do if adapter inrush keeps triggering SC?
First check if the device’s SC/OC blanking is fixed and too short. If it is configurable, extend it. If it is fixed, add board-level RC or delay the charger’s inrush so the protector sees a calmer line. Add this as a BOM remark to block short-blanking substitutes.
Can the thermal trip monitor both the IC and the external MOSFET?
Only if the protector supports an external NTC or a thermal-alert input. Internal temperature sensors watch the IC die, not the hot FET copper. For FET heating, put the NTC close to the FET and feed it to the protector so derating/trip reflects real board temperature.
Can I use an industrial-grade protector first and swap to AEC-Q100 later?
Yes, but lock the behavior. Confirm OV/SC priorities, debounce defaults and the recovery method (auto, power-cycle, MCU clear). If the automotive version changes any of these, record it in the BOM so production does not mix parts with different protection timing.
OV threshold of the alternative device is 200 mV higher — is it safe?
Often yes, but it depends on what sits in front. If a buck/charger expects a clean, lower ceiling, remeasure the input seen by that device. On multi-cell AFEs a higher OV can change how fast the pack is isolated, so run the validation tests from Chapter 8 again.
Gate-drive current is lower than my MOSFET needs — can I add a gate driver?
You can, but then the protector’s FAULT-to-gate-off timing must still be verified through the added stage. In SC tests the new driver must pull the gate down within the original safety window. Capture the scope shot and attach it to the BOM notes.
Should I synchronize primary protector and downstream eFuse faults?
Recommended. Route the primary protector’s FAULT to the downstream eFuse/charger so the system logs a single, obvious source. If you leave them independent, you may see “two faults for one event,” which makes field debugging harder and confuses the BMS host.
If the input port already has protection, do I still need a pack-level primary protector?
Yes. Port protection mainly shields against what comes from outside. The pack-level primary protector also shields the battery from internal faults or reverse/system backfeed. Their responsibilities are different, so you keep both layers in a BMS design.
Can I use MOSFET current sense instead of a shunt for SC?
It is possible, but accuracy and repeatability depend on the FET you picked and temperature. Many protectors are tuned for external sense resistors, so if you move to MOSFET-sense you must re-characterize the SC trip point and document the test in validation reports.
I can only buy the same device in a different package — can I drop it in?
Function will likely match, but you must re-check thermal path, pinout of FAULT/sense pins, and coupling into the sense line. Even a package swap can change debounce behavior in noisy layouts, so repeat the five tests from the validation chapter.
How can my BMS host tell false trips from real SC events?
Feed the primary protector’s FAULT directly to the host and sample current/voltage at the same instant. If the host sees a FAULT but no corresponding high current, tag it as a false/connector event. Some devices expose a fault source bit — log it and clear via host.
This FAQ only covers the Primary Protector / Pack FET topic in the “Battery Charging / Gauging / Protection / BMS” hub. Charger-level, gauging-level, vehicle-level or cloud-log questions belong to their own pages.
