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Role & Placement of the Primary Protector
A primary protector (also called a pack FET front-end) is the very first hard-protection device in a battery-powered system. Its job is simple but strict: cut off OC/OV/SC faults before the charger, eFuse, or BMS host has to deal with them. This ensures that downstream power-path, charging controllers, or gauging ICs always see a safe, pre-filtered input, even when the external power source or the load behaves badly.
In other words: this device acts first. It sits between the input (port or battery) and the rest of the system. Every other protection (secondary eFuse, charger-internal safety, BMS-level diagnostics) is assumed to operate after this primary cut. That is why we treat it as a separate topic instead of mixing it with charger or multi-cell BMS content.
Upstream first, downstream later
The primary protector removes dangerous energy right at the entry point, so chargers/eFuses don’t need to survive every abnormal event.
Why it needs its own page
OC/OV/SC, MOSFET gate driving, thermal trip and debounce are often not delivered together in one IC across all brands, so small-batch replacement can easily break one piece of the chain.
What we do not discuss here
No CC/CV, no JEITA, no multi-cell balancing — these are kept in their own charging/BMS chapters to avoid intent overlap.
Typical path 1: USB-C / vehicle DC-in → primary protector → charger / buck → battery.
Typical path 2: Battery → primary protector → system load. This isolates the pack when the load misbehaves.
Protection Channels: OC / SC / OV — Triggers & Priorities
A primary protector makes all of its decisions on top of three fault channels: over-current (OC), short-circuit (SC), and over-voltage (OV). These channels do not fire the same way: SC is microsecond-level and must turn the MOSFET off immediately; OC usually integrates over a small time window; OV is often a fixed or latched threshold. Because vendors ship different blanking, filter and threshold defaults, any cross-brand replacement in small-batch builds must be re-tested.
This section only explains when the protector trips and which output it asserts. It does not explain MOSFET gate-current sizing, thermal derating or charger termination. Those are intentionally kept out to avoid overlapping with charging/BMS chapters.
OC (Over-Current)
Handles sustained or quasi-sustained overloads (from a few ms to hundreds of ms). A timer or integration window is common so that short inrush events do not trip OC. Some devices fix the OC level; others let you set it with a resistor — sourcing must check which type you are buying.
SC (Short-Circuit)
Handles instant faults (µs). Normally drives the MOSFET gate directly to protect FET and battery. This path is the most likely to false-trip because of connector sparks, motor start-ups or switching spikes — later chapters will apply debounce/filtering.
OV (Over-Voltage)
Handles abnormal input voltage or back-feed. Some ICs implement latch + manual clear; if your board does not have a host to clear it, swapping to such a device will break your design.
Common priority is SC > OC > OV so the fastest and most dangerous fault wins first and pulls the gate down. A few devices, however, prioritize OV to protect the port/source. Therefore, when you replace the original primary protector with a different brand or with an automotive-grade variant, always confirm the fault-priority table — do not assume it is SC > OC > OV.
Relation to charging pages: we only state here that the charger/buck should see a safe input after this protector. We do not describe CC/CV, JEITA thermal control, or multi-cell charger controllers.
MOSFET Gate Driving & Pack FET Topologies
The primary protector does not just detect OC/SC/OV — it must also push and pull the pack MOSFET gate fast enough so the fault is actually removed from the battery path. This is where many small-batch designs fail: the detection works, but the FET is large or back-to-back, the gate-drive current is too small, and the short-circuit is not cut fast enough.
This section explains why the IC needs a built-in driver, how single FET vs back-to-back FET changes the drive requirement, what to check for high-side layouts, and how to write a simple BOM remark so purchasing does not downgrade gate-drive capability when switching brands.
Why the IC must drive
SC is a µs-level event. If gate turn-off is left to a slow or external driver, the pack FET stays on longer and the battery still sees the fault energy.
Single vs back-to-back
Single FET is easy to cut; back-to-back (source-to-source) gives reverse isolation but needs more gate current. Some brands cannot drive two big FETs cleanly.
High-side considerations
Pack-front protectors are often high-side. That means a gate-boost or high-side driver is needed. Some ICs integrate it, others require an external driver.
When you choose a larger, lower-RDS(on) MOSFET, its gate charge (Qg) increases. To keep the SC turn-off fast, the primary protector must be able to sink that charge in the same short time window. If the driver current is lower than the Qg needs, the FET turns off slowly and the SC protection becomes unreliable.
BOM remark (keep this when sourcing):
“Primary protector shall be able to drive back-to-back N-channel MOSFETs on the pack high side. Gate-drive current must be sufficient to meet the SC turn-off time of the reference design. Do not replace with versions with lower gate-drive current.”
This section does not cover power MOSFET selection (RDS(on), package, copper spreading). That topic lives in the battery protector hardware page to avoid overlap.
Thermal Trip & Derating Hooks
Not every primary protector ships with the same thermal strategy. Some only monitor their own die temperature, some accept an external NTC close to the pack FET, and some can react to an external thermal warning from the charger/host. When sourcing a replacement device, this is often where behavior silently changes — and it becomes pain point for small-batch production.
Internal sensor
Easy and cheap. But it measures the IC package, not the MOSFET. If the FET is off-chip, the IC may never see the real hot spot.
External NTC
Placed near the FET or copper pour, it reflects the actual dissipation. Best option when the FET is large or off-board.
Host / charger input
Some protectors just take a thermal-warning pin from upstream. If the new brand does not have this pin, logic must move to MCU.
Once temperature is known, the protector can react in two main ways:
- Derate: first reduce the allowed current, then disconnect if heat continues. This keeps the system alive.
- Trip: open the pack FET immediately once a thermal threshold is hit. Some devices require power-cycle or MCU clear to recover.
Sourcing check: “Does the replacement device support NTC-based derating, or is it trip-only? Does it auto-restart after over-temp, or does it require MCU/power-cycle to clear?”
This section does not cover system-level thermal runaway protection or multi-node pack sensing. Those belong to higher-level BMS pages.
Debounce & False-Trip Immunity
This section addresses the most common field complaint for primary protectors: “SC/OC keeps tripping even though nothing is really shorted.” In small-batch designs this usually happens right after a brand swap, because the new device has a shorter or fixed blanking time and the board-level inrush/connector noise is not filtered anymore.
To make the protector robust, we need IC-side debounce (blanking, multi-sample, peak suppression) and system-side debounce (clean ground routing, staggered inrush, optional MCU confirmation). All of them should be recorded in the BOM so purchasing does not buy a “short-blanking” version by accident.
Cable / adapter plug-in
Connector sparks and unsymmetrical rise cause narrow spikes → looks like SC.
High dv/dt buck start-up
Shared line with another DC/DC or charger → protector sees noisy current envelope.
Motor / inductive loads
Startup = one or more current bumps → without debounce they look like shorts.
Vehicle-port wobble
Automotive jacks vibrate → series of micro-dropouts → many protectors will trip.
IC-side debounce
- Blanking time (hundreds of ns – few µs)
- Multi-sample and use max/avg of 2–3 reads
- Peak suppression / small RC in front of sense
System-side debounce
- Sense pin on a clean analog return
- Stagger inrush of charger vs protector check
- MCU 2nd confirmation for non-critical trips
When changing brands, verify:
- Is the blanking fixed or programmable?
- If fixed, is it shorter than the original part?
- Are OC and SC using the same or different blanking times?
- If programmable, what is the method (resistor / I²C / EEPROM)? → must go into BOM.
BOM remark (anti-false-trip):
“Primary protector debounce shall be ≥ X µs to avoid SC false trips caused by adapter inrush. Do not replace with devices that have fixed shorter blanking.”
