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Concept & Placement in the Charging Branch
Active balancing in this context means moving usable energy from a higher-SOC cell to a lower-SOC cell instead of burning it as heat. That is why realistic efficiency sits around 70–90% depending on the chosen topology, switching devices, and how well the transfer is scheduled.
We keep this page inside the charging branch because balancing here can reuse what the charger already knows: CC/CV state, JEITA thermal limits, and power-path priorities. When cell voltages are naturally rising and pack temperature is already being watched, active balancing can run with proper derating and shutoff rules.
This page does not merge with the passive balancing page. Passive balancing usually bleeds excess energy through a resistor, triggers on simpler conditions, and can be allowed to run even during parking or storage. Active balancing, by contrast, opens a power path between cells and must be controlled by the charging state machine to avoid runaway heating or measurement corruption.
Scope for this subpage is 2S–6S packs first. For higher cell counts, active balancing can still belong to the charging branch, but it should be applied per segment (for example, 12S segmented into two 6S blocks) so it doesn’t conflict with pack-level BMS coordination pages.
Topology Options: Inductive vs Capacitive Shuttle
Active cell balancing can be realized in two main power-path styles. Inductive transfer uses a magnetics-based path (half-bridge or full-bridge driving an inductor) to push energy from a higher-SOC cell to a lower-SOC cell with relatively high efficiency. Capacitive or flying-cap transfer uses one or more capacitors that alternately connect to different cells and “carry” charge between them.
Inductive transfer is ideal when the SOC gap is large or when the system wants to converge quickly during the available charging window; but it costs more, requires better gate driving, and the EMI needs to be controlled so it does not corrupt cell measurements. Capacitive transfer is more budget-friendly and simpler to route, which makes it a good fit for compact 2S–6S BMS boards, but its overall balancing rate depends on how many stages and how the flying capacitors are sequenced.
Regardless of the topology, efficiency / duty / frequency must be under charging control. If an active shuttle runs freely during the CV or taper phase, it can generate extra heat right when the charger is trying to finish gracefully under JEITA limits. That is why this page explicitly says: the active shuttle gets its measurement from the measurement domain (AFE → clean cell voltages), but its decision gates come from the charging domain (CC/CV, temperature, power-path).
Scheduler & Coordination with CC/CV
The active balancer is not a free-running function. It must obey the charger state machine (Pre, Fast, CV, taper) and the thermal/JEITA gates that the charging branch already uses. In early stages we can be more aggressive, but in CV/taper we must reduce duty or pause to let the pack finish gracefully.
During Pre / Fast charge, a shuttle can run with higher duty as long as the charger still has current headroom. During CV / taper, it should either lower the duty, do only small-ΔV trims, or pause completely. To keep heat predictable, active balancing should run before passive bleeding, and passive should only chase the last few millivolts.
Because the shuttle opens and closes power paths, its activity can disturb ADC readings. Therefore, cell-voltage sampling must happen either in the gap between balancing pulses or be corrected afterwards. Otherwise the AFE may think a cell is over/undervoltage while it is just being balanced.
Trigger sources for the scheduler:
- ΔV between cells exceeds a defined threshold (voltage-based trigger)
- ΔSoC from the gauging domain exceeds a defined threshold (SoC-based trigger)
- Time-slice / round-robin to avoid serving only the highest-SOC cells
Measurement, Filtering & Noise Immunity (Charging Scope)
Switching an active shuttle injects sharp edges into the cell harness. If measurement lines see those edges directly, the AFE can falsely report overvoltage or undervoltage even though the cell is healthy. That is why the measurement domain must get filtered, settled voltages and must know when the shuttle was active.
Hardware mitigation is to separate the sense pickup from the high dI/dt balancing node and add small RC or CM chokes on the measurement branch. Software mitigation is to define a valid sample window: sample only after the shuttle finished and the cell terminal voltage has stabilized. We only discuss the noise that is specific to charging-scope active balancing, not the high-voltage insulation topic from other BMS pages.
Keywords to preserve in this section: active cell balancing noise, flying capacitor balancing EMI, cell voltage sampling during balancing, ADC sampling window, CM choke for inductive balancer. Keep them close to the measurement description so search engines can map intent to this page, not to the protection or insulation pages.
Faults, Thermal Derating & BAL_DISABLE
Active balancing opens a real power path between cells, so its fault handling must be stricter than passive balancing. This section defines when to stop immediately (BAL_DISABLE), when to derate, and where to report. Reporting in this page goes only to the charging / BMS host; it does not directly command pack FETs.
Immediate BAL_DISABLE conditions:
- Shuttle/balancing path open or short — the energy path is no longer predictable, stop to prevent damage.
- Target cell temperature over limit — use the same thermal reference the charging domain uses (JEITA or charger exposed limit).
- ΔV cannot be reduced in CV — persistent imbalance during CV suggests cell aging or mismatch, so stop and report.
- Charging IC enters fault — if the charger is no longer controlling CC/CV or thermal derating, active balancing must stop too.
Derate, do not stop, when:
- Ambient / pack temperature is high but still within valid range.
- Charging current is already reduced by JEITA, so the balancer should follow that reduction.
- Pack internal temperature is uneven — limit the affected cell(s) instead of stopping globally.
Reporting path for balancing-related faults on this page is: active balancer → charging/BMS host → logging / user / fleet. It is not the place to trip pack FETs or trigger high-voltage insulation actions — those belong to other BMS pages.
Keywords to keep in this section: BAL_DISABLE conditions, active cell balancing fault, thermal derating for balancing, CV-stage imbalance reporting, charging-scope fault reporting.
IC Selection & 7-Brand Mapping (realistic)
In automotive BMS today, very few devices integrate a full active (inductive/capacitive) shuttle. Most AFEs from the seven brands give you: high-voltage cell measurement, passive balancing hooks, and digital control to tell an external stage what to do. The realistic pattern is: use the AFE for measurement/telemetry → add your own shuttle (MOSFET / bridge / HSD) → let the charging branch schedule it.
TI
Legacy active / “PowerPump-like” devices: BQ78PL114 (old, non-mainstream, supply must be confirmed). Current automotive-relevant AFEs such as BQ7961x, BQ76952/42 expose cell voltages and passive balancing, but an external inductive or capacitive shuttle is still needed for the kind of active balancing in this page.
ST
Devices like L9963E, L9961 come with balancing hooks but are mainly passive. For active transfer you add an external bridge or HSD stage and let the ST AFE control it.
NXP
MC33771C / MC33772C are typical passive-balancing AFEs, but they provide SPI / I/O lines that can drive external balancing switches. This makes “external active board + NXP AFE” a practical path.
Renesas
ISL78600, ISL94216 are automotive BMS AFEs with passive balancing. Use them for measurement/telemetry; add your own shuttling stage if you want inductive/capacitive transfer.
onsemi
The strength is in BMS/HEV-related discretes and AFEs. There is no single-chip “do-it-all” active balancer; the realistic route is “onsemi MOSFET + your MCU/AFE control”.
Microchip
A very workable pattern is: dsPIC33EV / dsPIC33CH for control, plus external MOSFET / H-bridge power stage → your own active balancer. This is especially friendly to small-batch/repair markets where you must source devices flexibly.
Melexis
There is no turnkey active balancer IC, but current / Hall devices like MLX91208, MLX91216 can be used for efficiency feedback and fault detection around the shuttle path, which ties nicely back to Chapter 5.
Keywords to preserve: active cell balancer IC selection, BQ7961x active balancing add-on, L9963E balancing hooks, MC33771C external balancing switch, dsPIC active balancer, Melexis current sensing for balancing.
Small-Batch Procurement & Cross-Brand Alternatives
Active/charge-shuttle style balancing ICs are not widely available as single automotive parts. For small-batch orders, the realistic path is: pick an AFE that exposes cell voltages + basic control pins, then add your own inductive/capacitive shuttle board, and let the charging-branch scheduler coordinate it. This prevents purchasing from silently downgrading to a passive-only AFE.
Scenario 1: TI legacy part not buyable
Use major-brand AFE (TI / ST / NXP / Renesas) for measurement + generic MOSFET / high-side driver + your own balancing scheduler. This keeps the page in the charging branch even if the original IC is EOL or low stock.
Scenario 2: Lead time is too long
Swap to ST / NXP AFE as long as it exposes cell-voltage telemetry and a few GPIO/SPI-controlled outputs. That is enough to drive your external inductive/capacitive shuttle.
Scenario 3: Trader pushed “balancing” AFE
Some distributors ship AFEs that say “balancing” but are passive-only. For this page, that is not acceptable — you must tell purchasing not to replace an active-capable design with a passive-only AFE.
BOM remarks (copy/paste):
1) Requires external active-balancing stage, do not replace with passive-only AFE.
2) Balancing FET Rdson ≤ xx mΩ @ xx°C for xx A shuttle current.
3) Keep SPI/I2C register map compatible with [host MCU / main controller] for balancing scheduler.
Small-batch pitfalls to warn purchasing about:
- “Balancing” AFE that is actually passive-only.
- AFE exposes voltage but no GPIO / no register control for the shuttle.
- Thermal / Rds(on) specs not written → purchasing picks weaker FET → shuttle efficiency drops.
- Brand swap without checking SPI/I²C register compatibility → scheduler cannot run.
Frequently Asked Questions — Active Balancing in the Charging Branch
Can I mix passive balancing and an external inductive shuttle on the same pack?
Yes. In the charging branch you should run the active shuttle first to move real energy, then let the passive AFE channels finish the small ΔV. Make sure both respect the charger’s CC/CV state so they do not add heat at the end of charge.
During CC stage, can I run active balancing at full duty?
Only if the charger still has current headroom. In the charging branch, CC is the reference; the shuttle must read the charger’s limits and cap its own transfer current, otherwise it will steal current and make the pack hotter than the JEITA profile expects.
Can active balancing stay enabled in CV / taper?
Prefer to derate or pause in CV. In the charging branch, CV needs a quiet thermal situation to converge. Keep only small-ΔV trims or time-sliced moves; if imbalance persists in CV, raise a report instead of pushing more energy.
How do I stop the shuttle from fighting with JEITA-based derating?
Read the charger’s current limit and temperature stage first. In the charging branch, if JEITA has already reduced current, the shuttle must reduce duty or frequency too. Otherwise it will re-introduce heat and delay the end-of-charge decision.
Why do cell-voltage readings dip when the inductive shuttle kicks in?
Because the shuttle injects high dI/dt into the cell harness. In the charging branch you should sample only in the shuttle-off window, or tag those samples as “under balance” so the AFE will not flag false OV/UV events.
What signal should trigger an immediate BAL_DISABLE?
Shuttle path open/short, target-cell overtemperature, CV-stage imbalance that will not converge, or the charging IC entering its own fault. These are power-path events, so in the charging branch they must stop the shuttle right away.
How do I log transferred Ah for SOC correction?
Count energy moved by the shuttle (I × t) and add it to the gauging domain as a separate “balanced” channel. In the charging branch this prevents the main SOC estimator from drifting when cells are aggressively equalized.
Can I reuse the same shuttle hardware for 2S–6S packs?
Yes, as long as the AFE can expose each cell and the shuttle MUX can be time-sliced per pair. Keep the scheduler in the charging branch so it knows how many series cells are present and when the pack is in CV.
How do I avoid EMI from the shuttle getting into measurement?
Keep the measurement domain filtered (RC/CM), route sense away from high dI/dt nodes, and sample only in the shuttle-off time. This is the same rule from the charging branch measurement section.
If TI / ST AFE is on long lead time, which brands can I use?
NXP (MC33771C/72C) and Renesas (ISL78600/ISL94216) still expose cell voltages and SPI/I²C to drive an external shuttle. In the charging branch this is enough, because the real energy transfer is on your external board.
Is isolated gate driving mandatory on 6S inductive balancing?
It depends on your shuttle topology and how far the cell voltages spread. In the charging branch you only need isolation when the switch node rides on different cell potentials and your driver cannot withstand that common-mode.
How do I write a BOM remark to stop passive-only downgrades?
Add: “Requires external active-balancing stage, do not replace with passive-only AFE.” and “Balancing FET Rdson ≤ xx mΩ @ xx°C for xx A shuttle current.” This locks the design to the charging-branch active-balancer concept.