← Back to: eFuse / Hot-Swap / OR-ing Protection
Overview: Ideal Diode vs Schottky
At the same load current, Schottky OR-ing wastes power linearly (P ≈ I × Vf) and heats fast, while an ideal diode uses a low-RDS(on) MOSFET (P ≈ I2 × RDS(on)) with reverse-current blocking and a tunable ΔV priority window + hysteresis for clean switchover.
BOM note: OR-ing must use ideal-diode controller with reverse blocking; Schottky OR-ing is not allowed in production.
Architecture & Working Principle
Controller senses Vin − Vout against a precision window (with hysteresis) and drives an external MOSFET to achieve near-zero-drop forward conduction and fast reverse cutoff. Priority is defined by a tunable ΔV window and hysteresis.
Key formulas:
V_drop ≈ I_load × RDS(on,eq) + ΔV_ctrl |
V_rev_block ≥ |V_backup − V_main|max
Key Parameters & Thresholds
Use these thresholds to decide cross-brand replacement on the spot. Record them in BOM and test procedure so purchasing and validation share the same criteria.
Replacement redline: if ΔV_priority shifts > ±20 mV or t_sw slows > 2×, you must retune comparator RC / downstream PG-RESET and update BOM remarks.
I_load_max
Peak/continuous current under OR-ing. Validate at thermal steady state; if I_peak/I_rms > 1.7, do separate peak thermal check.
V_drop@I_max (target)
Line-end Kelvin sense. Recompute RDS(on)_req ≤ (V_drop_target − ΔV_ctrl)/I_max.
V_rev_block & I_rev_leak
Block ≥ |V_backup − V_main|max × 1.2. Record I_rev_leak_max@Thot for holdup/standby math.
ΔV_priority & Hys
Start point: ΔV=40 mV, Hys=15 mV. Tune for cable drop + noise. If ΔV shifts > ±20 mV, retune RC/logic.
t_sw (switchover time)
Capture Gate & Vout together; constrain ΔV_dip & µs-scale timing for DC/DC tolerance.
Gate stability @ light load
Start Rg=5–20 Ω + small C_gate; check Miller-induced ringing near the window.
VIN range & drift
Keep ΔV_ref drift < ±20% of ΔV_priority across temp/line/load.
PG/FAULT/Telemetry
If a gateway exists, PG or I²C/PMBus is required; otherwise synthesize PG.
| BOM/Procedure keys | Notes |
|---|---|
| I_load_max, V_drop_target@I_max, V_rev_block_min, I_rev_leak_max@Thot | Thermal steady state; reverse at high-T |
| DeltaV_priority, Hys, t_sw_max, R_g, C_gate | Window + hysteresis + gate damping |
| VIN_range, DeltaV_ref_drift, PG/FAULT, I2C/PMBus | System observability & control |
Engineering Acceptance Criteria
| Metric | Target / Limit | How to measure |
|---|---|---|
| V_drop@I_max | ≤ 40–60 mV @ 5 A (project-specific) | Kelvin at line ends; read at thermal steady state |
| V_rev_block | ≥ |V_backup − V_main|max × 1.2 | Measure at hot and cold; log worst case |
| I_rev_leak@Thot | ≤ 50% of standby budget | Read 60 s after cutoff; verify meter burden |
| ΔV_priority / Hys | Start 40 mV / 15 mV; ΔV drift within ±20 mV | Sweep source delta; record switch & return points |
| t_sw & ΔV_dip | t_sw ≤ 5 µs; ΔV_dip ≤ 60% of DC/DC UV threshold | Capture Gate & Vout simultaneously |
Edges & Corner Cases to Validate
- Long cable drop: ensure ΔV_priority covers drop + noise peaks; retune RC if chatter appears.
- Low temp: RDS(on) drops, but gate slew can slow; re-check t_sw vs ΔV_dip.
- High temp: I_rev_leak rises; re-check holdup window and standby budget.
- External backfeed (service supply): verify V_rev_block and eFuse clamp consistency.
- Asymmetric sources: slightly stiffer backup can “steal” priority if ΔV window is too small.
Design Calculations & Device Selection
Target V_drop → RDS(on) requirement
RDS(on)_req ≤ (V_drop_target − ΔV_ctrl)/I_load_max. If paralleled, apply 1.15–1.25 imbalance factor.
Conduction loss & temperature
P_cond ≈ I_rms² × RDS(on)(Tj); use temp coefficient (0.3–0.6%/°C). Validate at thermal steady state.
SOA check (if no Hot-Swap)
Verify VDS–ID–t with surge/plug pulses (µs–ms). If tight, prioritize SOA before squeezing loss/Qg.
Gate loop stability
Start Rg=5–20 Ω; add small C_gate if needed. Use slew-control/soft-off to shape t_sw and ΔV_dip.
BOM note: Select MOSFET Rds(on) ≤ __ mΩ @ Tj; verify SOA for hot plug & surge.
Worked Example — From Targets to Device Picks
Given (project targets)
I_load_max = 5 A; V_drop_target = 50 mV; ΔV_ctrl = 20 mV;
I_rms = 4 A; Tamb = 40°C; θJA ≈ 40–60 °C/W.
Step 1 — RDS(on) requirement
RDS(on)_req ≤ (V_drop_target − ΔV_ctrl) / I_max = (50−20)mV / 5A = 6 mΩ.
Step 2 — Conduction loss @ Tj
Assume 25→100°C drift ~ +40%: RDS(on)(Tj) ≈ 6 mΩ × 1.4 = 8.4 mΩ.
P_cond ≈ I_rms² × R(Tj) = 16 × 0.0084 ≈ 0.134 W.
Step 3 — Thermal headroom
ΔT ≈ P_cond × θJA = 0.134 × (40–60) ≈ 5–8 °C.
Good margin; verify with IR camera @ steady 5 A.
Step 4 — SOA & surge
Check VDS–ID–t curve for hot-plug and backfeed pulses (µs–ms). If tight, prefer a MOSFET with larger SOA even at slightly higher RDS(on).
Step 5 — Gate stability & t_sw
Start Rg=10 Ω; add small C_gate if light-load ringing observed.
Target t_sw ≤ 5 µs and ΔV_dip below 60% of DC/DC UV threshold.
System Integration & Timing
Define who turns on first and who turns off first. Interlock PG/FAULT so the OR-ing switchover does not create dips or backfeed, and debounce the comparator near the ΔV window.
Interlock: PG_eFuse → EN_IDC (or gate-allow). During switchover, assert a short RESET/PG mask (100–500 µs) to inform downstream DC/DC.
Integration Checklist & Debounce Rules
Signal interlocks
PG_eFuse → EN_IDCorallow_gate.- Switchover: assert short PG/RESET mask (100–500 µs) to DC/DC.
- Holdup: size output cap for worst ΔV_dip and load window.
Comparator debounce
- RC front-end τ start: 10–50 µs (tune to noise spectrum).
- If IC has digital debounce, start 5–20 µs.
- Do not overfilter load steps; verify t_sw & ΔV_dip after change.
Priority window tuning
- Start ΔV_priority=40 mV; Hys=15 mV.
- Increase ΔV if cable drop > window/2 or ripple > Hys/2.
- Re-run “20× toggles” test (main→backup→main) with no chatter.
BOM Remark (copy & paste)
OR-ing must use an ideal-diode controller with reverse-current blocking. Set ΔV_priority=__ mV, Hys=__ mV, t_sw_max=__ µs. MOSFET Rds(on) ≤ __ mΩ @ Tj; verify SOA for hot plug & surge. Record V_drop_target@I_max=__ mV@__ A, V_rev_block_min=__ V, I_rev_leak_max@Thot=__ µA. If ΔV_priority drifts > ±20 mV or t_sw slows > 2×, retune comparator RC/PG timings and update this remark.
Brief Holdup & Dropout Dip Control
Size a small holdup network so Vout rides through source dropout without reverse discharge to the failing source. Validate both the permitted sag and reverse current under worst load.
Holdup sizing
Core formula:
C_hold ≈ I_load × t_hold / ΔV_allow
(include DC/DC restart margin within ΔV_allow).
Reverse discharge control
Ideal diode must cut off backflow during dropout. If the downstream bulk is large, shape gate-off and consider an RC snubber at the post-diode node to tame spikes.
Test method (pass/fail)
Pull main source to 0 V with a fast MOSFET switch; measure Vout sag and t_hold. Probe reverse current (I_rev) at the
ideal-diode input; must stay within spec.
Fault Modes & Edge Cases
Pre-converge “rare” failures by validating the typical weak spots. Remember: an ideal diode solves direction and drop; it is not a short-circuit protector.
Light-load oscillation (1–10 mA)
ΔV noise near the window makes the gate chatter. Cure: raise Rg, add small C_gate, or increase comparator filtering slightly.
Mis-priority by cable drop / ground asymmetry
Take Kelvin at line ends; increase ΔV_priority; flatten ground returns. Verify with 20× main↔backup toggles.
Reverse mis-conduction at high T
RDS(on) and comparator drift can shift thresholds. Cure: raise Hys; validate cutoff at hot corner.
Short-circuit at source
If no Hot-Swap/eFuse upstream, do not expect current limiting from the ideal diode—cascade a protection stage.
Conclusion: An ideal diode solves direction and drop. It does not limit surge/short energy—always pair with an upstream Hot-Swap/eFuse for protection.
Validation & Mass-Production Test Scripts
Turn bench procedures into Script Cards with inputs → actions → expected waveforms → OK/NG criteria. Keep it vendor-neutral and pasteable into SOP.
Priority Switchover Scan
- Setup: Two sources; Kelvin at line ends; normal DC/DC load.
- Sweep: Step Vbackup upward across ΔVpriority (10–20 mV/step).
- Measure:
t_sw,ΔV_dip@Vout, switch/return thresholds vs temp. - OK:
t_sw ≤ __ µs,ΔV_dip ≤ 0.6×UV_th, ΔV drift ≤ ±20 mV. - NG: Gate chatter > 2 toggles within 2 ms.
Reverse Blocking
- Setup: Force Vbackup > Vmain + margin.
- Measure:
I_rev_leak@Thot, cutoff propagation time. - OK:
I_rev_leak ≤ __ µA@__°C, cutoff ≤ __ µs. - NG: Any backfeed spike > __ mA for > __ µs.
Light-Load Stability (1–10 mA)
- Sweep: 1→10 mA; inject small ripple near ΔV window.
- Observe: Gate ringing, Vout wander.
- OK: No sustained oscillation; gate cycles ≤ __ with < __ Vpp.
- Fix: ↑Rg, +Cgate, widen ΔV/Hys or add RC front-end.
Hot Soak Re-validation
- Condition: Tj=95–110 °C.
- Repeat: Cards 1–3; log worst case.
- OK: No spec regression; ΔV/Hys within drift budget.
Brief Holdup
- Cut: Pull main source to 0 V fast.
- Check:
t_holdvsΔV_allow, reverse current. - OK:
t_hold ≥ __ ms;I_revwithin spec; no brownout restart. - If NG: ↑Chold, add post-diode snubber, retime PG mask.
| Card | Scope Channels | Timebase / BW | Probes | Temp |
|---|---|---|---|---|
| Priority Switchover | CH1: Gate, CH2: Vout, CH3: Vmain, CH4: Vbackup | 1–10 µs/div, 20 MHz limit | 10× passive + Kelvin clips | Amb / Hot |
| Reverse Blocking | CH1: Vin, CH2: I_rev (sense) | 0.5–5 µs/div, 50 MHz | Current shunt or hall | Hot |
| Light-Load, Holdup | CH1: Gate, CH2: Vout, CH3: Iout | 10–100 µs/div | 10× passive + DMM logging | Amb / Hot |
OK/NG paste block: t_sw ≤ __ µs, ΔV_dip ≤ 0.6×UV_th, ΔV_priority drift ≤ ±20 mV, I_rev_leak ≤ __ µA@__°C, no chatter @1–10 mA, t_hold ≥ __ ms.
Small-Batch Procurement & Cross-Brand Alternatives
Use three replacement paths and a capability field map to avoid Schottky fallbacks. Redlines force timing/BOM updates before release.
A → A (same brand/series)
Pin-compatible; verify ΔVpriority, Hys, tsw, V_drop@Imax, V_rev_block, I_rev_leak. Minor RC/PG retune only.
A → B (cross-brand, same capability)
If tsw > 2× or ΔVpriority differs > ±20 mV → retune comparator RC + DC/DC PG/RESET; update SOP and BOM.
A → C (higher capability)
Lower RDS(on)/stronger reverse; watch package/thermal/layout cost. Re-check SOA and light-load stability.
| Field | Why it matters |
|---|---|
| ΔV_priority, Hys | Controls leader selection and chatter immunity. |
| t_sw | Ties to ΔV_dip and DC/DC PG mask margin. |
| V_drop@I_max | Thermals and efficiency at steady current. |
| V_rev_block, I_rev_leak | Backfeed safety and standby loss at hot. |
| PG/FAULT/I²C | Observability; audit trail; gateway integration. |
Redlines: ΔVpriority drift > ±20 mV, tsw > 2×, I_rev_leak@Thot > standby budget, or missing PG/telemetry → retune timing and update BOM/SOP before release.
BOM Hook (copy & paste): Alternatives must be within TI / ST / NXP / Renesas / onsemi / Microchip / Melexis. Cross-brand changes require capability mapping (ΔV_priority, Hys, t_sw, V_drop@I_max, V_rev_block, I_rev_leak, PG/FAULT/I²C) and BOM/SOP updates.
PCB Layout & Thermal Design Essentials
Avoid the trap “drop looks fine, thermals fail”. Use line-end Kelvin sense for ΔV window integrity, minimize hot loop, share ground reference with eFuse/Hot-Swap, and quantify heat with IR + θJA.
Current path & sense
- Shortest wide loop: Source → MOSFET → Load return.
- Kelvin sense at line ends; branch after pad fillet.
- Guard comparator inputs; keep 2–3 mm away from heat island.
Ground & timing
- Use same reference point as eFuse/Hot-Swap PG/FAULT.
- Star logic returns; keep di/dt paths off the star.
- Prevent ΔV window bias from cable/ground asymmetry.
Gate stability
- Short shielded Gate–Source loop; Rg at the pin.
- Fix light-load chatter: ↑Rg (5–10 Ω), +Cgate (10–100 pF), or input RC.
Thermal heuristics
- Pcond ≈ Irms2 × RDS(on)(Tj); ΔT ≈ P × θJA,eff.
- 1 oz copper: 10–15 mil/A for ≤10 °C rise (tune by stackup/air).
- ≥ 1–2 stitching vias/A near pads; aim ≥300–600 mm²/W island.
Quantitative checks
Compute V_drop@I_max and P_cond at Tj. Validate with IR camera (10–15 min soak). Acceptance: ΔT_sink ≤ __ °C @ __ A; Tj ≤ __ °C; ΔVpriority (line-end sense) within ±20 mV.
BOM Remarks & Compliance Checklist
BOM remark (paste-ready)
OR-ing must use an ideal-diode controller with reverse-current blocking. Priority window ΔV_priority = __ mV; hysteresis = __ mV; t_sw ≤ __ µs. V_drop ≤ __ mV @ I_max = __ A; reverse blocking ≥ __ V; I_rev_leak ≤ __ µA @ __°C. Select MOSFET Rds(on) ≤ __ mΩ @ Tj; verify SOA for hot plug/surge. PG/FAULT connected to MCU; eFuse/Hot-Swap timing coordinated. Alternatives limited to TI / ST / NXP / Renesas / onsemi / Microchip / Melexis; update cloud mapper on cross-brand.
Compliance — Electrical
- ΔVdip ≤ __ mV (≤ 0.6× DC/DC UV threshold).
- No gate chatter at 1–10 mA light-load sweep.
- Irev_leak ≤ __ µA @ __ °C; no backfeed spikes > __ mA for > __ µs.
- thold ≥ __ ms at MP load; no brownout restart.
Compliance — Timing & Telemetry
- ΔVpriority within ±20 mV; Hys within spec (line-end sense).
- tsw ≤ __ µs; if > 2× vs EVT → retune RC + PG mask.
- PG/FAULT/telemetry present & polarity verified.
Compliance — Thermal
- ΔT_sink ≤ __ °C @ __ A; Tj ≤ __ °C.
- IR hotspots align with copper choke points.
- Stitching vias & island area meet design targets.
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FAQ
When must an ideal-diode controller be used instead of Schottky OR-ing?
Use an ideal-diode controller whenever continuous current exceeds ~1–2 A, thermal budget is tight, or reverse-current blocking is mandatory. Compare losses: Schottky uses P≈I×Vf, while ideal diode uses P≈I²×RDS(on). If IR results show sink temperature rise > 30–40 °C at nominal load, replace Schottky OR-ing in production rails.
How large should ΔV_priority be to beat cable drop without false switching?
Start with 20–40 mV and increase to exceed worst-case line-end cable drop plus noise margin. A practical rule is ΔV_priority ≥ |ΔV_cable|worst + 10–20 mV, with hysteresis about 30–60% of ΔV_priority. Always sense at the connector (line-end Kelvin) and sweep backup voltage in 10–20 mV steps to verify chatter-free transitions.
How do I suppress gate chatter at light load (Rg, small Cgate, window filtering)?
Raise gate resistance by 5–10 Ω and add a 10–100 pF gate capacitor to slow edges just enough to avoid oscillation. If needed, insert a small RC at the comparator input to desensitize the window. Re-check that tsw still fits the PG/RESET mask and that ΔV dip during switchover remains within limits.
How do I calibrate reverse-block threshold and leakage when cross-branding?
Match Vrev_block and Irev_leak@hot to the existing standby budget and protection margin. Validate cutoff propagation time and measure leakage 60 seconds after source removal at hot corner. If leakage increases, update the power budget, verify thermal rise, and document the new acceptance limits in the BOM and SOP.
Vout spike is excessive at switchover—what should I tune first?
Tune in this order: ① increase ΔV_priority and set adequate hysteresis to eliminate chatter; ② adjust tsw via Rg/Cgate; ③ add a small RC snubber after the ideal-diode stage. Redline: ΔV_dip ≤ 0.6× the DC/DC UV threshold. Capture gate and Vout on a µs timebase with a 20 MHz bandwidth limit.
How do I quantify the RDS(on) versus Qg trade when selecting the MOSFET?
Use the figure-of-merit FoM ≈ RDS(on) × Qg and check against thermal and switching targets. Lower RDS(on) cuts conduction loss; higher Qg slows transitions and can increase ΔV dip. Validate at the final Rg/Cgate values and confirm both steady-state temperature rise and switchover timing margins.
How should PG/FAULT be interlocked with an upstream eFuse/Hot-Swap?
Gate enable for the ideal-diode should follow the eFuse PG. The ideal-diode PG/FAULT then informs the DC/DC PG/RESET path. Use a consistent ground reference and mask the DC/DC PG during OR-ing transitions. Verify no reverse current during either device fault and that all timing edges remain within the PG mask envelope.
How do I size C_hold for brief holdup without causing reverse discharge?
Use C_hold ≈ I_load × t_hold / ΔV_allow, adding headroom for the DC/DC startup dip. Place the capacitor after the ideal-diode stage so it cannot backfeed a collapsing source. If spikes appear, add a small post-diode snubber. Test by dropping the main source to zero and verifying hold time and reverse current limits.
Cable-drop asymmetry causes wrong priority—how should I route and sample?
Sense both sources at the line ends with symmetric Kelvin routing and returns. Increase ΔV_priority to exceed worst-case cable drop. Avoid mixing grounds across the comparator window, and shield sense lines from the hot current loop. Validate by heating or cooling cables and confirming the window does not drift into false priority.
Reverse leakage grows at high temperature—what’s the criterion and remedy?
Set a standby budget for Irev_leak@hot and treat overruns as NG. Remedies include choosing a device with higher reverse-block robustness, widening hysteresis, improving layout creepage, and selecting a MOSFET with better hot leakage performance. Confirm after a 95–110 °C hot-soak and measure 60 seconds after source removal to avoid transient artifacts.
How can MCU-forced priority coexist with the analog window (arbitration)?
Treat the analog window as primary safety and allow the MCU to override only within guard rails. Firmware must respect ΔV_priority and hysteresis, apply PG masks during transitions, and time-limit overrides. Log the cause of arbitration to aid failure analysis. Validate with a state-machine trace and confirm no reverse current during forced priority.
After cross-brand replacement in small batches, what must be updated?
Update BOM and SOP with ΔV_priority, hysteresis, tsw, V_drop@I_max, V_rev_block, I_rev_leak, and PG/FAULT/I²C polarity. Keep vendors limited to TI, ST, NXP, Renesas, onsemi, Microchip, and Melexis. Refresh the cloud telemetry mapper keys to align field names and thresholds before release. Re-run the validation scripts at hot corner.
