Role & Noise Paths Overview

This section sets the stage: why a simple 0.1 µF on an NR pin can cut reference noise by 10 dB, and how to estimate how much VIN ripple will appear on V_REF.

• Why does a 0.1 µF NR capacitor often reduce low-frequency noise by >10 dB?
• If VIN carries 100 mV_pp ripple, what fraction will leak onto the reference output?

Three Main Noise & Ripple Sources

For a practical noise bypass strategy, it helps to think in terms of three distinct contributors:

• Internal noise → OUT: op-amp broadband and 1/f noise, bandgap or buried-zener noise, shaped by internal filtering and external NR capacitors.
• VIN ripple → internal circuitry → OUT (PSRR): line ripple and upstream converter noise that leak through finite PSRR, especially where the PSRR curve dips with frequency.
• Load dynamics → OUT & divider injection: ADC/DAC sampling, switch arrays and sense dividers that feed current pulses and noise back into the reference output node.

The bypass pins and RC networks discussed in later chapters work by reshaping these paths in frequency: reducing low-frequency 1/f noise, attenuating VIN ripple, and isolating load-induced disturbances from the core reference node.

Bypass / NR / CAP Pin Archetypes

Different vendors use NR, BYPS, CAP or FILTER pins to expose internal reference nodes. Each archetype maps to a slightly different internal circuit and set of limits for capacitor value, dielectric and ESR. Getting these right is key to safe noise reduction.

Noise and Ripple Model

This section turns “add a capacitor” into a simple noise and ripple model. The goal is not a full control-theory derivation, but a practical way to estimate how bypass networks move poles, reshape spectra and reduce 0.1–10 Hz noise and low-frequency ripple.

Simplified small-signal picture

A useful mental model splits the reference into three contributors and a few first-order poles:

• Internal noise: bandgap and amplifier noise, filtered by internal networks and the NR capacitor.
• VIN ripple: upstream ripple seen through any VIN RC filter and the device PSRR over frequency.
• Load-induced noise: current pulses from ADC, DAC or switches multiplied by the output impedance profile.

With an NR capacitor, the dominant effect is a low-pass pole at the internal reference node. For practical work you can treat the pole frequency as:

f_p,NR ≈ 1 / (2π · R_eq · C_NR) – R_eq is the effective resistance seen at the NR node, and C_NR is the external NR capacitor.

VIN ripple and PSRR with VIN RC

A series resistor and decoupling capacitor on VIN form a first-order low-pass with corner frequency:

f_c,VIN ≈ 1 / (2π · R_VIN · C_VIN)

VIN ripple first passes through this RC, then through the reference PSRR curve. In magnitude terms, the effective transfer from VIN ripple to VREF can be approximated as an RC low-pass multiplied by the PSRR attenuation. The intent is not to calculate every point, but to choose R_VIN and C_VIN so that the worst ripple band sees meaningful attenuation before the PSRR dips.

Integrating noise in 0.1–10 Hz and other bands

Manufacturers often specify reference noise as a spectrum density, in nV/√Hz, plus an integrated 0.1–10 Hz figure. In practice you can think in terms of three bands:

• Very low frequency (0.1–1 Hz), dominated by drift-like behaviour.
• Low frequency (1–10 Hz), dominated by 1/f noise and most relevant for slow ADCs and sensors.
• Mid-band (10 Hz to tens of kilohertz), where noise tends to flatten toward broadband levels.

Increasing C_NR moves the NR pole downward and “shaves” the spectrum in the 1–10 Hz band. The integrated 0.1–10 Hz noise typically drops by several decibels until the pole sits well below the upper edge of that band, after which further increases bring diminishing returns and longer start-up time.

A simple noise budget expression

For most designs a three-term root-sum-square estimate is sufficient:

V_noise,total ≈ √( V_internal² + V_VIN² + V_load² )

• V_internal: integrated internal noise after NR filtering, typically close to the 0.1–10 Hz specification when C_NR is near the recommended value.
• V_VIN: the part of VIN ripple that passes through the VIN RC filter and PSRR, integrated over the relevant frequency band.
• V_load: load current noise times the frequency-dependent output impedance, integrated over the band of interest.

Increasing C_NR and tuning the VIN RC mainly reshape the V_internal and V_VIN terms in frequency. V_load often needs to be measured in the lab and kept small by layout and decoupling rather than pure reference bypass.

Design Rules for Bypass Networks

With the noise model in mind, this section turns NR, VIN RC and OUT–NR RC options into a practical design flow. The aim is to pick R and C values that hit noise and ripple targets without breaking start-up timing or loop stability.

Step-by-step design checklist

1. Define the critical bandwidth and noise target. For example, 0.1–10 Hz noise for slow ADCs and sensors, or tens of hertz to tens of kilohertz for PLL and audio rails.
2. Start from the datasheet recommendations. Use the suggested values for C_NR, C_OUT and VIN decoupling as a baseline rather than inventing combinations from scratch.
3. Estimate key pole frequencies. Compute or approximate f_p,NR and f_c,VIN to see whether they sit below, inside or above the sensitive band.
4. Check the stability window. Confirm that C_OUT, C_NR and any additional capacitors keep total load capacitance and ESR within the ranges the datasheet allows.
5. Review start-up and transient behaviour. Make sure C_NR does not stretch start-up beyond system timing, and that R_VIN does not cause excessive droop during load steps.

Rules by topology

NR capacitor to ground

• Use the vendor’s recommended C_NR as the starting point and respect any maximum value limits.
• Increase C_NR within the allowed range if 0.1–10 Hz noise needs further reduction, but expect longer start-up time.
• Prefer C0G/NP0 for small values and high-quality X7R for larger values; avoid capacitors with high leakage or strong voltage dependence.

VIN RC pre-filter

• Choose C_VIN to place f_c,VIN below the dominant ripple band of the upstream regulator while keeping inrush current manageable.
• Select R_VIN in the tens to a few hundred ohms so that, at maximum load current, the voltage drop and start-up delay remain acceptable.
• Verify that the upstream LDO or DC/DC remains stable with the added RC network; check its datasheet for output capacitor and ESR limits.

OUT–NR RC network

• Keep R and C close to the values used in the reference design or application note; use vendor-provided ranges as hard boundaries.
• Adjust C within the recommended range to fine-tune low-frequency noise; avoid large changes to R unless the datasheet allows it.
• Treat this network as part of the compensation; changes should be validated in the lab with start-up, load step and noise measurements.

Common pitfalls to avoid

• Oversized C_NR causing slow start and POR failures. A large NR capacitor can stretch start-up so long that reset supervisors or microcontrollers time out before the reference settles.
• Excess total capacitance reducing phase margin. Combining big C_OUT with extra bypass capacitors can move poles and zeros into an unstable region if you ignore the C_load limits.
• Poor dielectric or high leakage on critical capacitors. Low-quality MLCCs may leak or drift, slowly shifting the effective reference voltage or introducing extra low-frequency wander.

Ripple Rejection vs PSRR and Load

Ripple on a reference rail has two main sources: ripple from VIN passing through finite PSRR, and ripple created locally by load current transients. This section separates these paths and shows how RC networks on VIN, NR and OUT change the ripple profile instead of relying on the reference alone to fix upstream or load noise.

VIN ripple path and PSRR over frequency

VIN ripple travels from the upstream regulator into the reference bias network and finally to the output. At each frequency f, the combination of any VIN RC filter and the reference PSRR decides how much of this ripple shows up on VREF.

• Upstream source: rectifier ripple, DC/DC switching ripple and control loop oscillations.
• VIN RC filter: provides a first low-pass corner that can remove a large chunk of mid-frequency ripple.
• Reference PSRR(f): defines the remaining attenuation from VIN node to OUT across frequency.

Where PSRR is strong, VIN ripple can be moderate without harming VREF. Where PSRR dips, extra VIN filtering is often required to keep ripple below the error budget of the ADC, DAC or sensor chain.

Load ripple path and output impedance

Load-generated ripple has a different nature. Switching resistor arrays, sampling ADCs and logic-driven muxes draw current pulses directly from the reference output node. These pulses produce voltage disturbances according to the frequency-dependent output impedance of the reference plus any C_OUT or RC network on the output.

• Current pulses: charge injection and sampling spikes at the ADC reference pin.
• Output impedance Z_out(f): the internal reference and its compensation network.
• External capacitors: C_OUT and RC networks that lower Z_out(f) in the bands where the pulses are strongest.

Good PSRR cannot cancel load-induced ripple, because it is created at the output node. Local decoupling, RC shaping and layout are the first tools for this path.

What RC at VIN, NR and OUT really do

Different RC locations attack different parts of the spectrum and different paths. It is helpful to think of three levers rather than a single “bypass capacitor” knob.

• VIN RC: targets mid to high-frequency VIN ripple from rectifiers and DC/DC converters. It shifts a first corner frequency f_c,VIN down and lets PSRR work with smaller input ripple.
• NR capacitor or RC: targets low-frequency internal noise and low-frequency VIN ripple that PSRR does not fully reject. It shapes the 0.1 to 100 Hz spectrum seen at the bandgap node.
• OUT RC or C_OUT: targets load-induced ripple and transients. It lowers effective Z_out(f) in the bands where load current steps occur, often in the kilohertz and above region.

Thinking in terms of paths helps decide which lever matters most: VIN RC for noisy upstream supplies, NR C for low-frequency precision, and OUT RC for aggressive loads. In many real designs a combination of at least two is needed.

Strategies by application scenario

High-PSRR reference with light VIN ripple

With a clean linear supply and a reference that offers strong PSRR in the band of interest, VIN ripple often sits well below the error budget. In this case the main focus is low-frequency noise and drift:

• Follow the recommended C_NR value and consider using the “low-noise” option given in the datasheet if available.
• Maintain solid but not excessive VIN decoupling; a heavy VIN RC is usually not required.
• Keep C_OUT within the stability window; it can remain modest if load transients are weak.

Standard reference after a DC/DC stage

When a moderate PSRR reference runs from a DC/DC output, the DC/DC switching ripple and control loop peaking often dominate. The reference must work with a noisier VIN, and the combination of VIN RC and NR C becomes critical.

• Use a VIN RC network to knock down switching ripple in the tens of kilohertz to megahertz range before it reaches the reference input.
• Use C_NR to clean up low-frequency residual ripple in the 0.1 to 100 Hz band where PSRR may be weaker.
• Confirm that the DC/DC itself has good layout and output filtering; a badly designed power stage cannot be fixed by the reference alone.

Noisy loads such as switching resistor arrays

Some loads inject significant noise directly into the reference node: resistor ladders driven by fast logic, high-speed DACs or heavily multiplexed sensor arrays. Even with ideal VIN and strong PSRR, VREF can still be noisy.

• Route the reference as a separate Kelvin-connected trace to the sensitive load pins, away from high-current switching traces.
• Place local C_OUT or small RC networks close to the noisy load so that transient current loops are closed locally.
• Treat this as a load and layout problem rather than a VIN and PSRR problem; NR and VIN RC tweaks alone rarely fix it.

Mini-case: 12-bit ADC, 2.5 V reference and 50 mVpp VIN ripple

Consider a 12-bit ADC with a 2.5 V reference. One LSB is roughly 2.5 V / 4096 ≈ 0.6 mV. If the DC/DC feeding the reference has 50 mVpp ripple at its switching frequency, and the reference PSRR at that frequency is only 20 dB, then a few millivolts of ripple can leak into VREF, far above 1 LSB.

A practical strategy is to design VIN RC so that the RC corner sits below the main switching ripple band and adds another 20 to 30 dB of attenuation at that frequency. On top of that, C_NR is chosen to clean up lower frequency residual components, while C_OUT and layout keep load-induced disturbances down.

The exact component values depend on the DC/DC spectrum and reference data, but the method remains the same: start from an LSB-level ripple target at VREF, work backward through PSRR and VIN RC, and then validate the result on the bench.

Do not expect the reference to fix everything

Bypass networks can improve a solid design, but they cannot rescue a poor power stage or a bad layout. A quiet reference rail requires a reasonably clean VIN, well-designed DC/DC or LDO stages, properly decoupled loads and a layout that respects return paths. The reference and its RC networks are the last 10 to 20 percent of polish, not the first 80 percent.

Layout and Grounding for a Quiet Reference

Choosing NR, VIN and OUT RC values is only half of the work. Their effectiveness depends on how the PCB routes currents and return paths. This section turns the noise and ripple model into concrete layout rules so that bypass capacitors see the quiet ground and current loops you intended.

Quiet ground for NR and bypass capacitors

The ground node for NR and other bypass capacitors should be as quiet as possible. In practice this means isolating the reference return from high di/dt loops and digital switching currents.

• Place C_NR, C_OUT and feedback dividers in a small analog ground island near the reference device. Connect this island to the main ground at a short, well-controlled star point.
• Avoid routing large switching or motor currents through the same narrow ground neck or via cluster that connects the reference ground island to the main plane.
• Keep the NR capacitor ground pad close to the reference ground pin with a direct copper connection, not through long traces that wander into noisy regions.

VREF routing, Kelvin connections and RC placement

VREF routing decides which disturbances couple into the sensitive load. A good layout treats the reference output as a separate analog signal, not just another supply rail.

• Route VREF as a dedicated trace from the reference output pin to the ADC or DAC reference pin. Avoid tapping it from a busy power rail or a noisy digital node.
• Keep VREF away from high-current switching traces and nodes such as SW or LX pins, and avoid long parallel runs with clock or MOSFET gate signals.
• Place low-frequency bypass elements like C_NR close to the reference. Place decoupling and small RC networks that address load transients near the load pins, so that fast current loops close locally.

Multirail systems, ground partitioning and shared returns

Mixed-signal boards and multirail systems complicate the picture because multiple references and grounds share the same copper. The key is to prevent high di/dt currents from sharing narrow ground segments with the reference return.

• Whether you use explicit AGND and DGND regions or one continuous ground plane, make sure that the reference ground zone is tied to the quiet side of the system. It should not sit on the far end of a digital return path.
• Avoid routing digital return currents through the same neck, via stack or thin copper that connects the reference island back to the main ground. The shared inductance converts digital di/dt into voltage noise on NR and C_NR.
• When multiple references feed different ADCs or domains, avoid stacking them all on a single high-impedance ground spur. Each should have a short, low-impedance path back to the star point or ground plane.

Lab Validation and Debug Playbook

This section turns bypass and ripple-rejection theory into a bench playbook. The goal is to verify that NR capacitors and VIN/OUT RC networks deliver the expected noise and ripple improvements, and to give a structured way to debug results that do not match the datasheet or the design model.

What you want to measure

Before wiring any test setups, define a small set of concrete metrics. These let you compare the design, the datasheet and real hardware in a consistent way.

• Low-frequency noise: 0.1–10 Hz noise in RMS or p-p, matching the way the datasheet reports noise. Optionally extend to a wider band such as 10 Hz–10 kHz.
• Ripple rejection: how much of a known VIN ripple appears on VREF at a few key frequencies, effectively a spot-check of PSRR with your chosen VIN RC network.
• Stability behaviour: evidence of ringing, oscillation or “pendulum” behaviour on VREF when you change bypass values or apply load steps.

Every validation session should capture at least these three items. Without them it is hard to know whether a change in C_NR or VIN RC is really improving the design or just moving the noise somewhere else.

Instruments and measurement chain

Reference noise is usually in the microvolt range, so the measurement chain must add as little noise and drift as possible while still giving useful bandwidth.

• Low-noise amplifier (LNA or IA): amplifies tens of microvolts into a few millivolts so that an oscilloscope or data-acquisition card can resolve the signal. Its own noise floor should be well below the reference noise in the band of interest.
• FFT or noise analysis: a scope with FFT, a dedicated noise analyser, or a digitiser plus PC software can be used. Low-frequency noise requires long acquisition windows to capture 0.1–10 Hz content.
• Clean supply and shielding: where possible use a battery or low-noise linear supply. Place the reference board and amplifier in a simple shielded enclosure or metal box, and keep leads short and well twisted or shielded.

For low-frequency noise, take time to validate the measurement chain by shorting the input and recording its own 0.1–10 Hz noise. If this is on the same order as the reference noise, the setup will hide the effect of bypass changes.

Step-by-step noise validation

A simple three-step sequence makes it clear what each bypass network is doing. The idea is to measure a clean baseline, apply the datasheet-recommended network, then sweep values to confirm the trend.

1) Baseline with minimal bypass

• Populate only the minimum C_OUT and decoupling needed for stability. Leave NR and VIN RC networks unpopulated or at their smallest allowed values.
• Measure 0.1–10 Hz noise (RMS and/or p-p) at VREF, and record the broadband noise spectrum from 10 Hz up to tens of kilohertz.
• Save screenshots and numeric results as the “baseline” for your project documentation.

2) Datasheet-recommended bypass network

• Add the recommended C_NR or NR/OUT RC network and any recommended C_OUT values according to the datasheet low-noise example circuit.
• Repeat the same noise measurements, using identical acquisition time, bandwidth and averaging settings.
• Compare 0.1–10 Hz noise before and after. Several dB of improvement are typical when the NR network is used as recommended.

3) Sweep C values to confirm the trend

Instead of trusting a single value, change C_NR within the allowed range to see whether noise and start-up behaviour move in the expected direction.

• Increase C_NR by roughly 10× (within datasheet limits) and re-measure. Low-frequency noise should drop further but with diminishing returns, and start-up time should clearly increase.
• Decrease C_NR by roughly 10× from the recommended value. 0.1–10 Hz noise should move closer to the baseline, and any benefit from NR should shrink.
• If noise does not change with large C_NR adjustments, suspect the measurement setup or grounding before suspecting the reference itself.

Injecting VIN ripple to spot-check PSRR

A controlled VIN ripple test lets you verify whether the combination of VIN RC and PSRR matches your expectations. You do not need a full PSRR vs. frequency curve, just a few representative points.

• Power the reference from a clean DC source at the nominal VIN (for example 5 V).
• Use a function generator and a series resistor to inject a small sinusoidal ripple (for example 50 mVpp) into VIN. Choose a resistor value that lets you control the ripple without disturbing the DC level.
• At each test frequency (for example 100 Hz, 1 kHz, 10 kHz, 100 kHz), measure the ripple amplitude on VIN and the resulting ripple on VREF using the same probe and ground style.
• Estimate PSRR at that frequency as 20·log10(VIN_ripple / VREF_ripple) and compare to datasheet typical curves. The goal is not a perfect match, but a similar order of magnitude and shape.

Debug table: symptoms, expected trends and root causes

When measurements do not behave as expected, use a structured checklist instead of random component changes. The table below maps a few common test conditions to the trend you should see and likely root causes when reality disagrees.

Capturing results as a reusable asset

Once the bypass and RC networks are validated, treat the results as part of the design assets, not just lab notes. Save plots and numeric data alongside the schematic and layout files.

• Record final 0.1–10 Hz noise numbers for the chosen configuration, as well as before/after spectra.
• Document the VIN ripple injection test conditions and measured PSRR points for your chosen VIN RC network.
• Store scope captures of load step responses and any stability margins you verified.

These measurements justify your C_NR, C_OUT, VIN RC and OUT RC values and feed directly into the noise-critical BOM subset used in the next section.

BOM and Procurement Notes for Bypass Networks

The reference IC and its bypass and RC networks form a noise-critical subsystem. This section explains which BOM fields must be specified and gives concrete part examples so that small-batch procurement and design engineers do not treat C_NR, C_OUT and RC components as “any 0.1 µF and 10 kΩ.”

Required fields for the reference IC

For the reference device itself, the BOM should carry enough information for procurement, layout and validation teams to understand why this IC was chosen and how it must be used.

• Electrical: V_REF (nominal output), I_Q (quiescent current), 0.1–10 Hz noise and broadband noise density, PSRR at one or two key frequencies (for example 100 Hz and 100 kHz).
• Stability constraints: allowed C_load range and ESR range, whether a series R_iso is required or recommended, and any specific start-up conditions called out in the datasheet.
• Grade and package: temperature range, AEC-Q100 qualification if needed, package type and maximum height, including whether the package is suitable for the board assembly process.

Required fields for C_bypass, C_NR and C_OUT

Bypass capacitors are not interchangeable commodities. The BOM must distinguish between dielectric types, voltage ratings and tolerances that affect low-frequency noise, drift and stability.

• Capacitance and tolerance: nominal value (for example 10 nF, 100 nF, 1 µF) with tolerance (for example ±5 % or ±10 %). For C_NR, include the recommended value and acceptable range so that substitutions stay within validated limits.
• Dielectric and temperature characteristic: explicitly specify C0G/NP0, X7R or other dielectric. For noise-critical C_NR and precision C_OUT, C0G/NP0 or high-quality X7R should be required, with “no Y5V / generic X5R” noted in the BOM.
• Voltage rating and derating: list the rated voltage and target derating (for example “50 V rated, used at ≤10 V”). This avoids operating MLCCs near their rated voltage where effective capacitance collapses.
• Package size and ESR: specify the package (0603, 0805, etc.) and, where the reference requires it, call out “low-ESR MLCC” or the ESR band to stay within.

Required fields for VIN and OUT RC networks

RC networks on VIN and OUT are part of the noise and stability budget. Their values and technologies should be treated as design choices, not placeholders.

• Resistor value and tolerance: list nominal R, tolerance and, for precision paths, TCR (for example 47 Ω, 1 %, 25 ppm/°C).
• Resistor technology and power rating: thin-film resistors have lower excess noise and better drift than generic thick-film. Power rating and voltage rating ensure that self-heating does not change resistance or noise during operation.
• Capacitor details: for VIN and OUT capacitors, repeat the dielectric, voltage, tolerance and package constraints used for C_NR and C_OUT. If a capacitor targets a specific switching band, note that in the BOM so that substitutes preserve the same role.

Layout constraints to reflect in the BOM

Some placement constraints are easier to enforce if they appear directly in the BOM notes, not only in layout guidelines. This is especially important when different teams or vendors handle layout.

• Reference cluster: mark the reference IC, C_NR, C_OUT and feedback resistors as a “reference cluster” with a note such as “Place near REF IC, same side, shortest possible loop, tie to analog ground island.”
• VIN RC: note that R_VIN and C_VIN should be placed close to the reference VIN pin rather than on the DC/DC side, so that the RC time constant is defined by components, not long traces.
• Load-side decoupling: for RC and C_OUT intended to tame load transients, add a note such as “Place near ADC/DAC reference pin; close transient current loop locally.”
• Quiet nets and net classes: identify VREF, NR, C_NR ground and related nodes as “Quiet Net” or a dedicated net class. This tells layout to avoid routing digital or high-current return paths through these nodes.

Risks and second-source strategy

Noise-critical components are often at higher risk of availability issues or accidental substitution. The BOM should document these risks and define acceptable alternatives.

• C0G availability and MLCC EOL: certain small-package, high-voltage C0G parts can be harder to source. For these, define at least two qualified manufacturers and specify “C0G only, no X7R substitutes” to prevent last-minute dielectric changes.
• Same package, different dielectric: 0603 10 nF 50 V parts may exist in both C0G and X7R variants. Explicitly marking the dielectric in the BOM avoids silent substitutions that change low-frequency behaviour and drift.
• Resistor noise and drift: for key RC resistors, specify thin-film series with low 1/f noise and tight TCR. Treat them as “engineering-approved substitutions only,” not generic pull-up resistors.

Example noise-critical BOM sets

The following examples illustrate how to capture reference, bypass and RC components as a coherent noise-critical BOM subset. Part numbers are representative and can be replaced by equivalent devices with matching specifications.

Tying noise-critical BOM to your procurement flow

In practice, the reference IC and its bypass and RC network should be treated as a small sub-BOM inside the full design. Mark these entries as noise-critical in your ERP or BOM tool so that any substitution request triggers engineering review.

When you share a design or request a quote, include this subset explicitly. On your site you can link it to a dedicated inquiry endpoint, for example: /submit-bom, with a note that “reference IC + bypass network” must be preserved or reviewed carefully during second-source selection.

FAQs on Bypass, Ripple Rejection and Noise-Critical BOM

These questions collect the most common design, debug, measurement and BOM issues around NR capacitors and RC networks on voltage references. Each answer is written so it can be reused directly for People Also Ask snippets, social posts and FAQ structured data without further editing.