What this page solves

Phase and bus current sensing sit at the center of every serious servo, stepper and inverter drive. From 48 V compact axes to 230 VAC machines and 600 V industrial drives, the controller must always see both DC bus current and phase currents clearly enough to run closed-loop torque control, protect the power stage and report power or energy.

The hard part is not only picking a shunt value. Design teams need to decide where the shunt sits in the power path, whether the measurement can remain non-isolated or must cross a high-voltage barrier, and when it makes sense to move from simple shunt amplifiers to isolated amplifiers or ΣΔ modulators. On top of that, each decision changes the error budget, latency and thermal stress on the sensing path.

This page focuses on shunt-based phase and DC bus current sensing inside motor drives. It covers shunt placement options, non-isolated versus isolated amplifier and ΣΔ paths, and a practical way to build an error and thermal budget. Typical use cases include drives in the few-amp to few-hundred-amp range, with common DC bus voltages of 48 V, 320–400 V and 600–700 V across servo, stepper, BLDC/PMSM and ACIM V/f–FOC inverters.

Where bus and phase current live in the drive

In a typical motor drive, AC power flows through EMI filtering and rectification or PFC into a DC link, then into a three-phase inverter bridge that feeds the motor. DC bus current and phase currents are present at different points along this path. Bus current represents total power through the DC link, while phase currents represent what each motor phase actually receives and what the FOC or torque controller needs to regulate.

DC bus current is usually sensed with one shunt in the DC return or, in higher-voltage designs, in the positive rail using a high-side or isolated sensing path. It is a natural place to implement fast over-current or short-circuit protection and to estimate total drive power. Phase current sensing is implemented with low-side shunts under each phase leg, with two or three low-side shunts sharing return, or with inline shunts placed in the motor leads. The chosen topology determines how easy it is to reconstruct all three phase currents and how much constraint it puts on PWM timing.

A single DC bus shunt can be enough for simple V/f drives and basic power limiting. As soon as tighter FOC performance is required, most designs move to at least a two-shunt or three-shunt phase topology, or inline shunts when higher accuracy and fewer sampling blind spots are needed. The detailed control and reconstruction rules belong on the Control & Algorithms page; this section focuses on where the currents physically flow and which shunt positions matter for sensing IC selection.

Measurement jobs and constraints

Phase and bus current sensing in motor drives usually serves three distinct jobs: fast current control for FOC or torque loops, hard over-current and short-circuit protection, and slower metering or predictive maintenance logging. Each job drives different requirements for sampling frequency, bandwidth, accuracy, latency and long-term stability, and these requirements strongly influence shunt placement and IC selection.

FOC current loop

For FOC and other torque-control schemes, phase current measurements are typically sampled in sync with the PWM carrier at approximately 10–100 kHz. Loop bandwidth often reaches a few kilohertz, so the sensing path must provide consistent gain and phase across this range. A practical target is a total measurement error of about 1–3 % of full-scale, with end-to-end latency from physical current change to usable digital data kept within roughly one to two PWM periods.

Over-current and short-circuit protection

Protection channels are optimised for reaction time and determinism rather than fine accuracy. In many drives, over-current and short-circuit protection is expected to respond within hundreds of nanoseconds to a few microseconds. The circuit often uses hardware comparators connected directly across the shunt, or across a short-gain amplifier output, with independent thresholds and trip paths into the gate driver or protection logic. The phase or bus shunt therefore frequently serves both the ADC-based measurement channel and a separate fast comparator path.

Metering, logging and predictive maintenance

Metering and predictive maintenance care less about tens-of-kilohertz bandwidth and more about repeatability, drift and resolution at lower frequencies. Typical bandwidth is only up to a few tens of hertz, with heavy averaging or decimation. The sensing path is judged on long-term offset and gain stability across temperature, so that energy, efficiency and load profiles remain trustworthy over months or years rather than a single control cycle.

Key constraints for shunt and front-end design

Shunt power and self-heating (I²R): the chosen resistance sets both full-scale voltage and dissipation. At tens of amperes, even milliohm-range resistors can dissipate several watts, which forces attention to package rating, copper area, thermal coupling and the resulting change in resistance with temperature.

Common-mode voltage range: low-side shunts see a small common-mode voltage near the system reference, while high-side and inline shunts ride on the DC bus or motor phase nodes and can see hundreds of volts plus fast dv/dt. The amplifier or ΣΔ modulator must tolerate the intended common-mode range with adequate margin.

CMRR, CMTI, bandwidth and noise: high-side and inline solutions demand high common-mode rejection and high CMTI to survive steep switching edges without false readings. Bandwidth must cover the control and protection needs, while noise must remain low enough that small-signal current variations and thresholds are still distinguishable.

Temperature and module limits: the shunt and front-end sit inside a power module or drive enclosure where ambient and hotspot temperatures are often elevated. Self-heating of the shunt, ambient rise in the module and temperature coefficients of amplifiers, references and ADCs all feed into the total error budget. Detailed thermal planning belongs on the Thermal Sensing & Control page, but shunt and AFE choices must be consistent with those thermal limits.

Bus current sensing topologies

DC bus current sensing can be implemented with a low-side shunt and non-isolated amplifier, with a high-side shunt and a high-voltage differential amplifier, or with a high-side shunt feeding a ΣΔ modulator and isolated digital path. Each topology has a preferred DC bus voltage range, protection strategy and cost level, and each interacts differently with common-mode voltage, dv/dt and PCB layout.

Low-side DC link shunt with non-isolated current-sense amplifier

In the low-side topology, a shunt is placed in the DC return path, and a non-isolated current-sense amplifier measures the voltage across it relative to the system reference. Common-mode voltage is low, so the amplifier can use modest CMRR and operate from the same ground as the controller. A comparator or integrated fault output often uses the same shunt for over-current detection, while the amplifier feeds an ADC channel for control and monitoring. The main advantages are low cost, simple routing and a straightforward reference point for the analog front-end.

The limitations appear in fault coverage and ground integrity. Low-side sensing cannot see every possible fault mode, and ground bounce or shared return paths can introduce error if Kelvin connections and layout are not carefully handled. This topology suits low to medium DC bus voltages, such as 48 V and many 320 V class drives, where insulation structure and power levels still allow a grounded low-side reference.

High-side DC link shunt with high-voltage differential amplifier

In the high-side topology, the shunt sits in the positive DC bus path, between the rectifier or PFC stage and the DC link, or between the DC link and the inverter bridge. The amplifier measures a small differential voltage on top of a high common-mode voltage that may reach 320–400 V or 600–700 V. High-voltage current-sense amplifiers or dedicated high-side ICs provide the required common-mode range and CMRR, level-shifting the result down to the low-voltage domain for the ADC.

This arrangement measures true bus current independently of return routing and can improve visibility for power limiting, efficiency tracking and certain fault modes that bypass the low-side shunt. The trade-offs are higher device cost, stricter layout and bypass requirements and careful review of bandwidth and propagation delay to ensure suitability for both control and protection tasks. It is a common choice in higher-voltage servo and inverter drives where the bus is already several hundred volts.

High-side DC link shunt with ΣΔ modulator and isolated digital path

A more advanced high-side approach places a ΣΔ current-sense modulator directly across the shunt, often with the modulator sitting on the high-voltage side. The modulator outputs a high-speed bitstream that crosses an isolation barrier through a digital isolator and is then filtered and decimated in a controller or companion IC. This architecture combines strong common-mode rejection with robust CMTI, because the sensitive converter sits close to the shunt and only digital signals cross the noisy isolation region.

ΣΔ-based bus sensing is well suited to 400–700 V class industrial inverters and higher-power servo systems where high accuracy, high dynamic range and tough EMI conditions coexist. The additional complexity comes from the digital filter and its group delay, which must be compatible with the desired current-loop bandwidth. Over-current and short-circuit protection often still rely on a parallel fast comparator path rather than on the filtered ΣΔ data. This topology is typically reserved for higher-performance or higher-voltage drive families where the extra performance and isolation robustness justify the added cost and design effort.

Phase current sensing topologies

Around a three-phase inverter bridge, phase current can be measured with low-side shunts, with shunts in the high-side legs or with inline shunts inserted in the motor leads. Each topology interacts differently with sensorless FOC capability, phase current reconstruction and the available sampling windows inside the PWM cycle, and each drives its own combination of non-isolated, isolated or ΣΔ-based front-end ICs.

Low-side 2-shunt and 3-shunt topologies

In low-side phase sensing, two or three shunts sit between the inverter low-side switches and the DC return. Common-mode voltage stays close to the system reference, so non-isolated current-sense amplifiers or direct ADC connections can be used. A 3-shunt arrangement provides a separate measurement path for each phase, which simplifies FOC and sensorless FOC because phase currents are directly available whenever clean sampling windows exist in the PWM cycle. A 2-shunt arrangement saves one shunt and amplifier path but requires reconstruction of the third phase using current-sum relationships and more careful sector-based sampling.

With low-side shunts, the main planning tasks are ADC channel count and sampling instants. Many drives use two or three simultaneous-sampling ADC channels tied to PWM timing events, placing acquisition windows in the middle of conduction intervals to avoid dead time and commutation noise. Detailed reconstruction mathematics and PWM sector planning are reserved for the Control & Algorithms page; this section focuses on the hardware positions and front-end choices that support those strategies.

High-side phase shunts

High-side phase sensing places shunts in the upper legs of the inverter, between the DC bus and each phase node. These shunts ride on a high common-mode voltage that follows the DC bus, so high-side differential amplifiers, isolated amplifiers or ΣΔ modulators are typically required. Some power modules expose dedicated sense pins connected to internal high-side shunts, making this topology attractive when tight integration with a specific module is needed.

From a control perspective, high-side phase measurements can support the same FOC and sensorless FOC schemes as low-side shunts, provided the front-end maintains bandwidth and CMRR under high dv/dt. Sampling windows must be aligned with switching states that keep the front-end within its input limits and avoid saturation or large dynamic errors. ADC planning often involves three channels receiving level-shifted analog outputs from the high-side front-ends or several ΣΔ bitstreams feeding digital filters.

Inline shunts in the motor leads

Inline shunt topologies insert a shunt in each motor lead between the inverter and the motor terminals. These shunts see the full PWM waveform on their terminals and experience the highest dv/dt and common-mode stress, which drives the use of isolated amplifiers or ΣΔ modulators with very high CMTI and robust input stages. Many high-performance servo and traction inverters use inline sensing when the power module already integrates such shunts or when phase current fidelity is a top priority.

Inline shunts tend to minimise sampling blind spots because each shunt directly carries the corresponding motor phase current across all PWM sectors. This improves observability for sensorless FOC, harmonic analysis and acoustic or vibration optimisation. The trade-off is higher component stress, more complex isolation and layout, and tighter requirements on channel-to-channel matching and timing, especially in multi-axis and high-power drives. As with other topologies, exact reconstruction and timing rules for each PWM pattern belong to the Control & Algorithms page; this section defines the hardware options and their implications.

IC building blocks: shunt amps, isolated amps, ΣΔ modulators and references

Shunt-based phase and bus current sensing relies on a small set of key IC building blocks: non-isolated shunt amplifiers, isolated amplifiers, ΣΔ modulators and the precision references and input networks that support them. Choosing and combining these devices correctly allows the same sensing concept to scale from low-voltage servo axes to high-voltage industrial inverters and multi-axis motion controllers.

Shunt amplifiers

Shunt amplifiers convert the millivolt-level voltage across a shunt into a voltage that matches the ADC range. Important parameters include gain and gain options, bandwidth, input common-mode range, offset and offset drift, gain error and gain drift, output swing and drive capability. Low-side devices operate near the system reference and are widely used with low-side phase and bus shunts in low- and medium-voltage drives. High-side-capable shunt amplifiers extend the common-mode range to tens or hundreds of volts and support DC bus or phase sensing above ground.

For FOC-oriented designs, bandwidth must comfortably exceed the targeted current-loop bandwidth while keeping noise manageable. Offset and drift set the minimum measurable current and the stability of zero-current readings, while gain accuracy combines with shunt tolerance to define full-scale error. The amplifier output stage must also be able to drive any RC filtering and the ADC input without excessive settling time.

Isolated amplifiers

Isolated amplifiers transfer an analog representation of shunt voltage across a galvanic isolation barrier. Key specifications are isolation rating, CMTI, bandwidth, linearity, gain error, offset, drift and propagation delay. High CMTI is essential when shunts see the switching edges of high-voltage IGBTs or SiC MOSFETs. Bandwidth and delay must support both the control-loop requirements and any use of the channel in fast protection paths.

Isolated amplifiers are common in high-voltage servo and industrial inverters where the power stage floats at hundreds of volts and the controller remains at SELV levels. They fit naturally with high-side or inline phase shunts and with DC bus shunts in 400–700 V systems when a purely analog path into a standard ADC is preferred over ΣΔ-based approaches.

ΣΔ modulators

ΣΔ current-sense modulators convert shunt voltage into a high-speed digital bitstream that is transmitted across isolation and later filtered and decimated. Key parameters are modulator clock and bitstream rate, effective number of bits achievable for a given oversampling ratio, noise density, group delay of the combined modulator and digital filter, and CMTI. Because only digital signals cross the isolation barrier, ΣΔ paths often offer strong immunity to common-mode noise in high dv/dt environments.

ΣΔ-based solutions are widely used in high-voltage industrial drives and high-performance servo systems where needs include precise energy metering, high dynamic range and robust isolation. Control-loop design must take the fixed group delay of the digital filter into account, and very fast over-current or short-circuit protection is usually implemented with a separate comparator path rather than relying solely on filtered ΣΔ data.

Precision references and input or anti-alias networks

Precision references define the voltage scale for ADCs and ΣΔ demodulators that convert shunt amplifier or modulator outputs into codes. Reference voltage value, initial accuracy, temperature coefficient and long-term drift all feed directly into the current measurement error budget. In multi-axis control boards, sharing a single high-grade reference across multiple channels can significantly improve channel-to-channel gain matching.

Input and anti-alias networks around the shunt and front-end ICs complete the sensing chain. Small RC filters at the amplifier or modulator inputs are used to tame high-frequency switching noise and protect the IC, while still preserving the bandwidth needed for current control and protection. Series resistors, transient clamps and EMI structures must be dimensioned so they do not undermine accuracy or delay response. For a broader comparison between shunt-based and magnetic current sensors, the dedicated Current Sensing cluster can be consulted; this page stays focused on shunt and amplifier, isolated amplifier and ΣΔ building blocks.

Design checklist and error budget

A structured checklist and error budget make the phase and bus current sensing chain traceable from shunt selection through amplifier or ΣΔ front-end to protection settings. The items below can be copied directly into design documentation or a spreadsheet so that each step is explicitly reviewed and signed off.

Shunt resistor selection

▢ Full-scale shunt voltage drop defined, typically in the 50–100 mV range at rated current, balancing signal-to-noise ratio against power dissipation and self-heating.

▢ Power dissipation at rated and fault currents checked against shunt package limits and copper area capability, using I²R at both continuous and short-duration overload conditions.

▢ Resistance tolerance selected according to accuracy target, for example 1 % for basic drives, 0.5 % or 0.1 % where metering and predictive maintenance require tighter energy data.

▢ Temperature coefficient chosen (for example ±50 or ±25 ppm/°C) based on expected temperature rise of the shunt and the allowed gain drift over the operating range.

▢ Package size and footprint reviewed for thermal performance and for compatibility with Kelvin sense routing, avoiding shared high-current copper in the sense path.

Amplifier and ΣΔ front-end design

▢ Gain configured so that the shunt full-scale voltage maps close to the ADC or ΣΔ demodulator full-scale, with headroom for tolerance, drift and occasional overload.

▢ Front-end bandwidth selected to support current-loop bandwidth and protection requirements, while input and output filtering are tuned to avoid unnecessary noise amplification or excessive delay.

▢ Input common-mode range and CMRR verified against the planned shunt location (low-side, high-side or inline) and against worst-case voltage excursions in normal and fault operation.

▢ Required CMTI for high-side or inline solutions estimated from inverter dv/dt and compared to the amplifier or ΣΔ modulator datasheet, including suitable design margin.

▢ Channel-to-channel gain, offset and delay matching assessed for multi-phase and multi-axis systems, with critical limits documented for FOC performance and phase current reconstruction.

▢ For ΣΔ solutions, combined modulator and digital filter group delay checked against the target current loop bandwidth and protection timing so that control stability margins remain acceptable.

Error budget framework

The error budget summarises how shunt tolerance and temperature drift, amplifier errors, ADC imperfections and reference drift combine into total %FS error. A simple framework can be used in a spreadsheet, with one row per error source and all contributions converted into equivalent full-scale percentage at a defined operating point.

Total current measurement error can be estimated using a simple worst-case sum of all %FS contributions or a root-sum-square combination for a more realistic typical figure. The choice of method should match project safety, metering and control requirements.

Safety and protection linkage

▢ A fast comparator path is defined alongside the ADC or ΣΔ measurement path, with a clear connection to gate drivers or dedicated protection logic for over-current and short-circuit events.

▢ Comparator thresholds are set relative to rated phase current, for example 1.2–1.5 times the nominal level, to prevent nuisance trips while still limiting fault energy.

▢ ADC full-scale range and comparator thresholds are cross-checked so that fault conditions do not saturate the measurement chain before hardware protection responds, and so that diagnostic recording during fault events remains usable where required.

▢ Fault outputs from current-sense channels are integrated with the wider OC/OV/UV protection and safety monitor functions described in related pages, keeping the current-sense role focused on shunt-based detection.

Layout and EMC notes for current shunts and AFEs

PCB layout around shunt resistors and analog front-ends is often the difference between a stable current measurement and a noisy or drifting channel. The points below focus on the shunt itself, Kelvin connections, distance to high dv/dt nodes and the local relationship between power ground and sense ground, without attempting to replace full-board EMC guidelines.

Kelvin connections around the shunt

Power current and measurement current should follow clearly separated paths. High current flows through wide copper from the DC link to the shunt and on to the inverter or motor leads, while the measurement path uses a dedicated pair of sense traces that start directly at the shunt terminals and run to the amplifier or ΣΔ modulator inputs as a tight pair.

Sense pads are best placed directly on the shunt metal terminations or on dedicated sense terminals for four-terminal shunts, avoiding vias and copper stubs that also carry the main power current. Any extra series resistance or shared copper in this path converts voltage drops from the power loop into additional error that is indistinguishable from real current.

A practical checklist includes: separate power and sense pads on the footprint, a closely coupled sense trace pair from shunt to AFE, and no high-current vias or large copper branches inserted between shunt terminals and sense nodes.

High dv/dt nodes and AFE placement

The inverter phase nodes, half-bridge outputs and high-side gate drive traces carry high dv/dt and can inject significant noise through capacitive and inductive coupling. Shunt AFEs and sense traces should therefore be placed away from these switching nodes, with short, direct routing from the shunt to the AFE and minimal parallel overlap with power switch or gate-drive conductors.

For low-side sensing, placing the AFE close to the shunt and using a solid reference plane under the sense traces reduces loop area and susceptibility. For high-side or inline sensing with isolated amplifiers or ΣΔ modulators, the high-voltage side of the IC can be placed close to the shunt while the low-voltage side remains on the controller domain, with the isolation barrier arranged to cross mainly digital or well-controlled signals.

High CMTI devices rely on layout discipline to deliver their full performance. Short return paths, careful placement relative to phase nodes and avoidance of unnecessary coupling capacitance between power and sense circuits remain essential even when datasheets quote impressive CMTI numbers.

Power ground versus sense ground

Locally, the current-sense circuit benefits from a clear relationship between power ground and sense ground. A star point near the shunt or DC link return is commonly used, where the high-current return path and the sense ground reference meet. The AFE and ADC reference connections then tie to the sense side of this point so that ground bounce from the power loop does not directly corrupt the measurement reference.

On control boards that distinguish analog ground from digital ground, the shunt AFE and associated ADC channels usually belong to the analog ground region, with sensitive nodes kept away from large digital return currents. The analog and digital grounds then join at a defined point, typically near the ADC or at the power entry to the controller. This local discipline complements the wider EMC and grounding strategy described on the EMC Subsystem page.

The aim is to separate the high-current power loop, the small-signal sense loop and the noisy digital ground region while still providing a clear reference path for the measurements.

IC vendor and family mapping

The aim of this section is to map typical phase and bus current-sense roles to vendor families rather than individual part numbers. The focus stays at the “family” level, so that shortlists can be built quickly for shunt amplifiers, isolated amplifiers, ΣΔ current-shunt modulators and precision reference or PGA solutions across common motor-drive voltage and power ranges.

Low-voltage servo and stepper axes (48–60 V, 0–50 A)

In 24–60 V servo and stepper drives, phase and bus current sensing is usually implemented with low-side 2- or 3-shunt topologies and non-isolated shunt amplifiers. Vendor families in this area typically offer compact packages, low power consumption and gain options tuned for 50–100 mV shunt drops.

• Families such as Vendor A low-voltage shunt amplifier lines target low-side sensing in 24–60 V drives, with bidirectional inputs and common-mode ranges close to ground.
• Vendor B current-sense amplifier families concentrate on 50–100 mV shunt drops and direct interfacing to microcontroller ADCs, often with integrated filtering and reference options.
• Vendor C multi-channel shunt amplifier families serve compact multi-axis cards, where several servo or stepper phases share the same reference and layout.

When accuracy and cost must both be controlled, these families are usually the first candidates before moving to isolated or ΣΔ-based solutions.

Mid-voltage servo and industrial drives (up to 400 V)

In mid-voltage servo axes and compact industrial drives, designs frequently mix low-side shunt measurement with high-side or inline sensing depending on the power module and insulation strategy. Vendor families for this region cover both extended common-mode shunt amplifiers and isolated analog or ΣΔ front-ends.

• Vendor D shunt amplifier families support high-side or low-side sensing up to around 80–100 V common-mode and can be used on DC links and phases in compact drives.
• Vendor E isolated amplifier families are aligned with 230–400 V class inverters and match common power modules, providing reinforced isolation and high CMTI for phase and bus shunts.
• Vendor F ΣΔ current-shunt modulator families provide isolated bitstreams from shunts in mid-voltage drives, ready for digital filtering inside the controller or dedicated demodulators.

For these drives, a practical selection flow is to first choose between analog isolated amplifiers and ΣΔ modulators based on latency and resolution needs, then shortlist two or three families from different vendors that meet CMTI and isolation requirements.

High-voltage drives and multi-axis controllers (400–700 V, tens to hundreds of amperes)

High-voltage industrial inverters and multi-axis motion controllers often rely on inline or high-side shunts attached directly to power modules or bus bars. Vendor families here focus on reinforced isolation, high CMTI, low drift and well-defined group delay for control-loop design.

• Vendor A and Vendor B isolated amplifier families for 100–600 V DC bus rails supply analog outputs for high-side or inline shunts in large industrial drives.
• Vendor C and Vendor D ΣΔ current-shunt modulator series address 400–800 V inverters with isolated bitstreams suitable for combined control and energy metering.
• Vendor E multi-channel isolated front-end families combine several ΣΔ or analog channels for multi-axis servo controllers and cabinet-level phase and bus sensing.

These families are typically shortlisted when the design must withstand high dv/dt at hundreds of volts, with controlled delay and accuracy for both torque control and long-term energy tracking.

Precision references and PGA-based front-ends

Precision voltage reference and PGA families underpin the gain and stability of ADC-based current measurement across all of the scenarios above. They become especially important once multiple axes or phases share the same ADC and reference.

• Vendor F precision reference families are frequently paired with multi-channel ADCs so that all phase and bus current channels share a single low-drift reference voltage.
• Vendor G low-noise reference and buffer series provide high PSRR and low temperature drift for ADC full-scale settings in servo and motion controllers.
• Several vendors offer integrated PGA plus ADC front-end families where programmable gain and reference options are tuned for 0–50 A servo axes and small multi-axis boards.

When channel-to-channel matching is important, families that support shared references and clearly specified offset, gain drift and channel matching limits are usually preferred over ad hoc combinations.

Practical selection sequence

A practical way to use vendor families during shortlisting is:

1. Fix the sensing topology and common-mode range: low-side 3-shunt, high-side bus, or inline shunts at the motor leads. This immediately narrows shunt amplifier, isolated amplifier and ΣΔ family choices.
2. Choose a current and bandwidth class (for example 0–50 A servo axis, or 100 A industrial inverter) and focus on families positioned for that range in vendor documentation.
3. Decide how much emphasis to put on resolution and metering versus latency and cost, then choose between analog isolated amplifiers and ΣΔ current-shunt modulators accordingly.
4. Within the chosen role, shortlist at least two or three vendor families that meet isolation, CMTI, error budget and layout requirements so that purchasing and second-source planning remain flexible.

Magnetic current sensor families and their own vendor mapping are handled in the wider Current Sensing and Power or Energy Measurement cluster. This section stays focused on shunt-based paths and their amplifier, isolated amplifier, ΣΔ and reference building blocks.

Recommended topics you might also need

• FOC Controller / Motion MCU
• Servo Power Stage
• BLDC / PMSM Driver
• OC/OV/UV Protection

FAQs: Phase and bus current sensing

These twelve questions are the way I sanity-check phase and bus current sensing choices before freezing a drive design. Each answer is written from my point of view so I can reuse the logic in design reviews, sourcing discussions and safety documentation without reading the entire page again.