What this page solves

Protection relays sit between high-voltage equipment and breakers, and the hardest work is deciding how to detect faults and when to trip. Overcurrent, earth-fault, differential and distance elements all compete for priority, and each one depends on HV isolated sensing, ADC performance and FPGA or SoC logic.

This page helps map that decision flow so protection settings do not come from guesswork. The content focuses on how CT and VT signals are conditioned and isolated, how sampling and phase alignment affect detection, and how thresholds and time delays turn raw disturbance into a selective trip, an alarm or a logged event only.

The goal is to give a repeatable way to choose which protection elements are needed for a given feeder or transformer, how sensitive each element should be, and which combinations of magnitude and time are safe for both the network and the equipment. Upstream and downstream selectivity is kept in view, but the focus stays on the relay as the point where sensed current and voltage become a protection decision.

Position in protection architecture

A protection relay is the decision point between measurement and interruption. On the primary side are the feeders, transformers and busbars together with CTs and VTs. On the secondary side are isolated AFE stages, ADCs and a processing core that evaluates OC, EF, differential and distance elements before driving breaker trip coils through digital isolation.

Above the relay, substation IEDs and gateways collect status, events and measurements and forward them to SCADA and control centers. Lateral functions such as GNSS or PTP time sync, cybersecurity modules and auxiliary power or UPS systems support the relay but do not replace its decision role. The relay must operate correctly even if higher-level communication is temporarily unavailable.

In the wider smart grid system, the relay coordinates with recloser controllers, feeder automation units and downstream LV protection so each element handles faults in its own zone. This page keeps the focus on the relay core: how measured signals and time-synchronised data are turned into selective protection actions, while communication, reclose logic and asset monitoring remain on their respective pages.

Fault types & detection requirements

Protection elements only make sense when each one is tied to a clear fault type and a measurable signal. Overcurrent, earth-fault, differential and distance protection all look at the same CT and VT data, but each element expects its own bandwidth, resolution, phase accuracy and time window before declaring a fault.

For high-current phase faults, the main challenge is CT saturation and waveform distortion during the first few cycles. For earth faults, the limiting factor is often the ability to resolve small zero-sequence currents and voltages in noisy conditions. Differential and distance elements add strict requirements on phase alignment and multi-end consistency, especially when long lines and high source impedance are involved.

This section frames each fault type as a set of detection requirements: how much dynamic range the current channels must cover, how small an earth-fault current still needs to be seen, how tightly phase angles must match, and how quickly each element should respond. The next sections then use these requirements to shape the HV isolated signal chain and the FPGA or SoC processing logic.

HV isolated sensing & signal chain options

Every protection decision starts with current and voltage that are safe to digitise. High side CTs, zero-sequence CTs, VTs and shunt-based measurement chains all bring magnitudes, bandwidth limits and insulation constraints, and the choice of isolation amplifier, sigma-delta modulator or direct ADC input fixes how much detail the relay can see during a fault.

For current measurement, traditional CTs and core-balance CTs offer rugged isolation and fault-level headroom but need careful burden sizing and saturation handling. Shunt plus isolated amplifier or sigma-delta modulator chains suit medium-voltage and electronic relays where dynamic range and common-mode immunity are critical. Voltage paths use VTs or resistor and capacitor dividers with isolated front-ends, trading phase accuracy against cost and footprint.

This section treats the isolated signal chain as a single block: sensor, isolation, ADC and synchronisation. The aim is to show which combinations support high-current faults, sensitive earth-faults, differential stability and distance measurement, and how resolution, latency and channel-to-channel alignment feed into the FPGA or SoC logic that implements the protection elements.

FPGA/SoC protection logic & event flow

High-voltage sensing and ADCs only create value when converted into protection actions. Inside a modern relay, FPGA or SoC logic receives synchronised current and voltage samples, performs pre-processing and feeds multiple protection elements in parallel. Each element evaluates its own criteria, but all requests must be prioritised and turned into a single, time-stamped decision that drives trip coils, alarms and event logs.

The logic chain typically starts with filtering and RMS or phasor calculation, followed by dedicated engines for overcurrent, earth-fault, differential and distance protection. Overcurrent logic compares magnitude and time against inverse or definite-time curves. Earth-fault logic focuses on zero-sequence components and system earthing. Differential and distance logic rely on precise phase relationships between multiple currents and voltages to identify internal faults and locate them in the correct zone.

A decision layer then arbitrates between elements, enforces blocking and interlocks, and produces coordinated trip, alarm or log-only outcomes. Every step is time-tagged so fault records show which element operated, which phase or zone was involved and how long the protection path took to react. Supervisory firmware may handle configuration and reporting, but the core protection logic continues to run as a deterministic pipeline inside FPGA or hardened SoC blocks.

Threshold setting & coordination (selectivity)

Protection elements only deliver selective behaviour when thresholds and time delays are set in line with system short-circuit levels, CT and VT ratings, equipment withstand limits and upstream and downstream devices. Pickup levels that are too low cause nuisance trips, while values that are too high leave parts of the network unprotected during real faults. Coordination must be considered both along the feeder and between different protection elements within a single relay.

Overcurrent settings typically refer to rated current and short-circuit calculations, using definite-time or inverse-time curves so downstream feeders operate first and upstream devices act as backup. Earth-fault thresholds depend strongly on earthing method and the smallest fault current that must be detected without reacting to normal unbalance or leakage. Differential thresholds, slopes and harmonic restraint parameters are tuned to balance sensitivity with stability, while distance zones are shaped around line impedance and delayed to coordinate with lower-level relays.

Selectivity is therefore a two-dimensional problem: time–current coordination between stages in the network and zone or directional coordination between different functions. Proper setting leaves deliberate margins between curves and zones so that a fault is cleared by the closest device without unnecessary backup operation. The same settings also feed directly into event analysis, because each trip record carries the element, curve, zone and delay that led to the final decision.

Safety & diagnostics (self-test, watchdog, SIL)

Protection performance is only credible when the relay can prove that its own hardware and logic are healthy. Safety and diagnostics therefore extend from sensor inputs through the FPGA or SoC and out to the trip coils. Self-tests on power-up and during operation check measurement channels, power rails, clocks and trip outputs, while watchdogs supervise firmware and logic. These mechanisms support functional safety targets such as SIL and ensure that a failure in the relay itself does not silently compromise fault clearance.

Typical designs include loop diagnostics on trip circuits, zero and reference checks on current and voltage channels, power-good and brownout monitoring on all supply rails, and clock supervision tied to time-tag quality. FPGA and CPU domains are supervised by independent watchdogs, and critical protection paths for differential or distance elements may use redundant logic or voting. When any self-test or monitor detects a problem, the relay moves into a defined fail-safe state, while still recording events for later analysis.

Functional safety certification builds on these diagnostics. Device-level failure modes and effects analysis, diagnostic coverage estimates and proof-test intervals define which architectures are suitable for different SIL levels. A protection relay with robust self-test coverage, monitored supply and clock domains, protected configuration memory and clear safety manuals gives utilities a clearer path to meeting system-level safety requirements across feeders, transformers and busbar protection schemes.

IC selection map / vendor mapping

A modern protection relay is built from a set of repeatable IC building blocks. Current and voltage sensing chains rely on precision amplifiers, sigma-delta modulators and isolation devices, while ADCs and timing devices deliver synchronised samples for the protection core. FPGA or SoC devices implement the protection logic and communication stacks, and industrial I/O and driver ICs interface to trip coils, auxiliary relays and status contacts. Power supervisors, watchdogs and temperature monitors support the safety and diagnostics functions described in the previous section.

IC selection therefore starts with a functional map: sensing and isolation, ADC and timing, processing, trip and I/O drivers, safety monitors and communication interfaces. Each block has its own key parameters, such as common-mode immunity and isolation rating for AFEs, resolution and simultaneous sampling for ADCs, logic and memory resources for FPGAs and SoCs, and fault reporting capabilities for high-side drivers and digital input modules. Suitable vendors often offer complete families around these functions, simplifying design reuse across multiple relay types.

Vendor mapping is easiest when framed by these functional blocks. Some suppliers focus on high-precision AFEs and isolated modulators for CT and VT interfaces. Others specialise in FPGA and industrial SoC platforms with time-sensitive networking and functional safety support. Additional vendors bring strong portfolios in industrial I/O and relay drivers, or in power supervision and watchdog ICs. Grouping devices in this way helps design teams compare options, plan second sources and build consistent relay platforms across multiple voltage levels and applications.

Application examples

MV feeder OC/EF relay with recloser coordination

A typical medium-voltage feeder relay guards the connection between a busbar and an outgoing feeder in the 10–35 kV range. The primary objective is to clear phase-to-phase and phase-to-earth faults along overhead lines or cable sections without disturbing healthy feeders. Overcurrent and earth-fault elements are configured as the main protection, sometimes complemented by undervoltage and underfrequency, while a separate recloser controller attempts fast and delayed reclosing after transient faults.

CTs on the feeder breaker provide phase currents and zero-sequence components. The relay computes RMS currents and residual current, then applies definite-time and inverse-time curves. Instantaneous or short-delay overcurrent picks up near-end high-current faults, and longer inverse-time curves cover overload and further-out faults. Earth-fault thresholds are chosen according to the system earthing method so that high-resistance faults and low residual currents are still detected without reacting to normal unbalance or capacitive currents in long cables.

Coordination with upstream busbar protection is achieved on the time–current plane. The feeder relay curves sit lower and to the left, with shorter operating times and slightly lower pickups, while busbar relays use higher settings and longer delays as backup. Reclosing logic uses the relay’s trip information and faulted phase indication to decide how many reclosing attempts are allowed, how long to wait and when to block further reclosure after repeated faults. This architecture drives requirements for robust current sensing AFEs, medium-resolution ADCs, protection-grade FPGA or SoC devices and trip drivers with feedback so that each operation can be verified and recorded.

HV/MV transformer differential protection with backup overcurrent

Large HV/MV transformers require fast, selective protection for internal faults while tolerating through-faults and magnetising inrush. Transformer differential protection therefore becomes the main element, supported by overcurrent and earth-fault functions as backup. CTs on each side of the transformer feed a multi-channel measurement chain that compensates for ratio, vector group and zero-sequence handling before forming operate and restraint currents for the differential algorithm.

Inside the FPGA or SoC, phase currents from each side are scaled to a common base and rotated according to the winding connection so that internal faults appear as rising differential current. A multi-slope characteristic defines how much unbalance is tolerated at different restraint levels, and harmonic restraint distinguishes between fault currents and energisation inrush by analysing the ratio of second or higher harmonics to the fundamental. When the differential element declares an internal fault, it overrides backup elements and commands an immediate trip of the transformer breakers on all relevant sides.

Backup overcurrent and earth-fault functions protect against prolonged overload, external faults and situations where CT saturation or configuration errors would otherwise mask a genuine fault. Thresholds and time delays are coordinated so that line or busbar protection clears external faults first, while the transformer relay only intervenes when local limits are challenged. This application drives the need for higher-precision AFEs and ADCs, sophisticated FPGA logic for vector and harmonic processing, and strong self-diagnostics around CT wiring, configuration data and differential calculations to support higher SIL targets.

Transmission line distance protection with zone coordination

At transmission levels, distance protection becomes the primary tool for clearing faults along long overhead lines. CTs and VTs at each line terminal feed a protection relay that computes phasors for line currents and voltages, then derives apparent impedance to the fault. Zone 1 covers most of the protected line with the shortest operating time, while Zone 2 and Zone 3 extend reach to the remote end and adjacent lines with increased intentional delay so downstream relays can act first.

The FPGA or SoC calculates phase and sequence components, forms impedance in the R–X plane and compares the result against direction-sensitive zone characteristics. Load encroachment regions are shaped to prevent heavy load or power swings from entering fault zones. Overcurrent and earth-fault elements provide backup in case VT failures, configuration errors or unusual system conditions compromise the distance measurement. Coordination across multiple terminals depends on consistent line data, communication-assisted schemes and carefully staggered Zone 2 and Zone 3 timing.

This use case pushes requirements on ADC phase accuracy, phasor computation performance and time synchronisation. Devices with TSN-capable Ethernet, PTP hardware timestamping and powerful processing engines support both distance protection and synchrophasor reporting. Safety and diagnostics focus on VT health monitoring, configuration consistency checks, supervision of time quality and robust event recording so that misoperations and near-miss events can be analysed in detail.

Compact OC/EF relays in RMU and ring-main applications

In compact ring-main units and secondary substations, protection relays often take a more integrated form. Overcurrent and earth-fault elements remain the core, but packaging, power consumption and wiring simplicity become as important as raw feature count. Many designs use highly integrated metering and protection SoCs with built-in AFEs, ADCs, CPUs and communication interfaces to support multiple feeders in a single enclosure.

Protection settings are tuned to the characteristics of the local network, which may include looped cables, small distribution transformers and mixed customer loads. Selectivity must still be maintained with upstream feeder relays and upstream reclosers, but there is less emphasis on complex differential or distance schemes and more on ease of deployment, self-powered operation and maintenance-friendly diagnostics. Simple but reliable self-tests on measurement channels, trip outputs and communication links help operators identify units that need attention before a fault occurs.

These constraints favour IC choices that combine multiple functions in a small footprint. Integrated metering SoCs, digital isolation devices with multiple channels, compact industrial I/O drivers and efficient power supervision ICs enable high channel counts and remote monitoring within a limited form factor. Designs built in this way can be reused across different RMU and ring-main variants, reducing engineering effort while keeping protection behaviour consistent across a fleet of installations.

FAQs about protection relays

These twelve questions focus on real protection decisions rather than basic definitions. Each answer summarises how protection relays are positioned in the system, how elements are combined, which measurements and thresholds matter, and what to look for in safety, diagnostics and IC selection when building or specifying modern protection solutions.