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Precision Rectifier / Peak Hold for Envelope & Limit Detection

Precision Rectifier / Peak Hold for Envelope & Limit Detection

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Precision rectifier + peak hold turns tiny, fast-changing AC/envelope signals into a low-threshold, measurable peak that an ADC or comparator can trust. This page shows how to budget dead-zone, distortion, droop, and reset injection, then pick topology/components and validate performance with repeatable bench tests.

What it is (Precision Rectifier vs Peak Hold vs Envelope)

A precision rectifier removes the diode-like dead zone so small signals can be rectified without “missing” near-zero content. A peak hold captures short peaks quickly and holds the value with controlled droop and a predictable reset. Envelope detection is a use case built on rectifying and then smoothing/holding amplitude—this is not the same as true RMS (power-equivalent) measurement.

Quick concept map (engineering view)
Block Output meaning Best for Dominant error term Quick bench check
Precision rectifier Approximates |Vin| (or half-wave) without a diode dead zone. Low-level envelope/threshold detection, AM level detect, pre-processing before ADC/comp. Near-zero “kink” (loop headroom/CMR), switching recovery, diode/switch capacitance. Small-amplitude sine sweep: watch for a turn-on knee and zero-cross distortion.
Peak hold Outputs max(rectified) over a time window; holds between updates. Limit detection, crest/peak capture, short bursts, “capture then ADC read” systems. Droop (leakage/bias) and reset injection; attack time vs Chold. Pulse/burst test: verify captured peak, droop slope, and reset baseline.
Envelope (rectify + smooth/hold) Tracks amplitude contour with a defined time constant (not power-equivalent). Modulation envelope, level indicator, slow limiter control loops, event detection. Time-constant mismatch, ripple vs response, rectifier distortion floor. Step amplitude change: confirm rise/fall time and ripple meet the control/ADC window.
When to use which (fast decision)
  • Need clean rectification at very small amplitudes → Precision rectifier.
  • Need to capture short peaks and hold for an ADC/Comparator decision window → Peak hold.
  • Need a smoothed amplitude contour (envelope timing), not power equivalence → Envelope (rectify + smooth/hold).
  • Need power/true heating equivalence → RMS-to-DC (use the dedicated page).
Precision rectifier and peak hold block overview Block diagram: Raw AC goes into a precision rectifier, then splits to envelope and peak hold outputs feeding an ADC or comparator. Three small waveforms illustrate AC, rectified, and held peak. Raw AC small / burst Precision Rectifier low dead-zone Envelope smooth timing Peak Hold fast capture + low droop ADC / Comparator Waveforms AC Rectified Held peak
A precision rectifier cleans up low-level rectification; peak hold captures short peaks for ADC/comparator decisions while controlling droop and reset behavior.
See also (separate pages)
  • RMS-to-DC Converter (true RMS vs envelope/peak)
  • Clamp & ESD Front-End (protection without killing bandwidth)
  • Sample-&-Hold / Track-&-Hold (hold behavior, injection concepts)

Error model: why “low-threshold” is hard

“Low-threshold” rectification is a loop-and-switching problem, not a single diode Vf problem. The design must keep the loop valid around zero crossing, avoid overload recovery traps, and preserve peak accuracy while a hold capacitor stores charge. Use the four error buckets below as a debugging map: each symptom points to a dominant error term, a fast measurement, and a focused design lever.

Dead-zone (missing small signals)
Symptom

Rectified output stays near zero until the input exceeds a noticeable amplitude; small peaks are not captured.

Likely cause

Loop headroom/CMR limits, output swing limits, or load drive requirements collapse the “super-diode” behavior near zero crossing; large-signal saturation can also create a pseudo dead zone.

Quick check
  • Sweep a small sine amplitude and locate the “turn-on knee” at the rectified output.
  • Probe the op-amp output: any rail-hitting plateau or slow recovery indicates headroom/overload issues.
  • Repeat with lighter/heavier load to reveal drive-related dead zone behavior.
Design lever

Enforce loop validity around zero: guarantee input CM range and output swing margin, avoid output saturation, and keep load/hold paths from demanding current the loop cannot supply.

Distortion (zero-cross kink / THD)
Symptom

Rectified waveform shows a kink near zero crossing; THD/SFDR worsens sharply at small amplitudes or higher frequency.

Likely cause

Switching dynamics dominate: diode/switch capacitance and reverse recovery, loop phase margin collapse during polarity transitions, or op-amp GBW/SR limits during fast edges and charging events.

Quick check
  • Run FFT at minimum amplitude and watch harmonics grow disproportionately (kink-driven spectra).
  • Sweep frequency at fixed small amplitude to separate static offsets from dynamic limitations.
  • Probe the op-amp output for spikes/ringing during polarity transitions.
Design lever

Control transition behavior: select devices with adequate GBW/SR and clean overload recovery, reduce capacitive switching stress, and keep the rectifier loop stable under the real load/hold capacitance seen during transitions.

Droop (held value decays)
Symptom

Peak hold output falls during the hold window, exceeding the allowable error for an ADC read or threshold decision.

Likely cause

Leakage-current dominated behavior: capacitor leakage, diode/switch leakage, buffer input bias current, and PCB surface leakage (humidity/contamination) drain charge from the hold node.

Quick check
  • Measure droop slope (ΔV/Δt) over the actual hold time window.
  • Change Chold: a slope scaling ~1/C indicates leakage dominance; non-scaling suggests injection or loading artifacts.
  • Repeat at two temperatures to expose leakage tempco and board-level leakage paths.
Design lever

Drive droop down by reducing Ileak and protecting the hold node: select low-leakage capacitors/switches, minimize bias currents, use guard/leakage control layout, and avoid probing/loading that becomes the dominant leakage.

Recovery (missed peaks / reset artifacts)
Symptom

Peaks are missed at higher frequency or after large events; reset introduces a false peak, baseline step, or slow settling before valid capture resumes.

Likely cause

Overload recovery of the rectifier loop, inadequate discharge path strength, or charge injection/feedthrough from the reset switch/timing injects a transient onto the hold node that looks like a peak.

Quick check
  • Use burst peaks: compare peak #1 vs peak #2 to reveal recovery memory.
  • Stretch reset timing and vary edge speed: a changing artifact indicates injection/feedthrough dominance.
  • Probe the hold node directly with minimal capacitance loading to confirm real vs probe-induced artifacts.
Design lever

Make recovery deterministic: avoid saturating the loop, set a controlled reset path and timing, and minimize injection by switch choice, edge control, and layout symmetry around the hold node.

Error model map for precision rectifier and peak hold A chain-level error map from input to rectifier to hold node to readout, with tagged error buckets: dead-zone, distortion, droop, and recovery. Input & Source amplitude / f source Z / CM Rectifier Loop dead-zone / THD switching recovery Hold Node droop (I_leak) reset injection Readout ADC / Comp Four error buckets (use as a debug map) Dead-zone → missing small peaks Distortion → zero-cross kink / THD Droop → held value decays Recovery → missed peaks / reset artifacts Map each symptom to a bucket, then fix one dominant term at a time.
Debugging becomes faster when symptoms are mapped to dead-zone, distortion, droop, or recovery—then each later design step targets one dominant term.

Topology map (choose the architecture)

A precision rectifier and peak hold are not single “circuits” but families of architectures. The fastest path to a working design is to choose a branch based on signal type, frequency, minimum amplitude, source impedance, readout load, and recovery/reset needs. Use the flow below to select a topology first—then refine loop stability, capture speed, droop, and reset artifacts in the following sections.

Precision rectifier families (what changes in practice)
  • Half-wave vs full-wave: full-wave refreshes peaks twice as often and reduces ripple for envelope/hold, but adds path mismatch risk.
  • Inverting vs non-inverting: input common-mode and source impedance sensitivity differ; choose the form that preserves loop headroom at the minimum amplitude.
  • “Super-diode” loop: the diode/switch is inside the feedback behavior; success depends on headroom, stability, and recovery at polarity transitions.
Peak hold families (bucket by capture, droop, and recovery)
  • Diode + Chold: minimal parts; best for low-to-mid frequency and relaxed droop/error, but vulnerable to leakage and switching capacitance.
  • Buffered hold: adds a buffer so ADC/comparator loading does not dominate droop and peak error; useful when readout impedance is not high.
  • Active peak detector: improves short-peak capture (attack) at higher frequency, but increases sensitivity to stability and injection.
  • With reset / bleeder: enforces deterministic recovery for windowed measurements; reset timing and injection control become first-order.
Key selection axes (use as the “input constraints” list)
Frequency
Sets loop transition stress and peak capture limits.
Minimum amplitude
Determines headroom and effective dead-zone target.
Source impedance
Affects noise/error injection and rectifier form choice.
Readout load
Decides if a buffer is required to protect the hold node.
Recovery / reset
Defines windowed measurement behavior and false-peak risk.
Power / supply
Impacts headroom, recovery, and feasible GBW/SR class.
Topology selection flow for precision rectifier and peak hold Decision flow: choose based on input type, frequency, minimum amplitude, full-wave need, hold and reset needs, and output interface to ADC or comparator. Topology selection flow Pick a branch first; refine stability, capture, droop, and reset later. Input type AC / pulse / burst High frequency? YES NO Prefer active / buffered active peak / buffered hold Simple hold is viable diode + C_hold (if allowed) Need full-wave? Half-wave lower parts Full-wave less ripple Hold / reset window? Output ADC Comparator Hold buffer if loaded Reset injection control
Start with topology selection: then push performance by tuning loop validity, transition behavior, capture speed, droop, and reset artifacts.
Go next (within this page)
  • Selected a rectifier loop → proceed to Precision rectifier core design below.
  • Selected hold/reset behavior → later sections will cover Chold, droop, and reset injection.

Precision rectifier core design (super-diode behavior)

A “super-diode” precision rectifier behaves like an ideal diode because the closed loop forces the diode/switch path to conduct without a large threshold. In practice, the loop only stays ideal if four hard conditions are met: headroom, speed, stability, and recovery. The steps below translate required rectification accuracy into concrete constraints and verification checks.

1
Define targets (what must be preserved)
  • Minimum amplitude that must rectify without a knee (dead-zone target).
  • Maximum frequency / edge rate that must capture peaks without droop or miss.
  • Allowed distortion near zero crossing (kink-free criterion) and allowed recovery time after large events.
2
Translate to constraints (four hard gates)
Headroom
Input common-mode and output swing must keep the loop valid around zero crossing; avoid rail hits.
Speed
GBW/SR and output drive must support transition edges and charging events without lag or flattening peaks.
Stability
Phase margin must remain adequate with real diode/switch capacitance and any hold/load seen during transitions.
Recovery
Avoid overload saturation; choose fast overload recovery and control diode/switch reverse recovery artifacts.
3
Choose implementation ranges (keep transitions gentle)
  • Limit capacitive switching stress: keep diode/switch capacitance and any seen capacitance from becoming the dominant transition load.
  • Avoid rail hits: keep the loop away from output saturation across amplitude and common-mode corners.
  • Minimize mismatch for full-wave: ensure the two half-cycle paths do not introduce gain/phase asymmetry that biases peaks.
4
Verify (minimum set of tests)
Dead-zone sweep
Small amplitude sweep: knee must be below the minimum signal target.
Zero-cross distortion
FFT near minimum amplitude: no dominant kink-driven harmonics.
Transition ringing
Probe loop output: no sustained ringing at polarity changes.
Overload recovery
Large → small burst: peak capture must recover within the window.
Super-diode concept: loop, diode path, and transition behavior Abstract diagram of a super-diode precision rectifier showing the op-amp loop, diode conduction path, and error paths. A small waveform panel illustrates polarity transition and possible ringing/saturation artifacts. Super-diode behavior (abstract) Op-amp loop Vin Vout Diode / switch path Headroom Stability Recovery Polarity transition Vin Loop out Rectified ringing saturation Practical focus Keep the loop valid at zero crossing, prevent overload recovery, and minimize switching stress to avoid kinks and missed peaks.
A super-diode rectifier is a closed-loop system: headroom, speed, stability, and recovery jointly determine whether “low threshold” holds in real hardware.

Component choice: op-amp + diode/switch (what actually matters)

Datasheets become actionable when each spec is mapped to the rectifier error model. For precision rectifiers and peak detectors, the dominant failure modes usually land in four buckets: dead-zone, distortion (THD), droop, and recovery. Use the table below to evaluate parts by impact, quick checks, and hidden risks—not by marketing headlines.

Practical selection rules
  • Headroom first: common-mode and output swing must keep the loop valid at the minimum signal amplitude.
  • Transitions are the stress test: polarity flips expose SR/drive limits, stability loss, and charge effects.
  • Recovery is not optional: overload recovery can dominate peak accuracy after large events.
  • Leakage is a system budget: device leakage + capacitor leakage + PCB leakage add directly into droop.
Spec → impact → quick check → risk (engineering table)
Metric What it affects Quick check Risk / gotcha
Op-amp (rectifier loop)
Input common-mode + output swing Dead-zone “knee”, missing half-cycles, false clipping near rails. Evaluate worst-case CM and minimum amplitude; ensure loop does not hit rails across temperature and load. RRIO labels do not guarantee swing under load; rail hits cause slow recovery and distortion.
GBW Transition fidelity, small-signal tracking; reduced peak error at frequency. Sweep frequency at minimum amplitude; peak attenuation and zero-cross artifacts indicate loop gain shortage. High GBW without phase margin can ring at polarity changes (false peaks).
Slew rate (SR) Peak “flattening”, missed short peaks, distortion at large edges. Drive the largest expected output swing at target frequency; look for triangular waveforms or peak droop. SR limitations often masquerade as “diode threshold” problems.
Output drive (current) + load stability Charging Cj/C_hold, ringing, slow settling, peak bias. Scope the loop output at transitions; watch overshoot/ringing with real load and PCB parasitics. “Stable in unity gain” does not guarantee stability with dynamic diode capacitance.
Input bias (Ib) + offset (Vos) Droop contribution, small-signal error, baseline shifts in held value. Measure hold droop at different temperatures; correlate slope with Ib expectations. Input protection/leakage can dominate at high temperature and high impedance nodes.
Overload / saturation recovery Post-overload “deaf” time; wrong peaks after large events. Large → small burst test; verify peak accuracy returns within the measurement window. Recovery failures often look like droop/noise; the fix is recovery, not filtering.
Diode (when used as the switching element)
Junction capacitance (Cj) Transition spikes, ringing risk, high-frequency peak error. Inspect transition waveform while sweeping frequency; spikes growing with frequency point to Cj stress. Low Cj helps speed but may increase leakage or reduce robustness depending on diode type.
Reverse recovery (Qrr / trr) Distortion and delay around polarity flips; wrong peak capture at higher frequency. Look for asymmetric behavior between half-cycles and “hang time” after flip. Fast recovery is beneficial, but interaction with loop stability must be checked.
Leakage (temperature dependence) Droop slope and hold accuracy at high temperature. Temperature sweep of droop; strong exponential rise indicates device leakage dominance. Leakage can exceed capacitor leakage; do not assume the capacitor is the only droop contributor.
MOS switch (when replacing the diode)
On-resistance (Ron) Capture speed (attack) and amplitude-dependent error. Check peak capture on short pulses; slow capture often indicates too much path impedance. Ron varies with signal voltage and temperature; nonlinearity can show up as THD.
Charge injection (Qinj) + feedthrough Hold step error, false peaks, reset artifacts. Scope the hold node during switching/reset; quantify step size and decay. Faster control edges often increase injection; slowing edges reduces injection but can degrade timing.
Off leakage Droop (often worst-case at temperature) and hold-window accuracy. Hold droop temperature sweep; compare to capacitor-only expectation to locate dominance. Off leakage can exceed diode leakage depending on switch structure and biasing.
Table usage tip: start from the minimum signal amplitude and maximum frequency/edge rate, then verify recovery using a large→small burst test.
Symptom → likely dominating spec (fast triage)
Peak shrinks as frequency rises
SR / output drive / diode Cj / switch path impedance
Kink or spur near zero crossing
Headroom + stability at transition + reverse recovery
Hold value drifts too fast at hot
Device leakage (diode/switch) + op-amp Ib + PCB leakage
After overload, small peaks are wrong
Saturation recovery + reverse recovery + loop rail hits
Spec-to-error mapping matrix for precision rectifier and peak hold Left side lists device specs for op-amp, diode, and MOS switch. Right side shows error buckets: dead-zone, THD, droop, and recovery. Lines indicate strong coupling between specs and error sources. Spec → error mapping Use lines as “what to care about” hints (thicker line = stronger coupling). Dead-zone headroom THD transition Droop leakage Recovery overload Op-amp Headroom GBW SR Drive Ib Vos Stability Recovery Diode Cj Qrr Leak Temp drift MOS switch Ron Qinj Feedthrough Leak
Use the mapping to prioritize part specs by the error bucket that matters most in the target measurement window.

Peak hold capacitor network (droop, hold accuracy, response time)

Peak hold performance is defined by three coupled behaviors: capture (attack), hold accuracy (droop + step errors), and recovery (release/reset). The correct design approach is to start from a droop target and convert it into an allowable leakage current budget, then select a capacitor and switching strategy that still meets the required capture speed.

Selection logic (droop target → leakage budget → capacitor choice)
  1. Define the hold requirement as ΔV per window (for windowed measurements) or mV/s (for continuous hold).
  2. Convert to an allowed total leakage current budget that includes: capacitor leakage, switch/diode leakage, op-amp input bias, and PCB leakage.
  3. Choose a capacitor family that can meet leakage and stability over temperature (common options include C0G/NP0 and film for low leakage).
  4. Verify capture speed (attack) with the worst-case peak width and repetition; then verify recovery/reset for the required duty cycle.
Engineering checkpoint
If measured droop increases sharply with temperature, device leakage (switch/diode or input structures) is often dominating—not the capacitor alone.
Droop contributors (budget as currents)
Capacitor leakage
Dielectric-dependent; verify drift and leakage across temperature.
Switch / diode leakage
Often dominates at high temperature; also interacts with bias conditions.
Op-amp input bias (Ib)
Matters most when the hold node is high impedance and long hold windows are used.
PCB leakage
Humidity/contamination can become first-order; guard rings and cleanliness are design features.
Speed vs droop (what “too large C_hold” breaks)
  • Larger C_hold reduces droop for a given leakage current budget, but slows capture (attack) when the charging path is limited.
  • Short peaks require fast charge delivery: path impedance, op-amp drive, and switching element behavior set the real attack limit.
  • Reset becomes harder: more stored charge increases reset time and makes reset injection artifacts more visible.
Design intent guardrail
Choose C_hold to satisfy droop and the minimum peak width; then improve droop by reducing leakage paths before scaling C_hold upward.
Verification checklist (minimum tests)
Hold droop
Measure slope at temperature corners; pass when droop stays within the window budget.
Attack (capture)
Apply the shortest peak; pass when held value reaches the required fraction before the peak ends.
Reset / recovery
Windowed test: pass when reset-to-valid time meets duty cycle and no false peaks appear.
Switching artifacts
Scope the hold node; pass when step error and ringing stay below the measurement tolerance.
Peak-hold capacitor network: state machine and droop slope Three-state diagram for charge, hold, and reset with current-path arrows. A small plot shows droop as a voltage slope over time (ΔV/Δt). Peak hold: charge / hold / reset Treat droop as a leakage-current budget; treat attack as a charge-delivery limit. State machine CHARGE Icharge HOLD Ileak RESET Bleed Peak update Window end Next cycle Hold node (C_hold) current paths C_hold Cap leak Switch leak Op-amp Ib PCB leakage Droop slope time V ΔV / Δt = droop Attack Recovery
Peak hold design is a three-state problem: charge fast enough, hold with a leakage budget, and reset without injection-driven false peaks.

Reset / discharge / bleeder strategies (fast recover without bias)

Peak hold designs often succeed at capture but fail at repeatability: reset must be fast enough for the next window, while avoiding injection-driven steps and residual bias that inflate or corrupt the next peak. This section provides three proven reset modes and a timing approach that reduces false peaks.

Three reset metrics (design targets)
Reset-to-valid time
Time from reset start to Vhold within ±X mV of the intended baseline (X from system budget).
Injection step (ΔVstep)
Switching edges can create a step or spike on Vhold; limit ΔVstep < Y mV to prevent false peaks.
Residual bias
Any DC pull or offset after reset becomes a systematic error; verify baseline stability across temperature and duty cycle.
Three practical reset modes (choose by window rate and error budget)
Mode A: Passive bleeder resistor
  • Pros: lowest injection risk; simplest; predictable EMI behavior.
  • Risks: increases droop directly; reset speed trades against hold accuracy.
  • Best for: low window rate; long hold windows; injection-sensitive measurement chains.
Mode B: Controlled MOS discharge
  • Pros: fast reset; programmable pulse width; supports high window repetition.
  • Risks: Qinj/feedthrough creates ΔVstep; discharge current can trigger ground bounce.
  • Best for: medium-to-high window rate where reset time is a hard constraint.
Mode C: Analog switch short + two-phase timing
  • Pros: reduces false peaks by isolating the rectifier path before discharge; repeatable windows.
  • Risks: requires timing control; still needs layout discipline to avoid coupling.
  • Best for: high window rate or noisy inputs where reset artifacts can be mistaken as peaks.
Why reset creates “false peaks” (fast diagnosis)
Charge injection + feedthrough
Reset edge couples into Vhold; reduce ΔVstep by selecting low-injection switches, controlling edge rate, and minimizing coupling capacitance.
Ground bounce (return-path inductance)
Fast discharge currents lift local ground; keep the discharge loop compact and return paths continuous.
Discharge through the rectifier loop
If the rectifier path remains enabled, the discharge event can back-drive internal nodes and appear as a peak. Two-phase timing prevents this.
When track-and-hold timing is required (track window + hold window)
  • Use TRACK when the peak arrival time is uncertain and the maximum value must be captured within a defined window.
  • Use HOLD when downstream reading (ADC/comparator) needs a quiet, stable value for a measurement window.
  • Use RESET when the next measurement must not inherit prior charge; enforce reset-to-valid before the next track window.
Track / Hold / Reset timing and key node waveforms A timeline is split into track, hold, and reset windows. Control signals show rectifier enable and reset switch. Node waveforms illustrate input, hold node behavior, and reset injection step. Timing: TRACK → HOLD → RESET Two-phase timing: disable rectify path before discharging the hold node to reduce false peaks. TRACK window HOLD window RESET Control signals Rectify_EN Reset_SW Key node waveforms Vin Vhold Vread ΔVstep risk
Use two-phase timing to prevent the discharge event from coupling back into the rectifier loop and appearing as a false peak.

Practical measurement & debug (what to probe, how to validate)

Debug is fastest when each target behavior has a fixed test recipe. The checklist below uses a consistent format: input condition → probe points → pass criteria → common false read. Three probe points are repeatedly used: TP1 Vin, TP2 rectifier/loop output, and TP3 Vhold.

Debug checklist (bench-ready)
Test item Input condition Probe points Pass criteria Common false read
Low-threshold distortion Sine sweep at very small amplitude; repeat across frequency and temperature corners. TP1 Vin; TP2 loop/rectified node; TP3 Vhold (if peak mode enabled). No visible “knee” at zero-cross; harmonics within budget (THD/SFDR target at minimum amplitude). Scope bandwidth limits or filtering can hide the knee; probe capacitance can change switching behavior.
Peak capture (attack) Pulse or envelope bursts with the minimum expected peak width and repetition rate. TP1 Vin; TP2 loop output; TP3 Vhold. Vhold reaches the required fraction of the true peak before the pulse ends; no overshoot-induced false peaks. Probe loading can slow attack; trigger placement can misalign perceived peak timing.
Droop (hold accuracy) Hold a fixed peak; measure droop slope across temperature; compare capacitor options and cleanliness. TP3 Vhold (primary); TP2 for leakage back-path clues. Droop slope < X mV/s (or ΔV < X mV per hold window) at temperature corners. Switching leakage can dominate at hot; droop may be blamed on C_hold when the switch is the real source.
Reset artifacts (false peaks) Run repeated track/hold/reset cycles; vary reset edge rate and timing (two-phase vs single-phase). TP3 Vhold (ΔVstep); TP2 (loop disturbance); TP1 for external coupling checks. ΔVstep < Y mV; reset-to-valid < Treset; no peaks appear during reset window. Ground lead inductance creates apparent spikes; use a ground spring and short return paths.
Always repeat tests with a short ground spring and a 10× probe first, then confirm with an alternate probing method to rule out probe-induced behavior.
Measurement traps (quick counter-checks)
Probe capacitance changes the circuit
Counter-check: 10× vs 1× comparison, or add a buffer probe point. A behavior change implies the node is too high impedance or too fast for direct probing.
Ground lead inductance creates “fake spikes”
Counter-check: replace the long ground clip with a ground spring; spikes that disappear are measurement artifacts.
Scope BW/filter settings hide or invent problems
Counter-check: toggle bandwidth limit and digital filtering; a real injection step remains present across settings, only its appearance changes.
Trigger alignment misrepresents peak timing
Counter-check: trigger on TP1 input and cross-check TP3 hold node with the same time reference; confirm attack time against the defined peak window.
Bench debug setup and probe points for precision rectifier and peak hold Block diagram: signal source to DUT, with scope and ADC connections. Three test points are marked: TP1 input, TP2 rectifier/loop node, TP3 hold node. Notes highlight probe capacitance, ground, and bandwidth settings. Bench setup: what to probe Use consistent test points (TP1/TP2/TP3) to separate input issues, loop issues, and hold-node issues. Signal source sine / pulse DUT Rectifier / loop TP2 Hold node (C_hold) TP3 Readout buffer to ADC/comp TP1 Vin Oscilloscope BW / probes ADC / logger window read Probe C matters Ground spring BW / filter check
Keep probe points consistent (TP1/TP2/TP3) so each test isolates input integrity, loop behavior, and hold-node accuracy.

Protection & layout (keep it fast, keep it linear)

Protection is not “free” in a precision rectifier/peak-hold front-end: every added part brings parasitics (capacitance, leakage, nonlinearity, return-path changes). The goal here is a minimum protection set that preserves bandwidth and linearity, while keeping the hold node clean, stable, and repeatable across temperature and window rate.

Protection (minimum actions)
Series R for current limiting
Limits transient current and reduces stress; verify that the added pole does not slow peak attack below the required window.
Low-cap clamp in the protection zone
Use a low-C clamp where it can divert energy without becoming part of the precision signal path. Avoid bringing clamp capacitance into the rectifier loop.
Hold node isolation
Keep the hold node out of the “protection C” footprint. The hold node is high impedance: leakage and contamination directly become droop and drift.
Leakage control (keep Vhold stable)
Guard ring + keepout around Vhold
Surround the hold node with a guard to intercept surface leakage; keep digital traces and test pads away from the high-impedance area.
Cleanliness and humidity sensitivity
Flux residue and moisture create resistive paths to ground. A hot-corner droop increase is a strong sign that board leakage dominates.
Failure signature
Droop slope accelerates at hot; baseline does not return after reset; “memory” or rebound appears after discharge. Treat these as leakage-path symptoms first.
Grounding & return paths (avoid false peaks)
Keep the rectifier loop short
Minimize loop area (op-amp output → diode/switch → Vhold → feedback). Large loops amplify coupling, ringing, and injection sensitivity.
Keep digital edges away from Vhold
Route reset/control edges in a separate zone with a clean return path. Avoid crossing the hold guard region to prevent step injection.
Differential chains
If driving an ADC with differential inputs, the output common-mode must be controlled. Use a dedicated SE↔diff stage where required (see the FDA page).
Layout concept zones for protection, precision rectification, and hold node guarding Abstract layout blocks: input protection zone with series resistor and low-cap clamp, precision rectifier zone with short loop, hold node zone with guard ring and keepout, and digital control zone separated to avoid edge coupling. Dashed arrows indicate leakage paths and forbidden crossings. Layout concept: keep it fast, keep it linear Partition zones so protection capacitance and digital edges do not contaminate the rectifier loop or the hold node. Input protection Series R Low-C clamp to return Precision rectifier Op-amp + diode Short loop Hold node Guard ring Vhold keepout Leakage paths Digital control Reset edge Timing Do not cross guard Zone A Zone B Zone C Zone D
Place clamps in the protection zone, keep the rectifier loop compact, and guard the hold node to prevent leakage, drift, and reset-induced false peaks.

Design checklist (Engineering checklist)

This checklist is designed to be reused in design reviews, verification, and production readiness gates. Each item includes a pass criteria placeholder so system-specific budgets can be applied without rewriting the template.

Review & verification checklist (priority-ordered)
☐ Item Why it matters How to verify Pass criteria (placeholder)
☐ Minimum input amplitude Sets the low-threshold distortion budget (dead-zone risk). Small-signal amplitude sweep + FFT at corner temperatures. THD/SFDR within target at Amin: < X dBc
☐ Max frequency / shortest peak width Determines attack capability and loop dynamics. Pulse/envelope burst test at min width and repetition rate. Capture error: < X mV within window
☐ Allowed droop Sets leakage budget for C_hold, switch/diode, and board surface. Hold slope measurement across temperature corners. Droop slope: < X mV/s (or ΔV per window)
☐ Reset time budget Prevents “memory” across measurement windows. Repeated track/hold/reset cycles with timing variations. Reset-to-valid: < X ms; ΔVstep: < Y mV
☐ Op-amp: GBW / SR / recovery Insufficient dynamics inflate distortion and attack error. Step/pulse response + overload recovery test at corners. No saturation hang; settling: < X μs
☐ Diode/switch: Cj / leakage / injection Cj and injection affect THD and false peaks; leakage sets droop. Small-signal FFT + reset edge ΔVstep measurement. ΔVstep: < Y mV; leak budget met at hot
☐ C_hold: leakage / dielectric absorption Leakage drives droop; absorption can create rebound after reset. Droop slope + reset rebound test across temperature. Droop: < X mV/s; rebound: < X mV
☐ Error budget coverage Ensures no hidden term dominates (dead-zone/THD/droop/injection). Review budget table + verify each term has a test hook. All terms assigned & tested; margins: > X%
☐ Post-ESD drift check Detects latent damage that changes leakage or distortion. Repeat droop + low-threshold FFT after stress. No shift beyond budget: < X%
Tip: treat “X/Y placeholders” as system budgets and keep them consistent across spec, budget, and test artifacts.
Checklist ordering (why this sequence works)
  1. Lock spec boundaries (Amin, Fmax/peak width, droop, reset).
  2. Verify components against the error model (dynamics, leakage, injection).
  3. Write an error budget that assigns ownership and test hooks.
  4. Run a test plan that hits amplitude, frequency, temperature, and window repeatability.
Workflow: spec to budget to test for precision rectifier and peak hold Three-stage flow: Spec defines amplitude, frequency, droop, reset, temperature; Budget allocates dead-zone, THD, droop, injection; Test verifies with amplitude sweep, pulse capture, droop slope, reset cycle, temperature corners and closes the loop to fixes. Spec → Budget → Test (engineering flow) Keep placeholders consistent across documents: the same X/Y targets appear in spec, error budgets, and pass criteria. SPEC BUDGET TEST Amin (min amplitude) Fmax / peak width Droop target Reset time budget Temperature corners Dead-zone budget THD / SFDR budget Droop budget Injection budget Amplitude sweep + FFT Pulse capture (attack) Droop slope vs temp Reset cycle consistency Corner repeatability Pass / Fix loop
A disciplined flow prevents hidden terms: spec defines corners, budgets allocate error ownership, and tests confirm repeatability across amplitude, frequency, and temperature.

Applications (where rectifier + peak hold actually wins)

This block is strongest when the system needs low-threshold detection, fast peak capture, and a hold window long enough for an ADC/comparator/MCU to make a deterministic decision. The examples below intentionally avoid true-RMS and lock-in topics (those belong to their dedicated pages).

A) Envelope / limiter detection (audio, vibration, ultrasound gate)
Goal
Generate an envelope / limit trigger that remains valid at low amplitude and high crest-factor signals.
Signal
Bursty waveform with short peaks; detection window must be stable across temperature and repetition rate.
Why this block
Precision rectifier removes the low-level diode dead-zone; peak hold freezes the envelope peak for deterministic thresholding.
Gotcha
Attack is often probe- and layout-limited; reset edge injection can create false triggers if the hold node is not guarded.
Reference materials (examples)
Op-amp: OPA197, OPA2140, OPA320 · Diode: BAV199, 1N4148 · Switch (reset): TMUX1101, ADG884 · Chold: GRM1555C1H102JA01D (NP0, 1nF), GRM1885C1H103JA01D (NP0, 10nF)
B) Peak capture for safety / overload (shock and transient events)
Goal
Capture a narrow peak and hold it long enough for logging or for a protection decision.
Signal
Rare, short-duration over-limit spikes; peak width may be smaller than the ADC sampling period.
Why this block
Peak hold decouples the decision from ADC timing; the rectifier keeps small over-limit events visible instead of being lost in thresholds.
Gotcha
Reset strategy sets event-to-event independence; without a controlled discharge, “residual peak” can bias the next measurement.
Reference materials (examples)
Op-amp (fast capture): OPA355, OPA356, ADA4807-1 · Diode (fast switching): 1N4148W, BAV99 · Switch (low injection): TMUX1108, TS5A23157 · Chold: C1608C0G1H102J (TDK NP0, 1nF), GRM1885C1H102JA01D (NP0, 1nF)
C) AM demod / level detect (low-amplitude advantage)
Goal
Detect amplitude variations when the carrier is small enough that a passive diode detector becomes threshold-limited.
Signal
Higher-frequency carrier with a slower envelope; the rectifier must remain linear across the carrier band.
Why this block
The active loop collapses the effective threshold; a hold/RC stage provides a stable level for downstream measurement.
Gotcha
Insufficient GBW/SR can look “working” but injects distortion; clamp capacitance can silently dominate the linearity budget.
Reference materials (examples)
Op-amp (bandwidth headroom): OPA820, OPA828, AD8065 · Diode (low C): HSMS-2850, BAS70-04 · Switch: ADG1211, TMUX1112 · Chold: GRM1555C1H101JA01D (NP0, 100pF), GRM1555C1H102JA01D (NP0, 1nF)
D) ADC front-end peak monitoring (pre-saturation warning)
Goal
Detect and hold peak excursions that could saturate the measurement chain, even if the ADC misses the exact peak instant.
Signal
Near-full-scale amplitude; occasional spikes; peak detection must not add significant loading or distortion to the main path.
Why this block
A dedicated peak-hold monitor provides deterministic peak visibility without relying on sampling phase or firmware timing.
Gotcha
Ground bounce and reset coupling can mimic peaks; keep digital edges and clamp capacitance out of the hold node region.
Reference materials (examples)
Op-amp (RRIO monitor): OPA320, OPA192, OPA197 · Diode: BAV199, 1N4148W · Switch: TMUX1101, ADG884 · Chold: GRM1555C1H102JA01D (NP0, 1nF), GRM1885C1H103JA01D (NP0, 10nF)
Application chains for precision rectifier and peak hold Three application chains show how sensor signals flow through a precision rectifier and peak hold to a comparator, ADC, and MCU. Small waveform icons illustrate raw AC, rectified, and held peaks with minimal labels. Typical chains (2–3 patterns) Sensor → Rectifier → Peak Hold → Comparator/ADC → MCU Raw Burst Carrier A) Threshold / trigger Sensor Rectifier Peak Hold Comparator → MCU Injection Droop B) Peak logging Sensor Rectifier Peak Hold ADC → MCU C) AM level detect RF/IF in Rectifier Envelope/Hold ADC/DSP
Use the peak-hold monitor when decision timing cannot be guaranteed by sampling alone, or when low-level thresholds dominate passive detection.

IC selection logic (what to ask vendors / what to filter on)

The parts below are reference examples (starting points only). Final selection must be driven by the local error model (dead-zone, THD, droop, recovery, injection), worst-case corners, and the validation hooks in the checklist.

A) Must-ask fields (copy into RFQ / vendor email)
Op-amp (rectifier loop / buffer)
  • Input range (ICMR) across temperature at the target common-mode and amplitude.
  • Output swing/headroom and output current at the actual load and frequency.
  • GBW and slew rate (conditions required: supply, load, Vout swing).
  • Overload/saturation recovery (time to return to linear operation after rail hit).
  • Input offset and bias current (corner values, not only typical).
Example op-amps (by intent)
Low-leak / bias-sensitive: OPA2140, OPA140, ADA4625-1 · RRIO general: OPA320, OPA192, OPA197 · Fast capture: OPA355, OPA356, ADA4807-1, AD8065
Diode / analog switch (dead-zone, THD, injection)
  • Capacitance vs voltage (C-V) and leakage vs temperature.
  • Switch charge injection and feedthrough (test conditions required).
  • Reverse recovery / switching behavior (if diode is used at higher frequency).
  • On-resistance vs signal level (if MOS switch is used in the signal path).
Example diodes / switches
Low-leak diodes: BAV199 · General fast diodes: 1N4148W, BAV99 · Low-C Schottky (high-freq): HSMS-2850, BAS70-04
Low-injection switches: TMUX1101, TMUX1112, TMUX1108, TS5A23157, ADG884, ADG1211, ADG1219
Hold capacitor (droop + memory)
  • Leakage at hot corner and long-term drift behavior.
  • Dielectric absorption / rebound risk after reset (require a bench method).
  • Temperature coefficient and package contamination sensitivity.
Example NP0/C0G MLCC orderable codes
Murata: GRM1555C1H101JA01D (100pF), GRM1555C1H102JA01D (1nF), GRM1885C1H103JA01D (10nF)
TDK: C1608C0G1H101J (100pF), C1608C0G1H102J (1nF)
Platformization (windowed hold/reset + production repeatability)
  • Is a programmable hold/reset window required (MCU-timed track/hold/reset)?
  • Is a low-injection reset switch required (ΔVstep budget)?
  • Are calibration hooks needed (loopback/bypass, EEPROM parameters, temperature re-trim policy)?
Reset switch examples (window control)
Single/dual SPST: TMUX1101, TMUX1112 · Dual SPDT: ADG884 · Low-leak matrix style: ADG1211, ADG1219
B) Use-case buckets (fast filtering)
Low-frequency high-precision
Priority: leakage/bias → droop, then offset and reset injection.
Op-amp: OPA2140, OPA140, ADA4625-1 · Diode: BAV199 · Switch: ADG1211, TMUX1112 · Chold: GRM1885C1H103JA01D
Mid-frequency general purpose
Priority: loop dynamics (GBW/SR) and THD, then reset consistency.
Op-amp: OPA197, OPA320, OPA192 · Diode: 1N4148W, BAV99 · Switch: TMUX1101, ADG884 · Chold: GRM1555C1H102JA01D
High-frequency peak capture
Priority: dynamic headroom + recovery, then parasitic C and injection.
Op-amp: OPA355, OPA356, ADA4807-1, AD8065 · Diode: HSMS-2850, BAS70-04 · Switch: TMUX1108, TS5A23157 · Chold: GRM1555C1H101JA01D
Quick reject rules (keep the shortlist clean)
  • No corner data for leakage/injection → treat as high risk for droop/false peaks.
  • No overload/saturation recovery info → avoid for high-frequency peak capture.
  • Clamp capacitance sits inside the rectifier loop → expect THD and peak error regression.
  • Digital edges cross the hold guard region → expect ΔVstep and phantom peaks.
Selection funnel for rectifier and peak hold components A funnel shows how use case drives specs, which drives component constraints and produces a shortlist. A side rail highlights risk flags: leakage, injection, and recovery. Selection funnel (use case → specs → constraints → shortlist) Filter on what maps to dead-zone, THD, droop, recovery, and injection. Use case Specs Component constraints Shortlist Low-freq precision Mid-band general High-freq peaks Amin Fmax Droop Reset window Op-amp dynamics/recovery Switch C / injection Leakage (hot corner) C_hold absorption risk Layout feasible Test hooks Corner repeat Production-ready Risk flags Leakage Injection Recovery Examples OPA320 OPA197 TMUX1101 ADG884 BAV199 1N4148W
Treat part numbers as starting points; keep the shortlist only if corner leakage/injection/recovery data exists and the layout can protect the hold node.
Reference example list (quick lookup)
Op-amps: OPA197, OPA192, OPA320, OPA140, OPA2140, OPA355, OPA356, OPA820, OPA828, ADA4625-1, ADA4807-1, AD8065
Diodes: BAV199, 1N4148W, BAV99, HSMS-2850, BAS70-04
Analog switches: TMUX1101, TMUX1112, TMUX1108, TS5A23157, ADG884, ADG1211, ADG1219
C0G/NP0 caps (examples): GRM1555C1H101JA01D, GRM1555C1H102JA01D, GRM1885C1H103JA01D, C1608C0G1H101J, C1608C0G1H102J

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FAQs (Precision Rectifier / Peak Hold)

Troubleshooting-only. Each answer is a 4-line, measurable checklist: Likely cause / Quick check / Fix / Pass criteria.

Why does my “precision rectifier” still have a dead zone at small signals?
Likely cause The loop never behaves like a “super diode” due to ICMR/output swing limits or output current limiting at the operating point.
Quick check Sweep Vin amplitude at fixed f (e.g., 1–5 kHz) and monitor op-amp output (Vop); if Vop rails or clips near zero, the rectifier cannot close the loop at Amin.
Fix Move the operating point away from rails (bias/VOCM/gain) or choose an op-amp with guaranteed ICMR + output swing + recovery at the same supply and load.
Pass criteria No “knee” in Vrect vs Vin down to Amin; apparent threshold error < X mV at Vin=Amin and f=Ftest.
Why does THD explode near zero crossing even when DC looks fine?
Likely cause Switching nonlinearity at the polarity transition (diode/switch C, recovery, loop phase margin) creates a spike/step around zero crossing.
Quick check Compare FFT at mid-scale vs near-zero amplitude and scope the rectifier output at the crossing; a repeatable spike (ΔVcross) indicates transition-dominated distortion.
Fix Reduce transition stress (lower parasitic C, tighter loop layout, isolate hold node) or increase loop dynamic margin (GBW/SR/PM) without driving into saturation.
Pass criteria ΔVcross < X mV and THD/SFDR degradation near zero < Z dB relative to the mid-scale reference test.
Why does it work at 1 kHz but fails at 50 kHz (missing peaks)?
Likely cause Attack is limited by op-amp dynamics/output current and the effective charge path impedance into Chold.
Quick check Apply a known pulse/AM-burst and measure attack time (Tattack) to reach 99% of the peak on Vhold; if Tattack > peak width, peaks will be missed.
Fix Lower the effective charge impedance (Rpath), reduce Chold, or use a higher-speed amplifier/switch architecture that avoids saturation during peak capture.
Pass criteria Peak capture error < X mV at f=Fmax and peak width=Wmin; Tattack ≤ 0.3×Wmin (or the project budget).
Why does peak hold droop faster than expected (even with large C)?
Likely cause Leakage current dominates (capacitor leakage, switch leakage, amplifier input bias, or PCB contamination), so increasing C does not fix the root cause.
Quick check With input held constant, measure droop slope S=ΔV/Δt on Vhold at room and hot; if S scales strongly with temperature/humidity, leakage is the driver.
Fix Use low-leak components, guard the hold node, shorten/clean the surface path, and keep the hold node away from flux residue and high-field stress points.
Pass criteria Droop slope S < Y mV/s at the hot corner for the required hold time Thold, and S variation across humidity/cleanliness is within budget.
Why does reset create a false peak / offset step?
Likely cause Charge injection/feedthrough or ground bounce couples the reset edge into the hold node (ΔVstep), creating a phantom peak or offset.
Quick check Toggle reset with a steady input and record Vhold; if a repeatable step appears with reset edge rate (dV/dt), injection is dominant.
Fix Use a lower-injection switch, slow/shape the control edge, apply two-phase timing (disconnect rectify path then discharge), and route reset away from the hold guard region.
Pass criteria Reset-induced ΔVstep < X mV on Vhold and does not trip downstream thresholds over N reset cycles.
Why does changing diode/switch change the held peak by several mV?
Likely cause Parasitic C, leakage, recovery, and injection alter the dynamic error during capture and the bias during hold, shifting Vhold by ΔVpart.
Quick check Run the same 3 tests before/after the swap: (1) capture error vs frequency, (2) droop slope at hot, (3) reset step; identify which term changes.
Fix Select parts by the dominant error term (high-f: low C/recovery; high-precision: low leakage/injection) and keep clamp capacitance out of the rectifier/hold nodes.
Pass criteria ΔVpart < X mV under the same stimulus and temperature, and no regression in THD/capture error/droop beyond the allocated budgets.
Why does probing the hold node change the behavior dramatically?
Likely cause Probe capacitance/leakage becomes a parallel load on a high-impedance node, changing attack, droop, and even loop stability.
Quick check Compare passive ×10 probe vs active probe (or buffer the node); if Vhold shifts by ΔVprobe or droop slope changes, the probe is loading the node.
Fix Use a low-C, high-R measurement method (active probe/buffer) and design an explicit buffer or isolation resistor so the hold node is never directly exposed.
Pass criteria Probe-induced change |ΔVprobe| < X mV and droop slope change < Y% compared to the buffered reference measurement.
Why does temperature shift the held peak even with stable input?
Likely cause Leakage and bias currents increase with temperature, and diode/switch parameters drift, moving the effective capture/hold error.
Quick check At constant input, sweep temperature and log both Vhold(t=0) and droop slope S(T); separate “initial offset shift” from “droop acceleration.”
Fix Use low-leak choices for switch/diode/capacitor, guard the node, reduce thermal gradients, and add a temperature re-zero/recal policy if required.
Pass criteria Held-peak drift < X mV (or X ppm/°C) over the temperature range, and S(T) remains below the hot-corner droop budget.
Why does a larger C_hold make the system “lag” and miss short peaks?
Likely cause A larger Chold increases the required charge, so the capture path cannot reach the true peak within the peak width (attack-limited).
Quick check With a fixed narrow pulse, compare Vhold peak error for C1 vs C2 and measure Tattack; if Vhold under-reaches the peak more as C increases, the path is charge-limited.
Fix Set Chold from peak-width first, then meet droop via leakage control; if droop forces a large C, add windowed track/hold or stronger charge drive.
Pass criteria Capture error < X mV at peak width=Wmin, while droop remains < Y mV/s for Thold (no missed peaks).
How do I validate hold accuracy quickly on the bench?
Likely cause Peak error, droop, and reset step are mixed together in a single test, hiding the dominant mechanism.
Quick check Run a 3-step quick test: (1) pulse peak → capture error, (2) hold with constant input → droop slope, (3) reset toggle only → ΔVstep; record all three metrics.
Fix Create a minimal dataset: capture error vs frequency, droop vs temperature, and reset step vs edge rate; optimize only the worst offender first.
Pass criteria All three meet budget: capture error < X mV, droop < Y mV/s (hot), reset step < X mV across N cycles.
Why does the rectifier saturate and take long to recover?
Likely cause The amplifier hits a rail or current limit during peaks, and overload recovery dominates the next cycles (recovery-limited operation).
Quick check Force an over-range peak, then return to nominal amplitude and measure Trecover until Vrect/Vhold returns to within ±X mV of steady behavior.
Fix Add headroom (bias/supply/gain), limit input overdrive (series R/clamp placement), or select an amplifier with verified fast overload recovery under the same load.
Pass criteria Trecover < Tbudget and no missed peaks/false holds for N subsequent cycles after the over-range event.
Can I use an FDA or fully-differential stage for rectification/hold?
Likely cause Differential operation without controlled common-mode and symmetry can inject CM steps into the hold nodes and create channel mismatch errors.
Quick check Measure VOCM and both hold nodes; if VOCM moves by ΔVOCM during reset/capture or the two Vhold values mismatch by ΔVdiff, symmetry/common-mode control is insufficient.
Fix Use an FDA only with explicit VOCM control, symmetric rectification/hold/reset, and symmetric layout; keep digital edges and clamps away from both hold nodes.
Pass criteria ΔVOCM < X mV over capture/reset, and differential held-peak mismatch |ΔVdiff| < X mV across temperature and repetition rate.
Why does changing diode/switch change the held peak by several mV (even with the same schematic)?
Likely cause The part swap changes parasitic capacitance and injection timing, so the capture transient integrates into a different held value.
Quick check Overlay Vhold during the capture edge for both parts; if the waveform differs only during the first Tcapture microseconds, the error is injection/charge-path dominated.
Fix Select a part with lower injection or add timing isolation (disconnect then discharge), and keep the hold node capacitance dominated by Chold, not parasitics.
Pass criteria Part-to-part held-peak shift < X mV across N captures at the same stimulus, and ΔVstep after reset remains within the injection budget.
Why does THD explode near zero crossing even when DC looks fine (repeatable on some boards only)?
Likely cause Layout-dependent parasitics (loop area, return discontinuity, clamp capacitance) alter phase margin and transition behavior around zero crossing.
Quick check Compare ΔVcross and ringing on Vrect across boards using the same probe method; board-to-board spread indicates parasitic/layout sensitivity rather than pure device variation.
Fix Shrink the rectifier loop, keep clamp devices out of the loop node, and guard the hold node; add controlled damping only if capture error budget allows.
Pass criteria Board-to-board spread of ΔVcross < X mV and THD/SFDR spread < Z dB under the same stimulus and measurement setup.
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