Submeter / Smart Plug: Metering & Switching Architecture
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Core idea: A smart plug/submeter is one board that must measure and switch AC power without letting switching transients, phase error, or heat distort the metrology. This page focuses on a robust single-phase architecture—metering chain, relay/triac/SSR switching, isolation, protection, calibration, and validation—so readings stay stable on real loads.
H2-1. Definition & Engineering Boundary: Smart Plug vs Submeter
This page stays inside a single-phase, outlet-level device boundary: energy metering + switching + isolation-aware control. The goal is to set clear expectations before design trade-offs and debugging topics appear.
Quick boundary table (what this page covers)
| Item | Smart Plug (Outlet-level) | Submeter (Device / Branch-level) |
|---|---|---|
| Primary purpose | Measure energy and control a single load at the outlet | Measure a device or a circuit branch (still single-phase here) |
| Owned topics in this page | Metering signal chain + switching element selection + isolation boundary + practical protections + calibration and validation. | |
| Key design tension | Metering accuracy must survive switching noise and heating (relay/triac/SSR transients, thermal gradients, leakage paths). | |
| Explicitly out of scope | Polyphase / revenue-grade / PLC deep dive; OTA security-chain deep dive; PTP timing deep dive; AC-DC topology deep dive; EMC standards deep dive. | |
Three non-negotiable boundaries (fast checks)
Single-phase only
Outlet / single load
Metering × Switching coupling
- System boundary: single-phase AC input → metering → switching → outlet load. No multi-meter aggregation or polyphase metrology.
- Functional boundary: the engineering loop is “measure reliably while switching safely” (noise, phase, heat, leakage, and repeatability).
- Ownership boundary: anything that turns into a separate discipline becomes a link-out, not a detour.
Link-outs (name only, one-sentence boundary):
Polyphase / anti-tamper / PLC / revenue-grade metering belongs to Utility Metering Module. Secure boot / rollback / attestation belongs to Secure OTA Module. (Replace “#” with the final internal URLs.)
Polyphase / anti-tamper / PLC / revenue-grade metering belongs to Utility Metering Module. Secure boot / rollback / attestation belongs to Secure OTA Module. (Replace “#” with the final internal URLs.)
Figure F1 — What this page owns: outlet-level metering × switching × isolation
H2-2. Typical System Path: From L/N to Load (Board-level only)
A smart plug can be understood as a four-stage path. Each later chapter deepens one stage without changing the boundary. This keeps architecture, debugging, and validation aligned.
Four-stage path (the only map needed)
- AC input & protection: survive faults and transients with predictable behavior.
- Metering front-end & sampling: stable V/I measurement with controlled phase and bandwidth.
- Switching actuation & feedback: relay/triac/SSR choice, drive timing, and transient management.
- Control & communication: local processing and an interface to a radio/host (protocol details are out of scope).
Placement decision that impacts everything: “measure-before-switch” vs “measure-after-switch”
| Choice | Strength | Common pitfall |
|---|---|---|
| Measure-before-switch | Metering is less affected by switch drop/leakage changes | Switching transients can still inject noise into sensing if layout and timing are not controlled |
| Measure-after-switch | Can reflect the “true delivered” energy at the outlet node | Switch element heating and leakage can bias readings; SSR/triac behaviors become part of the metering chain |
A correct choice is requirement-driven: prioritize long-term energy stability vs delivered-node realism,
and consider the dominant load type (resistive vs SMPS/LED/motor). Later chapters convert this into test matrix coverage.
Figure F2 — Board-level block path: metering + switching + isolation boundary
H2-3. Metering Metrics & Accuracy Budget: “Measured” vs “Accurate”
Smart-plug metering fails most often when readings look stable (Vrms/Irms) but drift appears in P, PF, and Wh under heat, switching transients, and non-linear loads. An accuracy budget turns the system into actionable error blocks with clear verification paths.
Metric checklist (what must stay consistent)
| Metric | What it represents | Most sensitive to |
|---|---|---|
| Vrms | Voltage magnitude over a window | Divider tolerance/tempco, RC bandwidth shaping, ADC gain drift |
| Irms | Current magnitude over a window | Shunt/CT tolerance/tempco, thermal gradients, AFE offset at low current |
| P (Active) | Real delivered power (V·I·cosφ) | Phase error (PF loads), sync sampling alignment, non-linear harmonics |
| PF | Phase / distortion behavior of the load | Small phase offsets, CT phase delay, RC phase shift, channel timing skew |
| Wh | Integrated energy over long time | Small bias/offset that accumulates, temperature drift, calibration stability |
Sampling behaviors that decide metering credibility
Sync sampling
Phase control
Anti-alias
Windowing
Low-current bias
- Bandwidth and anti-aliasing: uncontrolled high-frequency content folds into the band and biases RMS/power.
- Phase and channel timing: V/I misalignment directly corrupts P and PF, especially under low-PF loads.
- Synchronous capture: V and I captured in different time grids behave like an added phase error term.
- Low-current behavior: offset and noise dominate; “stable” numbers can still integrate into Wh drift.
Accuracy budget tree (ranked by typical contribution)
| Budget block | How error enters | Fast verification signal |
|---|---|---|
| Sensor tolerance & tempco (Shunt/CT) | Gain changes with tolerance, heating, and mounting stress | Temperature sweep → slope of Irms/P vs sensor temperature |
| Phase error (PF-sensitive) | RC phase shift, CT phase delay, sampling skew | Vrms/Irms OK but P/PF wrong; load change causes step in error |
| AFE/ADC gain & offset drift | Gain drift shifts RMS; offset dominates at low current | Low-current points drift; “zero-load” bias affects Wh over time |
| PCB parasitics & thermal gradient | High di/dt coupling, Kelvin errors, local heating | Switching moments correlate with sample spikes; hot-spot maps match error |
| Calibration & production consistency | Coefficient stability, fixture repeatability, write/retain integrity | Unit-to-unit scatter; repeated calibrations produce different coefficients |
Boundary reminder: this page focuses on engineering-achievable accuracy and validation method.
Revenue-grade regulations, polyphase systems, and PLC metering stacks are intentionally excluded.
Figure F3 — Accuracy budget map: measurement chain + ranked error blocks
H2-4. Current Sensing Choice: Shunt vs CT (Outlet-Level)
The current-sensing method sets the dominant error terms in the budget: heat and common-mode sensitivity (shunt) versus phase behavior and low-current accuracy (CT). Selection must be requirement-driven, not preference-driven.
Comparison matrix (plug-level reality)
| Dimension | Shunt (Kelvin) | CT (small ring / board CT) |
|---|---|---|
| Cost / size | Low cost, compact footprint | Higher cost/volume, mechanical constraints |
| Isolation | Not isolated (measurement rides on HV domain) | Natural isolation between primary current and secondary |
| Heat / drift | Self-heating creates tempco + gradients | Low insertion loss; drift dominated by ratio, burden, and core behavior |
| Phase behavior | RC/AFE timing dominates; can be stable if layout is controlled | Phase delay can be significant at low frequency and small current |
| Low-current accuracy | Offset/noise can dominate; careful AFE required | Magnetizing current + burden choice can degrade small-signal fidelity |
| Surge / inrush | Thermal and copper stress; voltage drop increases at high current | Core saturation can distort peaks; recovery impacts computed power |
| Layout sensitivity | Very sensitive: Kelvin routing + return path control | More tolerant electrically, but sensitive mechanically and to burden placement |
Selection criteria (practical “decision drivers”)
Current range
Allowed drop / heat
Space
Isolation need
PF / non-linear loads
- Allowed voltage drop and heating: tight thermal headroom pushes away from shunt-heavy loss at high current.
- Isolation boundary: designs that must keep measurement away from HV-domain noise benefit from CT’s natural isolation.
- PF and non-linear loads: if P/PF must stay correct across SMPS/LED/motor loads, phase terms must be budgeted explicitly.
- Small-current credibility: standby currents expose offset/noise (shunt) or magnetizing/burden effects (CT).
Placement & “avoid-the-common-fail” pointers
| Method | Placement rule (what to do) | Common failure mode (what to avoid) |
|---|---|---|
| Shunt | Kelvin sense to AFE; keep sense loop away from high di/dt switching loop; isolate from hot parts | Sense lines sharing load current return; local copper heating creates gradient → “warm drift” in Irms/Wh |
| CT | Burden resistor close to CT secondary; keep secondary loop tight; characterize phase across load types | Improper burden causes low-current nonlinearity; core saturation during inrush distorts peaks and phase |
Out-of-scope reminder: Rogowski coils, polyphase CT systems, and revenue-grade metering transformers belong to a different page scope.
Figure F4 — Shunt vs CT: coupling differences (heat, phase, isolation, layout)
H2-5. Voltage Sampling & Phase: Low PF Loads Make “Phase Errors Explode”
In smart plugs and single-device submeters, Vrms/Irms can look correct while P, PF, and Wh drift under rectifier loads or inductive loads. The common root cause is phase error created by the voltage divider/RC network, current-channel delay, and mismatched sampling timing.
Three load “waveform archetypes” (text descriptions + key pitfalls)
| Load archetype | Text waveform description | Key pitfalls to watch |
|---|---|---|
| Near-resistive (heater) |
Current roughly follows voltage; smooth sinusoid-like behavior. | RC phase shift exists, but sensitivity is moderate; errors are often dominated by gain/tempco rather than phase. |
| Rectifier + bulk cap (SMPS/LED) |
Current flows in narrow peaks near voltage crest; rich harmonics. | Anti-alias and sampling window strongly affect results; “50/60 Hz phase OK” does not guarantee correct power under harmonics. |
| Inductive (motor) |
Current lags voltage; PF can be low and varies with load. | Low PF makes power extremely phase-sensitive; small channel delay mismatch can create large power error. |
Where phase error comes from (and why it gets worse with harmonics)
Divider + RC
CT / AFE delay
Sync timing
Harmonic content
PF sensitivity
- Voltage divider and RC anti-alias: any RC introduces frequency-dependent phase shift; rectifier loads push energy into harmonics where the phase response differs from the 50/60 Hz assumption.
- Current-channel delay: CTs can add phase delay (frequency and amplitude dependent); shunt designs still incur delay from filters/amps and PCB return paths.
- Sampling skew: V and I must share a timing reference; asynchronous capture behaves like an added phase term and directly corrupts P and PF.
- Low PF amplifies impact: when PF is small, a tiny phase error can create a large relative error in computed power and energy accumulation.
Practical methods that close the loop
| Method | What it fixes | How to verify (minimal tooling) |
|---|---|---|
| Phase calibration | Corrects systematic phase shift from RC, CT, and front-end group delay. | Compare against a reference meter across three archetype loads; confirm P/PF stability after calibration. |
| Channel delay matching | Aligns effective V/I timing so the compute engine sees coherent samples. | Step-load or switching event: confirm no transient “power spike” caused by skew. |
| In-band consistency check | Ensures the metering chain behaves consistently over the frequency content that matters. | Use a rectifier load and vary load power; watch whether PF/P shift non-physically with identical hardware conditions. |
Boundary reminder: the goal is engineering-grade robustness for plug-level single-phase metering.
Revenue-grade compliance workflows and polyphase/PLC metering stacks are intentionally excluded.
Figure F5 — Phase error sources: divider/RC, current-channel delay, sync skew (PF-sensitive)
H2-6. Metering SoC / Metrology AFE Selection: What to Check First
A metrology device should be chosen by timing coherence, dynamic range, and calibration hooks before secondary features. Many “spec-sheet wins” fail in production when low-current stability, phase robustness, or isolation-friendly interfaces are missing.
Parameter priority list (engineering relevance order)
| Priority | What to verify | Why it matters (smart plug / submeter) |
|---|---|---|
| 1) Synchronous sampling | V/I simultaneous sampling, channel timing match, skew budget | Directly limits phase error and stabilizes P/PF under low PF and rectifier loads |
| 2) Dynamic range | Low-current noise/offset behavior and large-current headroom | Standby Wh drift and inrush saturation are common field failures |
| 3) Phase / frequency response | In-band stability under harmonics; predictable group delay | Rectifier loads push harmonics; phase stability protects power computation |
| 4) Built-in compute | RMS / P / PF / Wh; optional harmonic metrics | Reduces host workload, but only helps if calibration and timing are correct |
| 5) Calibration support | Gain/offset/phase registers, temperature compensation hooks | Enables production consistency and thermal drift control across units |
| 6) Interface & isolation fit | SPI/I²C/UART feasibility across isolators; update rate tolerance | Metering data must cross isolation cleanly without adding timing ambiguity |
Typical solution tiers (capability layering)
| Tier | Best fit | Non-negotiables |
|---|---|---|
| Entry | Basic RMS/Wh with predictable loads; PF accuracy not the top KPI | Coherent sampling timing, stable offset at low current, basic gain calibration |
| Mainstream | Mixed household loads (SMPS + resistive) with credible P/PF expectations | Sync V/I capture, phase calibration hooks, robust anti-alias + stable group delay |
| High-demand | Strict energy consistency across wide temperature and diverse non-linear loads | Low-current stability, strong phase/frequency characterization, temperature compensation hooks |
Interface boundary (scope-safe)
- Only the handoff is covered: metrology AFE/SoC exposes results via SPI/I²C/UART to a host controller or wireless SoC.
- Isolation-friendly choices: select an interface that remains stable through isolators without introducing unpredictable timing skew.
- Protocol stacks excluded: Wi-Fi/BLE/cloud protocol details belong to other pages; this chapter focuses on metrology-device selection.
Figure F6 — Metrology AFE/SoC selection map: priorities, interfaces, and tiering
H2-7. Switching Actuator: Relay vs Triac vs SSR (Zero-Cross, Inrush, Heat)
In a smart plug or plug-level submeter, the switching element is not “just a switch”. It sets the limits for inrush survival, thermal headroom, and metering stability during turn-on/turn-off events.
Decision table: load type → recommended switch choice
| Load type | Relay | Triac | SSR (MOS/triac SSR) |
|---|---|---|---|
| Resistive heater |
✔ low loss, true off, low leakage | ✔ works well if holding current is satisfied | △ ok but watch conduction loss and heat |
| Inductive fan/motor |
✔ robust if arc/life is designed for | △ can be noisy/heat; commutation depends on load | △ thermal and surge margin must be strong |
| Capacitive input inrush-heavy |
△ contact stress at turn-on; life depends on surge | △ turn-on dv/dt and heating can be limiting | △ best when surge/thermal are over-designed |
| Rectifier SMPS chargers/LED |
✔ low leakage, good off behavior | ✖/△ low-load behavior may flicker; EMI/heat risks | △ leakage can cause “ghost” effects; heat matters |
| Very low power night light |
✔ true off and stable at tiny currents | ✖ holding current + leakage side effects | ✖/△ leakage can be visible; thermal still present |
Actuator “profiles” (what must be understood before committing)
Relay
Low leakageLow lossTrue off
- Strength: minimal conduction loss; clean off-state for low-power loads.
- Limits: contact life under inrush; bounce/arc can corrupt metering around events.
- System notes: coil drive current and switching loops must not share return paths with sensing.
Triac
AC-friendlyEMI/heatHold current
- Strength: simple AC switching and compact solutions.
- Limits: low-load holding behavior; some SMPS/LED loads show flicker or poor off behavior.
- System notes: random turn-on increases dv/dt stress and can inject noise into metering.
SSR (MOS / triac SSR)
SilentLong lifeHeat/leakage
- Strength: silent, no mechanical wear; attractive for frequent switching.
- Limits: conduction loss becomes heat; off-state leakage can affect tiny loads.
- System notes: surge tolerance and thermal path define reliability more than “headline current”.
Zero-cross vs random turn-on: what changes
| Mode | Impact on inrush & stress | Impact on EMI & metering interference |
|---|---|---|
| Zero-cross | Often reduces abrupt voltage steps; can soften stress in many cases, but capacitive inrush still depends on impedance and timing. | Typically reduces high-frequency content; easier to keep switching transients out of power/energy integration windows. |
| Random turn-on | Can hit the worst-case mains phase; increases peak stress risk for capacitive/rectifier loads. | Higher dv/dt and transient energy raise coupling into sensing, requiring stronger event gating and filtering strategy. |
Metering vs switching: preventing transient contamination
- Event tagging: switching edges should generate a “switch event” flag that the metrology path can use for data qualification.
- Blanking window: exclude a short time window around turn-on/turn-off from Wh accumulation (or apply a conservative rule set).
- Timing coherence: phase and timing assumptions (H2-5/H2-6) must remain valid under switching activity and thermal rise.
- Layout rule (high-level): keep switching current return paths away from sensing return paths; prevent shared impedance injection.
Boundary reminder: this chapter focuses on plug-level actuator choice and its interaction with metering.
Detailed EMC test methods and power-supply topologies are intentionally excluded.
Figure F7 — Load-to-switch map + zero-cross choice + metering protection (blanking/event tag)
H2-8. Isolation & Low-Voltage Domain: Isolated Comms and Isolated Power Requirements
Plug-level submeters often split into a high-voltage (HV) domain and a low-voltage (LV) domain. The isolation barrier must carry data, control, and status/timing without breaking the timing assumptions used by the metrology engine.
What must cross the isolation barrier
Data
Control
Status / Timing
- Data: metering results (Vrms/Irms/P/PF/Wh) or qualified samples, depending on architecture.
- Control: switch enable/disable, reset, protective actions, and safe-state gating.
- Status/timing: zero-cross indicator, switch state feedback, fault/inrush events used for metering blanking windows.
Isolation communication options (use-case boundaries)
| Option | Best fit | Boundary notes |
|---|---|---|
| Digital isolator | SPI / I²C / UART handoff of metering results and control signals | Keep timing predictable; avoid adding “unknown skew” that undermines phase coherence. |
| Isolated amplifier | Analog quantity across the barrier (rare in compact smart plugs) | Increases system complexity; use only when architecture requires analog-domain separation. |
| Isolated ADC | Digitize across the barrier or export digitized streams | Architecture-impacting choice; ensure sync sampling and phase calibration strategy still holds. |
Isolated power: define requirements (no topology)
| Requirement | What to specify (engineering level) |
|---|---|
| Isolation rating | Target withstand capability and safety margin consistent with the product class; treat it as a system constraint that drives spacing and component choice. |
| Power budget | LV-domain consumption (MCU/radio/LEDs) + HV-domain needs (metering/switch drive) with headroom for worst-case temperature. |
| Noise tolerance | Ripple/edge noise that is acceptable near metrology sampling; define “keep-out” around sensing references and clocks. |
| Size & height | Volume constraints are often the limiter; specify max footprint/height early to avoid late thermal compromises. |
| Creepage / clearance | Reserve board-level distances and isolation slots; keep routing rules aligned with the intended isolation barrier. |
PCB isolation practice (high-level, scope-safe)
- Isolation slot + return paths: prevent fast edge return currents from “bridging” the barrier through parasitic paths.
- Coupling hotspots: isolator edges, switch nodes, and high dv/dt paths are the primary injection points into sensing.
- Reference integrity: keep HV sensing reference and LV logic reference from sharing unintended impedance.
Boundary reminder: this chapter defines isolation boundaries and requirement-level specs for isolated power.
Detailed converter topologies and EMC compliance procedures belong to dedicated power/EMC pages.
Figure F8 — Isolation boundary: HV vs LV domains, signals that cross, and isolated-power requirement tags
H2-9. Protection & Safety Strategy: OCP/OTP/UV, Abnormal Loads, and Common Field Failures
Protection in a smart plug is a system decision: it must distinguish start-up inrush from real overload, prevent thermal runaway in power devices, and keep energy accumulation (Wh) consistent across brownouts.
Engineering table: Abnormal → Evidence → Action
| Abnormal condition | Evidence to collect (observable) | Action (layered, scope-safe) |
|---|---|---|
| Overcurrent (OCP) inrush vs overload |
I(t) peakdurationrepetition Compare short spikes to sustained over-limit; correlate with switch event timing. |
Use time windows + segmented thresholds:
allow higher short peaks but clamp sustained overload. Apply deglitch around switching events; log reason code. |
| Overtemperature (OTP) SSR/triac/relay hotspots |
Tj proxycase/board tempdT/dt Track temperature rise rate; correlate with load current and duty cycle. |
Prefer derating (limit power) before cut-off when safe; otherwise disconnect + cooldown timer. Preserve metering integrity by flagging derate/cut events. |
| Undervoltage / Brownout mains sag |
VrailUV flagreset cause Detect early sag; track reset and partial-write risk. |
Enter freeze mode: stop Wh updates, stop NVM writes, and commit only when supply is stable. On reboot, recover the latest valid record. |
| Abnormal load behavior nonlinear/unstable |
P/PF jitterharmonic proxyevent count Look for repeated spikes aligned with switch edges or thermal rise. |
Apply event tagging + blanking windows around switching. If instability persists, escalate from derate to disconnect and log the pattern. |
| ESD / surge exposure interface level |
fault countercomm resetsensor offset Sudden offset jumps, repeated resets, or persistent comm errors after an event. |
Use tiered protection at exposed nodes (TVS/ESD diodes, series resistors, chokes if needed), keep return paths short, and log “surge suspected” events (no waveform details here). |
OCP: preventing false trips without losing safety
1) Windowing
- Short window: tolerate higher peaks (start-up inrush).
- Long window: enforce lower sustained limits (real overload).
2) Filtering & deglitch
- Reject sampling spikes around switch edges.
- Require persistence before latching a fault.
3) Segmented thresholds
- Different limits for low vs high current ranges.
- Different handling for repetitive bursts vs continuous draw.
Practical outcome: inrush events are tolerated, while sustained overload still trips quickly.
OTP: where the heat is and what to do about it
- Hotspot reality: SSR/triac conduction loss becomes heat; relay contact/coil can also drive localized heating.
- Sensor placement: a sensor near the power device protects silicon; a sensor near the enclosure protects touch safety; a sensor near metrology protects accuracy.
- Action ladder: derate (limit power) → disconnect (if risk persists) → cooldown + controlled retry or latch, always with reason codes.
Brownout: keep Wh and logs consistent (strategy only)
- Freeze early: once UV is detected, stop accumulating Wh and stop writing calibration/energy records.
- Commit safely: write only when stable, using CRC + commit marker to avoid partial records.
- Recover deterministically: on reboot, select the newest valid record (passes CRC and commit rules).
Interface-level ESD/surge: device roles only
Mains entry
- Energy absorption tier (MOV/TVS class), coordinated with fuse/limit elements.
- Keep surge return paths short and controlled.
Switch node
- Snubber / clamp role: reduce dv/dt and spike injection into sensing.
- Protect against repetitive stress that accelerates thermal aging.
Exposed low-voltage nodes
- ESD diodes + series resistance at buttons/LED/ports.
- Chokes only when cable exposure requires it (scope-safe rule).
Common field failure patterns (what shows up most)
- SSR/triac overheating: rising case temperature, increasing drift, repeated thermal trips; usually a thermal-path or conduction-loss headroom issue.
- Relay contact wear: higher contact resistance over time, heat near relay, intermittent behavior near turn-on; often worsened by inrush-heavy loads.
- Brownout corruption symptoms: Wh jumps backward/forward after resets; indicates insufficient commit discipline in energy record updates.
Boundary reminder: protection is defined at plug-level with actionable strategy.
Detailed EMC waveforms, standard clauses, and backup power design are excluded.
Figure F9 — Protection ladder: abnormal → evidence → action (fast cut / derate / freeze / log)
H2-10. Calibration & Production Consistency: From “One Unit” to “Every Unit”
A metering chain is not “accurate by parts selection alone”. Accuracy at scale requires a production workflow: controlled stimulus, sufficient capture time, stable coefficient write/verify, and traceable records that explain drift in the field.
Calibration types (what gets corrected)
Offset
Gain
Phase
Temp hook
- Offset: bring near-zero readings to a stable baseline; prevents “no-load is not zero” symptoms.
- Gain: correct proportional error; use at least two current points when possible (low and near rated).
- Phase: correct V/I channel delay mismatch; critical for low PF and nonlinear loads where small phase error becomes large power error.
- Temperature hook: store calibration temperature and allow coefficient adjustment or validation across temperature (principle only).
Production strategy: controlled input → capture → write → verify → trace
| Step | Engineering requirements |
|---|---|
| Fixture stimulus | Use repeatable sources/loads and stable connection. Prioritize repeatability and time stability to reduce false yield loss. |
| Capture time | Short captures for screening, longer captures for coefficient derivation. Ensure enough cycles to average noise and avoid aliasing effects. |
| Compute coefficients | Derive offset/gain/phase consistently. Use a minimal point set that achieves the required error budget for the target load mix. |
| Write + verify | Write with CRC and commit markers. Verify by re-measurement and coefficient readback. Never accept a partial record after brownout. |
| Traceability | Store SN, lot, station, time, temp, stimulus points, and coefficient version. Ensure field returns can be tied to calibration history. |
Drift in the field: common sources and how to make it diagnosable
Thermal aging
- Heat cycles change device parameters and contact behavior over time.
- Track temperature history and relate drift to temperature exposure.
Shunt drift
- Resistance value can shift with self-heating and long-term stress.
- Use low-current check points to detect baseline shifts.
Contact resistance change
- Connector/relay contact changes can create extra loss and heat.
- Correlate power loss anomalies with temperature rise and switching count.
Calibration data storage: lifetime + brownout consistency (principles)
- Wear-aware updates: avoid rewriting the same NVM page repeatedly; rotate records or use staged commits.
- A/B records: keep two copies, each with version + CRC. Only one record is marked “committed”.
- Deterministic recovery: on boot, pick the newest record that passes CRC and commit rules; otherwise fall back to the last valid record.
Boundary reminder: coefficient storage is about reliability and traceability.
Security chains (signing/encryption/rollback) are handled in the dedicated Secure OTA module page.
Figure F10 — Production calibration pipeline: stimulus → capture → compute → write/verify → trace
H2-11 · Validation & Test Plan: prove it won’t fail on real loads
A smart plug/submeter is “done” only when accuracy, switching robustness, and thermal/protection behavior stay consistent across nonlinear loads, PF extremes, and frequent on/off events.
Engineering framing: use a matrix (coverage) + defined pass/fail metrics (evidence) + a “switch-edge corruption” experiment (coupling proof). Avoid “one-load, one-temperature” confidence.
Test matrix (Load × Current points × PF/Waveform × Temperature × Switching)
| Load family | Current points | PF / waveform stress | Temp points | Key observations |
|---|---|---|---|---|
| Resistive (R) heater / lamp |
standby-ish low I mid I (typical) near rated I |
PF ≈ 1 baseline low harmonic content |
ambient baseline hot steady-state |
P error & Wh drift baseline; linearity vs I; temperature coefficient of gain/offset |
| SMPS rectifier + bulk cap |
very low I (sleep) mid I (charging) startup inrush |
PF low-ish non-sinusoidal current |
ambient hot steady-state |
Phase sensitivity (PF loads); anti-alias RC impact; inrush vs false OCP; switch-edge sample corruption |
| Motor/Fan inductive |
rated running I startup peak repeated starts |
PF varies with speed/load commutation noise |
ambient hot (enclosure) |
OCP discrimination (real overload vs start surge); relay arcing vs triac commutation; thermal rise near switch |
| LED Driver dimming/low-hold |
low I sustain mid I pulses frequent toggles |
high crest factor triac compatibility risk |
ambient hot steady-state |
Triac holding current issues; SSR leakage visibility; PF error under distorted waveforms; nuisance trips |
Pass/fail metrics (define before testing)
- Power error (P): compare against a reference analyzer over a defined stable window (avoid counting switch-edge transients).
- Energy error (Wh): long-run integration (minutes to hours) to expose drift, temperature dependence, and rounding/accumulation bias.
- PF error: validate under low PF and distorted current; small phase mismatch can dominate error.
- Thermal rise & hotspots: record switch-area temperature and enclosure hot spots; correlate with accuracy drift and protection triggers.
- Nuisance trip rate: count false OCP/OTP/UV events per N switching cycles and per hour of steady operation.
Switch-edge corruption check (Pre / Edge / Post windows)
This experiment proves whether switching transients are polluting metrology (or falsely triggering protection logic).
- Define three windows: Pre (stable before toggle), Edge (around turn-on/turn-off), Post (stable after toggle).
- Run repeated toggles (e.g., 1000 cycles) at representative loads: SMPS + motor + LED driver.
- Compare statistics: P/PF/Irms distributions in Pre vs Post; Edge window should be excluded from Wh accumulation (or heavily de-weighted).
- Protection sanity: verify OCP/OTP decisions are based on validated windows (not edge spikes), with event counters for traceability.
Instrumentation tip: add a “reference tap” (test pads) for V-sense and I-sense so phase/latency checks can be repeated during EVT/DVT without rework.
Thermal tip: log switch-area temperature vs Wh drift. If drift tracks switch temperature rather than ambient, layout/heat coupling is the root cause.
Example parts (MPN examples) that commonly appear in validation builds
These MPNs are examples for BOM discussion and test coverage planning; final selection must match voltage/current, insulation, and safety requirements.
Metrology IC: ADE7953
Metrology IC: STPM01
Meter/Monitor IC: ATM90E26-YU-R
Power monitor IC: MCP39F501-E/MQ
Digital isolator: ISO7721
Digital isolator: ADuM1201
Relay: Omron G5Q-1A
Triac: BTA16-600B
Optotriac (ZC): MOC3063M
Shunt series: Vishay WSLS2512
NTC inrush: EPCOS/TDK B57236S…
MOV varistor: EPCOS S14K275
Figure H2-11 — Validation coverage map (loads → stresses → proof)
H2-12 · Metering + Switching + Isolation in One View
Goal: a 10-second architecture read. The diagram highlights the three couplings that most often cause field failures: phase error under PF loads, switch-edge sample corruption, and SSR leakage/heat.
Three critical callouts:
Phase error hurts PF loads
Switch edge corrupts samples
SSR leakage & heat matter
Example building blocks (MPN examples)
| Block | Typical role | MPN examples (not exhaustive) |
|---|---|---|
| Metrology IC / SoC | sync V/I sampling, RMS/P/PF/Wh engine, phase calibration registers | ADE7953 · STPM01 · ATM90E26-YU-R · MCP39F501-E/MQ |
| Isolation comms | SPI/UART/control across barrier (basic or reinforced depends on design) | ISO7721 · ADuM1201 |
| Relay path | low loss + low leakage switching (life/arcing must be validated) | Omron G5Q-1A (family) |
| Triac / optotriac path | AC static switching; zero-cross option reduces EMI but affects control timing | BTA16-600B · MOC3063M (zero-cross driver) |
| Shunt sensing | compact, linear current sense; Kelvin routing + thermal management | Vishay WSLS2512 series (example) |
| Input surge / inrush | inrush limiting + surge clamp (select per mains and safety targets) | TDK/EPCOS B57236S… (NTC) · EPCOS S14K275 (MOV) |
Figure H2-12 — Smart Plug “Metering + Switch + Isolation + Protection” (board-level)
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H2-13 · FAQs (Submeter / Smart Plug)
All answers stay inside this page: metrology chain, switching devices, isolation comms, protection policy, calibration, and validation. No polyphase/AMI/PLC, no OTA security chain details, no PTP, no backup architecture, no EMC standard deep-dive.
→ H2-3 / H2-6 Why do readings “jump” or show negative power at ultra-low standby current?
At very low current, offset + noise can dominate the signal, and sign errors appear when voltage/current phase or polarity is inconsistent. First evidence: check
Irms near zero, DC offset after digital filtering, and the sign convention for V/I channels. Fast test: short the input (or use a small resistive load) to verify stable zero and correct polarity before chasing “accuracy.”
- Typical suspects: front-end offset drift, too-short averaging window, miswired shunt Kelvin sense, sign-inverted channel.
→ H2-5 / H2-3 When PF is very low, power error suddenly grows—check phase first or amplitude first?
For low PF or distorted loads, phase error usually dominates because active power is the small difference between two large apparent components. First evidence: compare PF error vs P error; if PF shifts while Vrms/Irms look normal, phase/latency mismatch is primary. Fast isolation: validate with a pure resistive load (PF≈1). If accuracy recovers there, focus on RC anti-alias phase, CT delay, and channel alignment.
→ H2-7 / H2-11 After changing the relay, metering got worse—contact resistance change or switching noise corrupting samples?
Separate steady resistance shift from edge transient corruption. First evidence: compare P/Wh drift in stable ON state vs errors concentrated around toggles. If steady ON shifts, contact resistance and thermal coupling change the effective series path (and sometimes the shunt’s thermal gradient). If toggling causes spikes, apply the Pre/Edge/Post window method and exclude Edge samples from Wh accumulation. Example relay family: Omron
G5Q.
→ H2-7 / H2-9 SSR is silent, but why does it run hot and still leave “voltage” on the load when OFF?
SSRs dissipate heat due to conduction loss (effective voltage drop × load current) and may leak current in OFF state, which can keep small loads faintly energized. First evidence: correlate temperature rise with load current and enclosure airflow; confirm OFF leakage with a high-impedance meter. Protection policy should treat SSR hotspots as first-class inputs for OTP derating or shutdown. For AC SSR control, optotriac drivers like
MOC3063 are common in some designs.
→ H2-7 Triac control with LED/SMPS often flickers or won’t fully turn off—what’s the usual root cause?
Many LED drivers/SMPS loads fail triac control due to holding current limits and waveform distortion: the load current may fall below the triac’s holding threshold each half cycle, causing intermittent conduction and flicker. OFF behavior can also look “not clean” due to snubber/leakage paths. First evidence: observe current near zero crossings and at low dim/low power. Triac example:
BTA16-600 class.
→ H2-7 / H2-11 Energy (Wh) “jumps” during switching—how should sampling windows or filtering be handled?
A Wh jump usually means edge transients are being integrated. First evidence: compare Wh growth rate in Pre vs Post windows; spikes clustered at on/off indicate edge inclusion. Practical strategy: define a short Edge exclusion window (or de-weight samples), then resume accumulation only after Vrms/Irms settle. Validate by repeating 1000 toggles and verifying Wh consistency. This is a validation problem first, then a DSP/window policy problem.
→ H2-4 / H2-10 A shunt seems “power-rated enough,” yet temperature drift still moves readings—why?
Power rating does not guarantee low drift. The dominant factors are TCR (temperature coefficient), thermal gradient across the shunt, and copper/PCB heat injection into Kelvin sense nodes. First evidence: drift tracking local hotspot temperature rather than ambient. Fast fix path: tighten Kelvin routing, thermally isolate the sense pair, and use temperature hooks in calibration (gain/offset vs temperature). Example low-ohmic shunt series: Vishay
WSLS.
→ H2-4 / H2-5 CT sensing looks safer, but why can low-current accuracy be worse?
At low current, CT errors rise because magnetizing current and core behavior become significant relative to signal, and phase error can increase—especially with an unfavorable burden selection. First evidence: poor linearity at the lowest current point while mid/high current looks acceptable. Fast isolation: check phase and magnitude separately using a resistive reference load, then re-evaluate burden value, saturation margin at peaks, and the metrology channel’s phase alignment.
→ H2-10 Some units in the same batch are accurate and others are not—what calibration step is most often unstable?
The most common instability is not the math—it is the calibration input repeatability and the “capture conditions.” First evidence: unit-to-unit spread that correlates with fixture contact, clamp force, or capture time. Stabilize by defining: (1) controlled reference load/source, (2) minimum settle time, (3) fixed averaging window length, (4) gain/offset/phase write + readback verification, and (5) trace fields (temperature, timestamp, operator/fixture ID).
→ H2-9 / H2-11 Over-current protection trips too often—how to tell “startup inrush” from real overload?
Distinguish by time scale and repeatability. Inrush is short and load-type specific (SMPS/motor), while overload persists. First evidence: event logs showing peak current duration and whether the trip happens only at turn-on. Practical policy: multi-segment thresholds (higher short-time limit, lower long-time limit) plus a validated sampling window that avoids switch-edge spikes. Prove it with the validation matrix at startup and steady states.
→ H2-8 / H2-9 Switching and metering look fine, but some loads reset the Wi-Fi/MCU—why?
Resets typically come from brownout or noise injection across the isolation boundary or shared ground references, not from “metering math.” First evidence: reset coinciding with load start/stop, and supply droop flags (UV/BOR) in logs. Mitigation stays at the requirement level: define brownout thresholds, add state-safe commit rules for Wh counters, and ensure isolation comms are robust to transient bursts (e.g., digital isolators like
ISO7721 class).
→ H2-11 How should a validation matrix be designed to cover the most failure-prone load combinations?
Use a minimal set that stresses the known couplings: R baseline (linearity), SMPS (PF/distortion + inrush), motor (startup + commutation), and LED driver (triac/SSR compatibility). For each, cover low/typical/rated current, ambient/hot temperature, and both steady ON and frequent toggles. Always include the Pre/Edge/Post window experiment to prove switching transients do not pollute Wh.
Note: MPN mentions above are examples for engineering discussion (metrology: ADE7953/STPM01/ATM90E26/MCP39F501; isolation: ISO7721/ADuM1201; switching: G5Q/BTA16/MOC3063; shunt series: WSLS). Final selection must meet safety, insulation, and thermal constraints of the product.
