ULP PMIC for IoT Nodes: Ultra-Low IQ Buck/LDO
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An IoT ULP PMIC is successful only when sleep current, clean domain gating, and repeatable wake sequencing all work together—low IQ alone is not enough. The practical goal is to make every “off” rail truly reach 0 V, keep retention minimal, and let PG/RESET enforce a deterministic brownout behavior so nodes wake reliably without hidden leakage.
H2-1 — What is an “ULP PMIC” in IoT: scope & boundary
Goal: provide a cite-ready definition and a clear line between what this page covers and what it does not.
Definition (45–55 words): An IoT “ULP PMIC” is a power manager built for sleep-dominant devices, where battery life is set by standby current and ultra-light-load behavior. It combines ultra-low quiescent current, efficient regulation at µA–mA loads, controllable power-domain gating, and predictable PG/RESET sequencing to enable reliable wake-up without hidden leakage paths.
“Ultra-low power” is not a single number. A design qualifies only when energy (sleep draw + light-load efficiency) and behavior (domain control + PG/RESET timing) both remain stable across temperature, battery droop, and wake bursts.
This page covers
What to measure, choose, and verify in ULP PMIC designs.
- ULP metrics: mode-specific IQ, light-load efficiency curves, mode transitions
- Power domains: always-on / retention / active and domain-gating rules
- PG/RESET: thresholds, deglitch, delay, brownout behavior (reliable wake)
- Leakage & back-powering: common paths and evidence-driven isolation
- Practical validation: correct nA/µA measurement and debug steps
This page does not cover
Handled by sibling pages under the same IoT & Edge map.
- Energy harvesting / MPPT architectures (Harvesting Front-End page)
- Backup/hold-up/supercap, eFuse/hot-swap/PMBus (Edge Power & Backup page)
- PoE PD and high-power front-ends
- Wireless protocol stacks or gateway software architectures
- Secure OTA / device identity / timing sync deep dives
Visual intent: a PMIC qualifies as “ULP” only when low sleep draw and predictable power-domain behavior hold together.
H2-2 — Where it sits: typical IoT power tree & power domains
Goal: place the PMIC into a system context so domain gating and PG/RESET decisions become concrete.
A sleep-dominant IoT node is best understood as three power domains with different “always required” rules. The ULP PMIC sits between the source and these domains, acting as a domain manager: it regulates rails, cleanly gates what can be off, and provides PG/RESET behavior that prevents partial wake or brownout loops.
Domain roles (engineering view):
- Always-on: must remain powered in deep sleep (RTC timebase, wake pins/interrupt logic, minimal housekeeping).
- Retention: keeps only the state that is cheaper or safer to preserve than to rebuild (selected RAM/registers/sensor keep-alive).
- Active: powers high-current work windows (MCU run, radio bursts, sensor conversions, I/O drivers), then returns to off.
In deep sleep (expectations)
- Only Always-on stays enabled; everything else is gated unless strictly needed.
- Rails that are “off” must be truly off (no back-power through I/O or protection diodes).
- Leakage control matters as much as PMIC IQ; a single unintended path can dominate the budget.
On wake (expectations)
- Domains come up in a defined order to avoid inrush, false boot, and reset chatter.
- PG/RESET gates MCU execution until rails are settled and stable.
- Brownout behavior returns the system to a safe state instead of “half-on” oscillation.
H2-3 — Sleep current budget: IQ vs leakage vs “accidental loads”
Goal: identify what actually consumes sleep current and turn it into a measurable budget worksheet.
Working budget equation: Isleep,total = Iq,PMIC + ΣIleak paths + ΣIpull-ups/dividers + Isensors
A low PMIC IQ does not guarantee a low system sleep current. Sleep draw typically collapses into three buckets: (1) PMIC self-consumption in the intended sleep mode, (2) leakage/back-power paths that keep “off” domains partially alive, and (3) accidental static loads such as pull-ups, dividers, LEDs, or debug interfaces. Budgeting works only when each term is paired with a verification step.
- Freeze the state: confirm the device is in the repeatable deep-sleep state (same firmware path, same pins, same wake sources).
- Stepwise isolation: gate domains one-by-one (load switch off) and record the current delta after each step.
- Prove “rail truly off”: an off-domain rail should approach 0 V; any elevated rail often indicates back-power.
- Hunt static loads: temporarily lift pull-ups/dividers/LEDs; a constant current term typically points here.
- Validate sensor states: verify sensors are in their lowest-power state (not merely “idle”).
| Term | Typical contributors | Quick verification | Common fix |
|---|---|---|---|
| Iq,PMIC (mode-specific) | PMIC sleep/standby/shutdown IQ, internal references, housekeeping blocks | Force intended PMIC mode; compare to datasheet IQ under same VIN/VOUT; confirm mode pins/registers | Select lower-IQ mode/PMIC; disable unused rails; confirm auto-mode entry conditions |
| Σ Ipull-ups/dividers | Pull-ups on I²C/GPIO, resistor dividers, always-on bias networks, indicator LEDs | Temporarily lift/disable a network; current should drop by a constant step | Increase resistance, duty-cycle sensing, gate the network with a switch, remove debug/LED in production |
| Σ Ileak paths | ESD/protection leakage, level shifter leakage, input clamp currents, cable-side leakage | Disconnect external interfaces; measure rail-to-0 V when “off”; observe temperature dependence | Lower-leakage protection, isolate interfaces in sleep, re-bias clamps, ensure off-domain pins do not exceed rails |
| Back-power (subset of leakage) | MCU I/O powering an off-domain through ESD diodes, powered peripherals feeding logic lines | Set suspect GPIOs to Hi-Z; toggle pull states; check whether an “off” rail rises above 0 V | Add series resistors, power-aware level shifting, isolate buses, enforce pin states before gating |
| Isensors | Sensor standby current, internal ADC/LDO left enabled, interrupt lines forcing partial wake | Command true deep-sleep/one-shot; verify register state; observe delta when sensor rail is gated | Use lowest-power mode, gate the sensor rail, rework interrupt/pull strategy |
1) I/O back-power
Off-domain rail is not at 0 V.
- Evidence: off-rail floats high; sleep current changes when GPIO pull state changes.
- Fix: Hi-Z pins in sleep; add isolation/series-R; power-gate level shifters.
2) Protection leakage
Leakage grows with temperature or interface bias.
- Evidence: current rises with temperature; unplugging an external cable reduces sleep draw.
- Fix: lower-leakage protection; isolate interface during sleep; re-bias clamps.
3) Dividers & pull-ups
Constant drain independent of domain gating.
- Evidence: current drop is constant when a resistor network is removed.
- Fix: increase resistance; gate the network; duty-cycle measurement windows.
4) Debug & indicators
Lab convenience becomes production drain.
- Evidence: connecting debugger increases sleep current; LEDs dominate budget.
- Fix: gate debug rails; remove indicators; add production strap options.
5) Sensor not truly asleep
“Idle” is not the lowest-power state.
- Evidence: programming deep-sleep registers reduces current; sensor rail gating causes a clear delta.
- Fix: enforce deep-sleep/one-shot; gate sensor power; refine interrupt logic/pulls.
Visual intent: sleep current becomes controllable when each term is isolated and verified with a repeatable step.
H2-4 — Buck/LDO at ultra-light load: efficiency mechanisms that matter
Goal: explain why light-load efficiency can collapse and how mode behavior (PFM/PSM/burst) decides real battery life.
At ultra-light load, a converter’s fixed overhead can dominate. The output power is tiny, while switching events, gate driving, control circuitry, and reverse-current behavior remain present. That is why a “high peak efficiency” number is rarely predictive for sleep-dominant IoT nodes. The decision must be made from the efficiency curve in the µA–mA region and the converter’s mode transition behavior.
These modes reduce unnecessary switching activity when the load is small. The trade is that ripple/noise and transient behavior can change at the mode boundaries. For ULP designs, the most important question is not “which mode is used,” but whether mode transitions are predictable and do not create false resets, wake glitches, or measurement confusion.
- Switching loss: energy spent every time the switch toggles; becomes dominant when load power is small.
- Gate-charge loss: charging/discharging MOSFET gates; often tied to switching frequency and driver choices.
- Control overhead: controller/reference/driver housekeeping current; a “fixed cost” in many designs.
- Reverse current: unwanted backflow (often linked to synchronous rectification or light-load conduction behavior).
When a buck tends to win
Only if µA–mA behavior is strong.
- High efficiency in the target light-load band (not just at peak load).
- Reverse current is controlled; mode transitions are stable.
- Ripple/noise does not disturb the node’s low-power sensing or wake logic.
When an LDO tends to win
When fixed overhead dominates.
- Load spends most time in very low current where buck overhead cannot be reduced enough.
- Output stability (no mode boundaries) is preferred for predictable behavior.
- Voltage headroom is acceptable; LDO dissipation does not dominate the budget.
- Efficiency vs load in the µA–mA region, with clear indication of operating modes.
- Mode transition points (where PFM ↔ PWM or burst ↔ PWM happens) and whether forced modes exist.
- Reverse current behavior in light load (especially with synchronous rectification).
- Regulation/ripple at very light load; verify that the rail remains inside system limits.
- Quiescent/housekeeping current in the exact mode used during sleep (not an unrelated test condition).
Practical use: choose by µA–mA efficiency and transition behavior; fixed overhead terms define light-load performance.
H2-5 — Ultra-low-IQ LDO: IQ vs PSRR vs noise trade-offs
Goal: avoid “IQ-only” selection mistakes by linking static savings to dynamic rail behavior (PSRR, noise, and transients).
An ultra-low-IQ LDO is not “always better.” Lower static current often comes with reduced dynamic margin: PSRR can drop at relevant frequencies, output noise can rise, and load-step recovery can slow. In sleep-dominant IoT nodes, bursty loads (e.g., radio activity) can amplify these trade-offs into real system cost: rail dips, PG/RESET chatter, repeated retries, and unintended wake/restart cycles.
- PSRR (frequency-dependent): lower loop bandwidth/drive headroom can weaken suppression, especially outside low-frequency points.
- Noise: lower bias/optimization can increase output noise or worsen integrated noise without adequate filtering paths.
- Transient response: slower response and deeper dip during burst load steps can propagate into PG/RESET instability.
Static & operating points
Confirm the exact mode/conditions.
- IQ condition match: enable state, VIN/VOUT, load, and temperature must match the node’s sleep state.
- Dropout/headroom: verify margin at the lowest battery point; dropout can degrade dynamic behavior.
- Enable / soft-start: avoid rail shocks that can trip downstream monitors.
Dynamic behavior
Prevent hidden system-level penalties.
- PSRR curve: check the band where the system is most sensitive; do not rely on a single low-frequency number.
- Noise spec: confirm integrated noise / density; use filtering options only if compatible with wake timing.
- Load-step response: evaluate dip depth and recovery time under burst-like steps.
- Apply a repeatable burst-like load step and observe Vout dip, recovery, and PG/RESET stability.
- If dynamic events cause retries/resets, the energy saved by a lower IQ can be lost to repeated wake/restart cycles.
Visual intent: lower IQ can be paid back by weaker PSRR/noise/transient margin under bursty loads.
H2-6 — Dynamic domain gating: load switches, retention rails, discharge & sequencing
Goal: power down cleanly and power up predictably—rails must truly reach 0 V when off, and sequencing must prevent brownout loops.
Domain gating is the practical difference between a low-IQ design that works on the bench and one that works in the field. A gated domain must be truly off (rail near 0 V, no back-powering) and predictably on (soft-start and sequencing aligned with PG/RESET). Retention rails exist to preserve only minimal state (RTC and small keep-alives) without turning sleep into constant drain.
Building blocks
What must exist in a controllable gating design.
- Load switch / power gate: controlled rail on/off for an active domain.
- Soft-start / slew control: limits inrush and reduces input droop.
- Active discharge: pulls an off rail toward 0 V to avoid floating “half-on” rails.
- PG/RESET: prevents partial boot; releases execution only after rails are stable.
Retention boundary
Keep only what is worth keeping.
- Allowed: RTC, wake logic, small retention RAM/registers.
- Avoid: bursty/high-current domains placed in retention by convenience.
- Rule: retention current is a constant term in the sleep budget—treat it as “always paid.”
- Rail truly goes to 0 V: an off-domain rail should not remain elevated or floating.
- No back-powering: off-domain pins must not be fed through GPIO clamps/ESD paths.
- No phantom behavior: avoid PG/RESET chatter, false interrupts, or bus “half-alive” states.
OFF checklist (power-down cleanly)
Prevent back-power before cutting power.
- Set cross-domain GPIOs to Hi-Z or a safe state (no forced high into an off rail).
- Disable interface pull-ups that can feed an off domain (or move them to always-on with isolation).
- Turn off the load switch; enable active discharge if available.
- Verify: off rail approaches 0 V and sleep current drops by the expected step.
ON checklist (power-up predictably)
Make rails stable before logic runs.
- Bring up always-on/retention first; then enable active domains in a defined order.
- Use soft-start to limit inrush and prevent input droop / UVLO loops.
- Gate MCU execution: hold RESET until PG is stable (with deglitch/delay).
- If brownout occurs, return to a safe state rather than repeated on/off oscillation.
- Off rail “floats high”: evidence is rail not near 0 V; fix by active discharge and removing back-power sources.
- I/O clamp back-power: evidence is sleep current changes when GPIO state changes; fix by Hi-Z + isolation/series-R.
- Peripheral powered from I/O: evidence is bus stuck/phantom interrupts; fix by isolating lines and sequencing pins before gating.
Visual intent: clean gating requires discharge to 0 V and preventing clamp-based back-power through GPIO/interface lines.
H2-7 — PG/RESET done right: thresholds, delays, deglitch, and brownout behavior
Goal: stop intermittent boot failures and reset chatter by defining how rails, PG, RESET, and EN must behave across wake and brownout.
PG and RESET are not “status indicators.” They are a hard gate that binds rail stability to system execution. If thresholds, hysteresis, deglitch, and delays are mis-tuned, short dips and ramp variations can turn into intermittent boot failures, repeated resets, and “half-awake” behavior under brownout.
- Define a stable window: release RESET only after the main rail is above its valid region and remains stable for a fixed window.
- Use deglitch on PG: short dips during bursts must not toggle PG if the rail remains functionally valid.
- Add hysteresis: avoid PG oscillation at the threshold boundary during ramp or droop.
- Delay after threshold: “crossing the threshold” is not the same as “ready to run”—apply a deliberate delay or internal timer.
- Brownout must be decisive: if the rail enters a brownout/UVLO region, PG must drop and RESET must assert to force a clean hold state.
- Avoid oscillation loops: prevent repeated enable-on/off cycles near UVLO; require a recovery window before releasing RESET again.
- Clarify division of labor: PG/RESET gate system-level readiness; MCU BOR protects the core; watchdog addresses run-time lockups.
- Verify with correlated traces: validate rails + PG + RESET on one timeline; do not tune by single-signal observation.
External RC (when it helps)
Simple, but must match real ramps and temperature.
- Useful for a minimal delay if the rail ramp is predictable.
- Risk: component tolerance and temperature drift can make “sometimes boot” failures.
- Must not replace proper PG deglitch/hysteresis when bursts exist.
PMIC internal timing (preferred when available)
More deterministic gating and recovery behavior.
- Supports explicit PG delay, deglitch, and coordinated sequencing.
- Enables brownout recovery rules (hold-off + stable window before release).
- Reduces dependence on external tolerances for critical timing.
- Enter brownout: PG drops and RESET asserts to force a clean hold state (no partial execution).
- During brownout: keep RESET asserted; avoid repeated release/reattach cycles.
- Recover: wait for rails to re-stabilize, then apply a recovery window before releasing RESET.
Visual intent: PG ignores short dips via deglitch, RESET releases only after a stable window, and brownout forces a clean hold state.
H2-8 — How to measure nA/µA correctly: instrumentation & test traps
Goal: prevent measurement setups from changing the system state (burden voltage, sampling, and burst currents).
Ultra-low current measurement fails most often because the instrument changes the device under test. A series meter can introduce burden voltage, sampling can hide or invent “average” values, and burst currents can push the system into brownout without being obvious in slow readouts. Reliable numbers require a repeatable sleep state and at least one cross-check method.
- Lock a repeatable sleep state: confirm the same firmware path, same wake sources, same domain gates; repeat 3 times until results match.
- Observe rail voltage first: verify the main rail stays in the valid region; any sag indicates the setup is altering behavior.
- Choose range and sampling intentionally: avoid auto-ranging during critical transitions; set a known integration window.
- Measure both average and burst: use a long window for average, and a short capture for burst/peaks.
- Use domain step-down testing: gate domains one-by-one and record current deltas to isolate leakage vs accidental loads.
- Cross-check with a second method: confirm the conclusion with another technique (e.g., shunt+diff sense or a probe).
| Trap | Typical symptom | Root cause | Fix / validation |
|---|---|---|---|
| Series DMM in supply path | Sleep current looks “worse,” boot becomes intermittent | Burden voltage and series impedance droop VIN during bursts | Use shunt+diff sense or a probe; verify rail voltage does not sag in the same scenario |
| Auto-ranging during transitions | Readout jumps, false peaks/valleys | Range switching changes integration window and effective sampling | Fix range and sample window; log raw data over a stable interval |
| Only “average” measured | Battery life estimate is wrong | Burst peaks are hidden by slow sampling/integration | Capture burst separately (short window) and combine with long-window average for energy accounting |
| Sleep state not repeatable | Every run is different | Domains and peripherals not consistently gated; wake sources vary | Prove repeatability first; then apply domain step-down to isolate deltas |
| Wiring / ground coupling | Rails “look noisy,” false resets appear | Measurement loop injects noise or adds parasitic drop | Short leads, solid ground reference, verify with a second method to confirm behavior |
Visual intent: measure both average and burst with a method that does not force rail droop via burden voltage.
H2-9 — Debug playbook: sleep current too high (top causes → proofs → fixes)
Goal: build the shortest evidence chain from “µA is too high” to a proven root cause and a repeatable fix.
“High sleep current” is often not a PMIC problem. The fastest path is to prove (1) the device is truly in a repeatable sleep state, (2) gated rails really go to 0 V without back-powering, and (3) accidental loads are not dominating the budget. Use delta tests (change one thing, measure the current step) to avoid guesswork.
- Repeatability: run the same sleep entry three times; the current should land on the same plateau.
- Off-rail = 0 V: measure each gated rail after shutdown; a floating rail indicates leakage or back-power.
- ΔI by isolation: disconnect one interface or disable one domain and record the current step (delta method).
| Symptom | Quick test | Expected evidence | Fix (most effective first) |
|---|---|---|---|
| Current never settles no stable sleep plateau |
Confirm sleep entry repeatability; observe wake pins / interrupts; check if clocks/EN are still active. | Current shows continuous activity-like variation; GPIOs are not in safe state; domains remain enabled. | Enforce a deterministic sleep state; gate peripherals consistently; set cross-domain GPIO to Hi-Z/safe states before gating. |
| Off domain rail stays above 0 V phantom power |
Measure the “off” rail voltage; toggle suspect GPIO to Hi-Z; disconnect one interface (I²C/SPI/UART) at a time. | Rail floats at hundreds of mV to volts; current changes immediately when a line is disconnected or set to Hi-Z. | Prevent back-power (Hi-Z before off); add isolation/series-R where needed; enable active discharge; adjust sequencing to stop clamp feeding. |
| Current is a stable constant term doesn’t look bursty |
Temporarily remove/disable dividers, pull-ups, indicator LEDs; estimate I = V/R and compare with ΔI. | Measured ΔI matches resistor-based estimate; current stays flat rather than peaky. | Increase resistor values; gate dividers/pull-ups; move pull-ups to controlled always-on rails; gate LEDs (short pulse only). |
| Sleep current is high only in “sleep” mode mode not actually entered |
Verify PMIC mode (mode pin / status / register); compare current across standby/sleep/shutdown paths. | Mode indicator remains active; current does not step down as expected when “sleep” is commanded. | Correct mode pin/register configuration; satisfy entry conditions (disable unneeded rails, confirm load thresholds and timers). |
| Unexpected consumption under light load low-load behavior dominates |
Observe output ripple and switch activity at µA–mA; compare auto-mode vs forced mode; test a temporary minimum load. | Frequent burst switching or irregular ripple at low load; current improves when mode behavior is changed. | Tune mode behavior (auto/PFM/PSM/FPWM as appropriate); optimize output caps; consider rail partitioning (buck for burst rails, LDO for quiet rails). |
Visual intent: prove repeatable sleep, prove off-rail is 0 V, then isolate by ΔI steps in the fastest order.
H2-10 — Selection checklist: the few specs that decide success
Goal: reduce datasheet noise into the small set of parameters that determine sleep current, wake reliability, and clean domain gating.
A successful ULP PMIC selection is decided by a small number of behaviors: how low the current is in the exact intended modes, how the converter behaves at ultra-light load, whether load switches can truly shut domains to 0 V, and whether PG/RESET timing prevents reset chatter across brownout and recovery. The checklist below uses a fixed order so evaluation stays consistent across vendors.
- IQ (all modes): shutdown / standby / sleep current under the same VIN/VOUT/temperature and rail-enable conditions.
- Light-load efficiency curve: the µA–mA region + mode transition behavior (PFM/PSM/auto) matters more than peak efficiency.
- Low-load regulation: ripple, output accuracy, and any minimum on-time limitations that appear at small loads.
- Load switch quality: Rds(on), leakage, and an active discharge option to ensure off-rails actually return to 0 V.
- PG/RESET quality: accuracy, hysteresis, deglitch, delay timing, and deterministic recovery behavior after brownout.
- Start-up / inrush control: current limit, soft-start, and ramp control to prevent UVLO oscillation on weak sources.
- Protections (sleep/wake impact): UVLO/OCP/thermal thresholds and hysteresis—verify they do not chatter at boundary conditions.
| Spec that matters | Field consequence if wrong | Quick evidence to confirm |
|---|---|---|
| IQ by mode (shutdown/standby/sleep) | Sleep budget fails; “sleep” does not look like sleep; battery life misses by a constant offset | Clear current step between modes; repeatable plateau under the exact rail-enable condition |
| Light-load mode behavior + efficiency curve | Unexpected consumption at µA–mA; burst events trigger rail dips and PG chatter | Low-load ripple and switch activity correlate with current; improvements when mode is changed |
| Low-load regulation / ripple / min on-time | Quiet domains become unstable; false wake or brownout at low load | Measure Vout ripple and accuracy at the real low-load condition; confirm stability across temperature |
| Load switch leakage + discharge | Off-rail not 0 V; back-power through interfaces; sleep current higher than expected | Off-rail voltage after gating; ΔI when interfaces are disconnected or set Hi-Z |
| PG hysteresis/deglitch + reset timing | Intermittent boot failures; reset chatter; half-awake behavior during brownout | Correlated traces of rail/PG/RESET show stable window gating and decisive brownout handling |
| Soft-start / inrush control | UVLO oscillation on weak sources; repeated boot attempts and wasted energy | Input droop and repeated PG/RESET cycles during wake; improved behavior with tuned ramp limits |
| UVLO/OCP/thermal thresholds & hysteresis | Chatter near thresholds; unexpected shutdowns at low battery or cold/hot edges | Boundary testing shows deterministic enter/exit behavior with a recovery window |
Visual intent: ignore most datasheet “noise,” and focus evaluation on the small set of behaviors that decide sleep, wake, and gating success.
H2-11 — Reference architectures: 3 practical patterns for IoT nodes
Purpose: three “copyable” node-level power patterns, described only from the PMIC + power-domain management view (domain gating, rail sequencing, PG/RESET, UVLO/soft-start, and ultra-light-load behavior).
These patterns are intentionally practical: each one highlights (1) when it fits, (2) the few failure modes that most often break sleep current or wake reliability, and (3) a short validation checklist that produces repeatable evidence. Part numbers below are example BOM candidates—final selection should be confirmed with the latest datasheets and real sleep/wake measurements under the exact rail-enable conditions.
Pattern A — Coin-cell + buck/LDO + retention rail
Best for sleep-dominant sensor/beacon nodes with short wake bursts and strict average-current budgets.
- Very long sleep periods; wake actions are short and repeatable (sense → radio burst → sleep).
- Retention domain only needs RTC + minimal state (small RAM/register retention).
- Active rail can be gated to true 0 V without back-power paths.
- Brownout-reset chatter: burst load causes rail dip; PG/RESET thresholds or deglitch are too tight.
- Retention creep: “accidental loads” placed on retention rail (pull-ups/dividers/LED) dominate sleep current.
- Off-rail not 0 V: no discharge or I/O clamp paths feed gated domains.
- Sleep current lands on the same plateau across 3 repeated sleep entries.
- All gated rails measure near 0 V after off (no floating rails).
- PG/RESET stays stable during the worst burst; no “half-awake” oscillation.
- ΔI isolation steps: disabling each domain produces a clear current step consistent with the budget.
- ULP buck (light-load focused): TI TPS62740 / TPS62743; TI TPS62840 (evaluate mode behavior at µA–mA)
- ULP LDO (quiet/retention rails): TI TPS7A02; Microchip MCP1700; Analog Devices ADP160
- Load switch (domain gating): TI TPS22916 / TPS22918; TI TPS22860; Microchip MIC94063
- Reset / supervisor (ultra-low supply current): TI TPS3839; Microchip MCP100; Maxim/ADI MAX809
Tip: choose the retention rail intentionally; keep only RTC/minimal state there, and gate everything else.
Pattern B — Li-SOCl2 (high impedance) + light-load strategy
Best for industrial long-life nodes where average current is tiny, but burst power can collapse VIN.
- Primary cell with high source impedance; radio bursts are the dominant reliability risk.
- Converter must behave predictably at ultra-light load and during burst transients.
- PG/RESET must enforce a clean brownout policy (no oscillation loops).
- UVLO oscillation loop: burst drops VIN; converter restarts repeatedly; system never completes wake.
- Inrush looks like a short: soft-start/inrush control is not tuned; VIN dip deepens at wake.
- “Sleep looks fine” but wake fails: light-load optimization is good, but burst policy is not validated.
- Worst-case burst test: VIN minimum stays above UVLO enter threshold with margin.
- PG/RESET behavior is deterministic: brownout forces a clean reset hold until rails recover.
- Soft-start/ramp does not trigger repeated UVLO cycles on a weak source.
- Low-load behavior does not create excessive switching “overhead” at µA–mA.
- Buck-boost / boost candidates (evaluate burst response): TI TPS63900; TI TPS61099; Analog Devices LTC3531
- Input/load switch with controlled turn-on (helps inrush): TI TPS22965; TI TPS22916 (check slew features by variant)
- Supervisor / reset policy: TI TPS3839; Microchip MCP100; Maxim/ADI MAX16054
- ULP LDO for quiet always-on/retention: TI TPS7A02; Microchip MCP1700
Tip: prioritize UVLO hysteresis + restart policy + ramp control; verify with real burst waveforms.
Pattern C — Li-ion + multi-domain gating (radio burst + sensor)
Best for richer nodes (more sensors + radio bursts) that need repeatable sequencing and clean off-rails.
- Multiple functional domains: MCU core/I/O, sensors, and radio that are not always-on together.
- Domain gating is used to enforce a strict sleep budget while keeping fast wake behavior.
- PG/RESET and enable sequencing must be repeatable across temperature and battery edges.
- Back-power through I/O: gated sensor/radio rails are fed via GPIO clamps, keeping rails floating.
- Intermittent boot: sequencing assumptions are violated (PG/EN/RESET windows inconsistent).
- Mode transitions cause jitter: light-load behavior interacts with burst domains and triggers rail ripple.
- Every gated rail returns to ~0 V after off; confirm no phantom rails across interfaces.
- Wake sequencing is repeatable: rail → PG stable → RESET release (consistent timing window).
- ΔI step-down proves domain partitioning: each domain off yields a clear current reduction.
- Low-load ripple and burst droop are both within the PG/RESET stability window.
- IoT PMIC / multi-rail candidates (validate sleep + sequencing features): NXP PF1550; Nordic nPM1300; Renesas DA9070
- ULP buck for burst domains: TI TPS62840; TI TPS62743
- Quiet LDO for AON/retention: TI TPS7A02; Analog Devices ADP160
- Load switches for domain gating: TI TPS22916 / TPS22918; TI TPS22860; Microchip MIC94063
- Supervisor / reset (when external policy is preferred): TI TPS3839; Microchip MCP100; Maxim/ADI MAX809
Tip: treat “off rail = 0 V” as a hard requirement; prevent I/O clamp feeding before tuning anything else.
Diagram intent: show domain boundaries and control signals (EN/PG/RESET) without expanding into charging, harvesting, or backup subsystems.
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H2-12 — FAQs (long-tail entry points mapped to this page)
Each answer stays within this page scope: ultra-low-power buck/LDO behavior, domain gating (load switches), PG/RESET policy, measurement pitfalls, debug evidence chains, and selection-critical specs.
1What does “ULP PMIC” mean in IoT, and why is IQ alone not enough?
An ultra-low-power (ULP) PMIC is not just a low-IQ regulator. It must provide low current across the intended modes (shutdown/standby/sleep), predictable ultra-light-load behavior, and controllable domain gating with clean wake sequencing. If only IQ is checked, leakage paths, accidental loads, and mode-transition losses can dominate the sleep budget and break wake reliability.
2How should AON / Retention / Active domains be partitioned in an IoT power tree?
Start from the sleep state and keep the always-on (AON) domain minimal (wake sources and essential housekeeping). Retention should hold only what must survive sleep (RTC and small state), while the active domain contains burst-heavy blocks (MCU core, radios, sensors) behind load switches. The partition is correct when gated rails truly reach 0 V and no interface can back-power an “off” domain.
3How to budget sleep current quickly: IQ vs leakage vs “accidental loads”?
Use a simple sum: total sleep current equals PMIC mode current plus leakage paths plus resistive loads plus any sensors left powered. Leakage often comes from I/O protection, ESD diodes, and sensor pins; accidental loads include pull-ups, dividers, indicator LEDs, and debug headers. The fastest approach is delta testing: disable one domain or disconnect one interface and record the step change in current.
4Why can a buck waste power at µA–mA load, and what do PFM/PSM/burst modes really change?
At ultra-light load, control overhead and switching-related losses can dominate: gate charge, comparator activity, housekeeping bias, and reverse-current behavior matter more than conduction loss. PFM/PSM/burst modes reduce switching events by skipping pulses, but they also introduce mode transitions and ripple behavior that can affect sensitive rails. Selection should focus on the light-load curve and transition points, not peak efficiency.
5When does an LDO beat a buck for battery life in IoT nodes?
An LDO can win when the load is mostly in the µA–low mA range and the buck’s control overhead dominates. It also helps when a quiet rail is needed and the system can tolerate the dropout and input-voltage range. Conversely, a buck is often better for burst-heavy domains or when VIN-to-VOUT headroom is large. The deciding factor is the real duty cycle across sleep and wake, not a single “average efficiency” number.
6Ultra-low-IQ LDO trade-offs: how do IQ, PSRR, noise, and transient response interact?
Lower IQ is often achieved by reducing internal bias, which can weaken loop bandwidth, PSRR at certain frequencies, and transient response. In IoT nodes, radio bursts or fast digital edges can push the rail harder than the average current suggests. The right LDO is the one that stays stable under burst load steps while meeting noise/PSRR needs for the domain. Evaluate IQ together with load-step response and the relevant PSRR band.
7A gated rail is “off,” but voltage remains: how to prove the rail is not shut down cleanly?
Measure the gated rail after shutdown; any persistent voltage indicates leakage, floating charge, or back-power feeding. Then isolate interfaces: set related GPIOs to high-impedance before gating, disconnect I²C/SPI/UART lines, and observe current and rail voltage steps. If the rail collapses only after disconnecting a signal line, an I/O clamp path is feeding the domain. Correct by sequencing (Hi-Z first), adding series resistance/isolation, and enabling active discharge where appropriate.
8Is active discharge necessary on load switches, and what breaks if discharge is missing?
Active discharge is helpful when an off rail must quickly return to 0 V to prevent floating states, phantom powering, or undefined logic levels. Without discharge, a rail can stay partially charged through capacitors or leak paths, keeping downstream circuits in a gray zone. Symptoms include unexplained sleep current, intermittent wake failures, and false resets due to slow rail decay. Use discharge when clean off-state and repeatable sequencing are required, and verify the discharge path does not create new leakage in sleep.
9How to configure PG/RESET to avoid intermittent boot and reset chatter (thresholds, delays, deglitch)?
Set PG thresholds with margin against worst-case droop and temperature drift, then add hysteresis and a deglitch window to ignore brief dips during switching transients. Use a release delay so RESET is asserted until rails are stable for a defined time, not merely “above threshold.” Under brownout, RESET should hold firmly low until recovery is unambiguous, preventing half-awake oscillation. Coordinate the PMIC’s PG/RESET policy with MCU BOR so only one policy dominates recovery.
10Why do nA/µA measurements go wrong, and how to measure sleep current correctly?
Many DMM ranges add burden voltage, which can shift regulator modes or prevent true sleep. Burst currents can also alias into misleading averages if sampling is slow. A robust method is to first guarantee a repeatable sleep state, then measure with a low-burden setup (SMU or appropriate meter range) and capture burst behavior separately using a shunt plus scope/current probe. Segment the test: gate domains one at a time and record delta steps to separate true contributors from measurement artifacts.
11Sleep current is too high: what is the fastest debug order (causes → proofs → fixes)?
Start by proving repeatable sleep entry (stable plateau), then prove “off rail = 0 V” for every gated domain. Next, remove the most common accidental loads (dividers, pull-ups, LEDs) and use delta steps to quantify each change. After that, verify the PMIC truly entered the intended low-power mode and check light-load behavior for excessive switching overhead. This evidence-first order prevents chasing noise and quickly separates software state issues, back-power paths, and genuine PMIC-mode problems.
12Which PMIC specs decide success: how to screen quickly without drowning in datasheets?
Prioritize (1) IQ by mode under real rail-enable conditions, (2) the µA–mA efficiency curve and mode-transition behavior, (3) low-load regulation/ripple, (4) load-switch leakage plus discharge options that guarantee off rails reach 0 V, and (5) PG/RESET accuracy, hysteresis, deglitch, and brownout policy. Then check soft-start/inrush and UVLO hysteresis to avoid oscillation on weak sources. Each of these specs maps directly to field outcomes: sleep budget, wake reliability, and clean gating.
