What this page solves

This page focuses on the USB-C VBUS power path and load switch stage: where the negotiated power from the PD controller actually flows, how it is routed between sources and loads, and how it is electrically protected. The goal is to prevent dropouts, excessive heating and hard failures around the USB-C port.

The PD controller decides what voltage and current to request, but the FETs, load switches and OR-ing paths on VBUS decide how that energy moves. This page explains how to architect that stage so that direction switching, source selection and fault handling are predictable and robust.

Three critical pain points at the USB-C power path

• Direction switching (Source vs Sink vs DRP) – A single USB-C port can act as a power Source to external devices or as a Sink that accepts power from an adapter or in-car charger. The power path must cleanly change direction without momentarily shorting sources or dropping the system rails.
• OR-ing and dual inputs (adapter plus battery) – When an adapter and an internal battery coexist, the system needs a clear priority policy and a smooth handover: which source feeds the rail in each state, and how to avoid sparks, brown-outs or reverse stress when one source appears or disappears.
• Protection on VBUS (OT/OC, reverse current and reverse polarity) – USB-C VBUS can reach 20 V at several amperes, with unpredictable cables and hot-plug events. Without proper current limiting, inrush control, thermal protection, reverse blocking and reverse-polarity handling, the USB-C connector and main board are at high risk.

Typical applications that depend on a solid USB-C power path

The same set of power-path decisions appears across many designs:

• Laptops, tablets, phones and portable monitors that must charge from USB-C as a Sink, run from battery and sometimes source power back out to accessories.
• In-car USB-C chargers that face automotive transients and wiring faults while supplying high current to connected devices.
• USB-C docks and Thunderbolt docks that distribute USB-C power to multiple downstream ports and internal loads.
• Power banks and small UPS units that use a single USB-C port for both charging and discharging, requiring reliable bidirectional flow and isolation from the battery.

The explanations on this page are written for engineers who have already seen VBUS sparks, overheated MOSFETs or mysterious dropouts under plug and unplug events and want a systematic way to harden the USB-C power path.

This page is limited to the VBUS power path and protection circuitry. USB-C and PD protocol logic, including PDO tables, PPS ranges and cable identification, is covered in the USB-C PD/QC/PPS Controller topic.

System context & boundaries

At system level, the USB-C power path sits between the USB-C receptacle and the internal rails, batteries and chargers. The PD controller negotiates power over the CC pins and then drives enable, mode and current-limit settings, while the FETs and load switches in the power-path block carry the actual VBUS current.

The diagram below positions the USB-C power path in a dual-role system: it shows how the USB-C connector, PD controller, power-path FETs, system bus and battery or charger blocks are related, and highlights the specific part of the architecture covered by this page.

Roles of the main blocks

• USB-C receptacle – Brings in VBUS, GND and the CC pins from the cable and exposes the physical interface to the outside world, including ESD and surge stress.
• USB-C PD controller – Runs the USB-C / PD protocol over CC, negotiates PDOs and PPS ranges, and exposes control outputs such as enable, power-role mode and current-limit settings to the power-path stage.
• USB-C power path / load switch – Connects and disconnects VBUS, selects between adapter and battery sources, enforces direction and reverse-current rules and implements OT/OC behavior for the port.
• System bus and PoL rails – Receive regulated power from the USB-C path and feed SoCs, memory and I/O through downstream DC-DC converters and sequencers.
• Battery and charger block – Represents the local energy store and its charging path. The interaction between this block and the USB-C power path defines how charge and discharge modes are separated and how OR-ing is performed.

Relationship to other topics

The USB-C power path depends on, and feeds into, several other building blocks:

• USB-C PD/QC/PPS Controller – Selects voltage and current over CC and reports cable capabilities. For protocol selection, PDO tables, PPS behavior and cable identification, refer to the dedicated controller topic; this page assumes those decisions are already made.
• eFuse & Hot-Swap – Protects higher-level backplanes or racks that may feed multiple ports and loads. The USB-C power path behaves like a local, port-level hot-swap stage tuned to USB-C conditions, while the eFuse & Hot-Swap page addresses system-level buses.
• Multi-Rail PoL DC-DC and Power Sequencing – Once VBUS is safely delivered to an internal bus, PoL regulators create the downstream rails for the system. Their efficiency, compensation and sequencing strategies are treated in those topics; this page only treats them as loads on the USB-C power path.

The scope of this page is therefore limited to the virtual “bridge” between the USB-C port and the system rails: the FET topologies, OR-ing arrangements and protections that determine how VBUS energy flows and when it is intentionally cut off.

Core topologies: load switch vs ideal diode vs back-to-back FET

The USB-C power path on VBUS is usually built from three foundational topologies: a single high-side load switch, an ideal-diode OR-ing stage and a back-to-back MOSFET arrangement. Each one solves a different part of the problem: simple on/off control, low-loss source selection and fully bidirectional, reverse-blocking flow for dual-role ports and power banks.

Selecting the right topology for a given USB-C role is as important as choosing the correct PD profile. A sink-only accessory, a source-only charger and a dual-role laptop can share the same PD controller family but demand very different power-path structures and device ratings.

Single high-side load switch

A single high-side load switch is the simplest way to connect or disconnect VBUS. It typically integrates a MOSFET, gate driver, soft-start and basic current limiting in one device. On a USB-C port it is best suited to strictly unidirectional roles:

• Sink-only inputs – VBUS from the connector passes through the load switch to the system bus or battery charger input.
• Source-only outputs – The system bus drives VBUS through the switch when the port is allowed to source power.

Advantages include a compact BOM, simple layout and integrated features such as soft-start, inrush limiting and over-temperature protection. The main limitation is the intrinsic body diode of the MOSFET: reverse blocking is limited and typically requires a second device or additional circuitry. A single load switch therefore does not cover true dual-role or power-bank style bidirectional operation by itself.

For USB-C sink-only ports, a high-side load switch can be effective at the connector input if reverse current into the port is handled elsewhere in the architecture. For source-only ports, the same topology can gate VBUS from an upstream rail but must be rated for the full PD voltage and current.

Ideal diode and OR-ing control

Ideal-diode and OR-ing controllers replace traditional diode OR-ing with MOSFETs to minimize voltage drop and heating. They are the preferred way to combine multiple sources feeding a USB-C power path, such as an external adapter rail and an internal battery or backup rail, into a single system node.

A typical placement has one MOSFET path from the adapter rail and one from the battery or DC bus. Both feed an OR-ing node that then connects to the USB-C power path stage or directly to the system bus. The controller senses voltage and current and drives each MOSFET so that:

• The preferred source conducts with minimal drop (I × R_DS(on) instead of diode forward drop).
• The non-preferred source is isolated from backfeed and does not see reverse current.

Compared with simple diodes, ideal-diode OR-ing greatly reduces dissipation and improves runtime on USB-C systems where 3 A or 5 A currents are common. The trade-off is added IC and MOSFET cost and the need to respect controller supply sequencing. The topology is still fundamentally oriented from “source” to “OR-ing node” and is not, by itself, a fully bidirectional solution for power-bank style ports.

In USB-C designs, ideal-diode OR-ing is most useful at the boundary between the adapter rail and the battery rail. The resulting OR-ed node can then feed the USB-C power path so that adapter power is used when present and the battery takes over smoothly when the adapter is removed.

Back-to-back MOSFETs for bidirectional and reverse-blocking paths

Back-to-back MOSFETs place two FETs in series with their body diodes opposing each other. This arrangement removes the net diode in either direction and creates a controllable, low-resistance path that can conduct in both directions when enabled and block current in both directions when disabled. It is the workhorse topology for dual-role (DRP) ports and single-port power banks.

On a USB-C port, a back-to-back pair typically sits between VBUS at the connector and the internal system bus or battery rail. When the PD controller configures the port as a Sink, the pair is driven to allow current from the connector into the system; when configured as a Source, the same silicon is driven so that current flows out from the system towards the connector, subject to reverse-current limits and protections.

The benefits are clear: true bidirectional capability, strong reverse-current blocking and a single compact conduction element for both charging and discharging. The trade-offs are higher effective R_DS(on) (two FETs in series), tighter SOA and thermal constraints and more demanding gate-drive circuitry. Layout quality around these devices has a strong impact on efficiency and reliability at 20 V and 5 A.

For DRP ports and single-connector power banks, a back-to-back FET structure is usually mandatory. Ideal diode OR-ing and simple load switches can still appear elsewhere in the design, but the core path between the USB-C connector and the main energy store requires the full bidirectional and reverse-blocking behavior of the back-to-back topology.

Mapping topologies to USB-C roles

• Sink-only devices – High-side load switch at the VBUS input plus separate reverse blocking where needed.
• Source-only chargers and adapters – Load switch or ideal-diode based output stage, with strong inrush and short-circuit control.
• Adapter plus battery systems – Ideal-diode OR-ing between adapter rail and battery/DC bus, feeding a downstream USB-C power path.
• Dual-role ports and power banks – Back-to-back FETs as the primary path between the USB-C connector and the system or battery rails, often assisted by OR-ing and load switches in supporting paths.

OT/OC and short-circuit protections

USB-C VBUS can deliver tens to hundreds of watts into cables, capacitors and downstream loads. At these power levels, overcurrent, short-circuit and over-temperature protection inside the power path are not optional extras but core safety functions. The behavior of current limit, soft-start and thermal shutdown must be coordinated with the PD profile, external capacitance and line impedance.

Unlike legacy 5 V USB ports, a 20 V, 3 A or 5 A USB-C port can stress MOSFETs, connectors and copper far beyond their comfort zones in a single fault event. Protection strategy has to cover three main scenarios: hot-plug inrush into large capacitors, cable or load short circuits and sustained high-load operation that raises device temperature.

Current limiting, fold-back and short-circuit behavior

USB-C power-path and load-switch ICs usually provide a programmable current limit (ILIM). When the load tries to draw more than ILIM, the device enters a controlled mode:

• Constant current limiting – The path supplies approximately ILIM and allows VBUS or the output rail to sag until the fault is cleared.
• Fold-back limiting – At deeper overloads or near short circuit, the device reduces the current below ILIM to ease stress on the MOSFET and package.

Current limiting must be time-bounded because allowing a device to sit at a high current indefinitely will quickly exceed its safe operating area. Many USB-C power-path ICs therefore combine ILIM with an internal timer: after a programmable or fixed time at overload, the device trips and turns off the path.

A second dimension is the distinction between blanking time and true fault duration. During hot-plug events, large downstream capacitors can cause brief, benign surges that should not be treated as short circuits. A short blanking interval allows such inrush to pass while deeper, sustained overloads trigger a fault response.

After a short-circuit trip, devices typically either latch off and wait for a system intervention or automatically retry with brief test pulses. Latch-off behavior is preferred in safety-critical or rugged designs; auto-retry behavior improves user experience in consumer products but must be combined with limits on retry duty cycle to avoid repeated heating.

Soft-start and dV/dt control for inrush and EMI

Soft-start control shapes how VBUS and the downstream rail rise from 0 V to the negotiated level. A sharp step in voltage into a large capacitor bank produces very high inrush current and strong EMI. By controlling the gate slew of the MOSFET or using a dedicated dV/dt pin, the power-path device can enforce a defined voltage ramp that keeps inrush within the current-limit envelope.

A useful mental model is that inrush roughly follows C_load × dV/dt. For a given total load capacitance, selecting dV/dt such that this product stays below ILIM reduces the risk that every plug-in event immediately hits the current limit. Soft-start also reduces contact bounce sparks and helps VBUS ramps remain within USB-C timing expectations once the PD controller has enabled the path.

Over-temperature protection and safe operating area

Over-temperature (OT) protection guards against sustained overloads and ambient extremes that raise the silicon junction temperature beyond its rating. Typical power-path devices monitor their own temperature and shut off when a threshold is exceeded, then re-enable the path after cooling and hysteresis. If the design repeatedly cycles through OT and recovery under normal use, the current limit and thermal design require revision.

Safe operating area (SOA) curves provide a more complete view than static current ratings. USB-C ports may experience brief high-voltage, high-current stress during faults that must still reside inside the MOSFET SOA envelope over the corresponding time scale. ILIM, blanking and trip timing should be chosen with these curves in mind, especially at 20 V and 5 A when line inductance and cable behavior can create substantial transients.

PCB copper area, thermal vias and enclosure conditions also have a strong influence on the permissible continuous current. A device that appears adequate in a data sheet table may run significantly hotter in a compact consumer enclosure with limited airflow. Designing margin into R_DS(on), package size and copper spreading is essential for long-term reliability.

Overall, USB-C port protection should be treated as a coordinated system: ILIM, blanking, trip timing, soft-start slope, OT thresholds and retry policy must be selected together. Simply reusing old 5 V USB protection habits on a 20 V, multi-amp port is a common cause of unexpected failures.

Reverse current & reverse-polarity protection

Reverse stress on a USB-C power path falls into two related but distinct categories. Reverse current occurs when current flows in the wrong direction while polarity is still correct, for example when a higher-voltage system rail pushes energy back into VBUS or an external adapter. Reverse polarity occurs when the port pins or supply rails are wired with incorrect polarity so that devices are driven far outside their intended voltage range. Both must be treated as primary design threats.

At USB-C power levels, uncontrolled reverse paths can damage batteries, adapters and PD controllers, or leave a connector sitting at a hazardous voltage even when no cable is plugged in. Robust reverse blocking and reverse-polarity protection are therefore integral parts of the VBUS power path, not optional add-ons.

Typical reverse-current risk scenarios

Several recurring situations tend to expose reverse-current weaknesses in USB-C designs:

• External high-voltage rail feeding back into the battery or adapter – A boosted system bus at 15 V or 20 V can backfeed into a battery, another DC rail or an attached adapter if the power path only uses a single MOSFET with an exposed body diode.
• System rail backfeeding an idle USB-C port – When the system is already powered from another input, an unprotected path can elevate VBUS at the connector even with no cable present, creating unexpected voltage at the port and the risk of backfeeding any device that is later plugged in.
• Automotive and industrial miswiring – Reversed battery leads, swapped lines or incorrect harness connections can drive the USB-C front end with reversed polarity or with significantly higher than nominal voltages.

These situations are not rare corner cases. They occur during field servicing, user error and brown-out events, and must be handled gracefully by the power path instead of depending on users “doing the right thing.”

Back-to-back MOSFETs and body-diode blocking

A single high-side MOSFET can disconnect the forward path when it is turned off, but its intrinsic body diode still conducts in one direction. If the “output” side rises above the “input” side, that diode can form an unintended reverse path and backfeed current into an adapter, battery or upstream rail even while the switch appears off in the schematic.

A back-to-back MOSFET arrangement solves this problem by placing two FETs in series with opposite body-diode orientations. With the gates driven off, at least one diode is always reverse-biased regardless of the voltage direction, so there is no continuous conduction path. With the gates driven on, both FETs conduct and the pair behaves as a low-resistance, bidirectional pass element for normal operation.

Between a USB-C VBUS pin and the system bus or battery rail, a back-to-back pair is therefore the preferred way to enforce true reverse blocking. Any design in which the system rail can be higher than VBUS should treat a single MOSFET path as unsafe and favor a reverse-blocking topology instead.

Reverse-current detection and fast turn-off

Blocking reverse current purely with passive structures is not always sufficient. Many USB-C port power-path controllers add active reverse-current detection and fast turn-off so that the back-to-back FETs are switched off proactively when a reverse flow is detected. Detection is commonly implemented by monitoring the voltage across the FET pair or by sensing current direction through an internal sense element.

Once reverse current is detected beyond a small tolerance, the controller quickly discharges the gates and turns off the pair within microseconds. This reaction time is critical when PD role swaps, cable unplug events or sudden rail transients invert the expected voltage relationship. Fast turn-off protects adapters, batteries and upstream converters from being driven as unintended loads.

Reverse-polarity protection topologies

Reverse polarity is more severe than simple reverse current because the absolute polarity at the port is wrong. Common strategies for protecting the USB-C front end against reversed supply connections include:

• P-channel MOSFET reverse-polarity protection – A P-MOS device placed “backwards” in the positive rail blocks current when the supply is reversed. In the correct orientation, its body diode and gate drive allow the device to act as a low-resistance pass element. This approach is simple and compact, but R_DS(on) and V_GS limitations restrict its usefulness at full 20 V, 5 A USB-C power levels.
• Ideal-diode front ends with TVS protection – A dedicated ideal-diode controller with N-MOS devices can provide efficient forward conduction and strong reverse blocking, while a TVS array clamps ESD and surge events at the connector. This combination is common at the USB-C receptacle in many consumer products.
• Dedicated USB-C protection ICs – Some devices integrate ESD, overvoltage, reverse current blocking and reverse polarity protection in a single port protector placed between the connector and the PD controller or main power path. These devices often target conformance to USB-IF requirements and simplify layout in dense designs.

Automotive and industrial USB-C front ends usually combine a robust reverse-polarity stage at the vehicle or plant supply with a more refined USB-C specific protection stage near the connector. Separating these roles helps keep the port-protection IC within its intended voltage range while still surviving harsh external wiring conditions.

Direction switching & OR-ing use cases

Direction control and source selection are where USB-C power paths move from abstract topologies to concrete product behavior. Real systems must decide when the port is allowed to be a Sink, when it can act as a Source, which rail supplies the system at any moment and how to avoid cross-conduction between adapters, batteries and converters. This section maps the earlier topologies and protections onto three practical USB-C scenarios.

Notebook: adapter priority, battery backup and dual-role ports

Modern notebooks often accept power from a USB-C adapter and can also provide power out to external devices on one or more USB-C ports. Internally, the architecture has to juggle adapter priority, seamless switchover to battery backup and controlled use of dual-role ports for sourcing power.

• Adapter-present, port as Sink – The adapter rail feeds an ideal-diode OR-ing stage that also sees the battery rail. The OR-ed node drives the system bus. USB-C VBUS enters through a back-to-back FET path and into the charger and system rails as a Sink.
• Adapter-removed, running from battery – The OR-ing stage automatically lets the battery rail take over. If configured to do so, a USB-C port can now act as a Source by driving VBUS through the same back-to-back FET pair in the opposite direction.
• System-off states – The architecture restricts paths so that batteries are not backfeeding adapters or idle ports, while still allowing controlled battery charging if the adapter is present.

At a block level, the adapter rail and battery rail feed an ideal-diode OR-ing stage that drives the system bus. Back-to-back FETs between the system bus and each USB-C VBUS pin handle direction switching and reverse blocking for the ports. Coordinating control between the OR-ing stage, the charger and these FETs prevents situations where two sources fight each other or where system rails backfeed into adapters and cables.

Power bank: single-port charge and discharge coordination

A power bank typically uses the same USB-C connector for both charging its internal cell stack and delivering power out to external loads. The power path must therefore switch the direction of the main current flow while keeping the charger, boost or buck-boost stage and battery isolated from any unintended cross currents.

• Charge mode (Sink) – USB-C VBUS passes through a back-to-back FET pair into the charger input. The boost or buck-boost stage is off or isolated so that it cannot drive back into the charger or the port. Reverse-current blocking ensures that the charged battery does not backfeed VBUS.
• Discharge mode (Source) – The battery feeds a boost or buck-boost stage that generates the required VBUS voltage. The output of this converter drives the same back-to-back FET pair, which now conducts from system towards USB-C VBUS to power external devices.
• Bypass or pass-through modes – In some designs, the adapter may simultaneously power the external load and charge the battery. OR-ing and direction control must ensure the charger and boost stages do not drive against each other.

From a power-path standpoint, the key building block is again a back-to-back FET pair between USB-C VBUS and the internal power rail shared by the charger and boost converter. Control logic decides whether the FETs are enabled for Sink or Source operation and coordinates the charger and converter so that only one active power stage drives the rail at any time.

Automotive chargers and portable displays: source-first, still guarded

Many car chargers and portable displays primarily behave as USB-C Sources. Even without dual-role operation, they must handle harsh supply conditions, avoid backfeeding the vehicle harness and decide how to prioritize different inputs such as a barrel jack and a USB-C PD rail.

• Automotive chargers – The 12 V or 24 V vehicle supply passes through an automotive-grade front end with reverse-polarity, surge and transient protection. Downstream, a DC-DC converter generates a regulated rail that feeds the USB-C VBUS source path, often with a load switch or ideal-diode output stage.
• Portable displays – A barrel jack adapter and a USB-C PD input may both be able to power the display. An ideal-diode OR-ing stage selects the active input. The selected rail then feeds the internal system and any USB-C Source capabilities through controlled power paths.

In these designs, direction switching is simpler but OR-ing and reverse-current protection remain critical. Even a Source-only USB-C port should not allow external equipment to push current back into the vehicle harness or the primary adapter. OR-ing devices, load switches and ideal-diode controllers at the input and output sides work together to enforce these boundaries.

Key design parameters & trade-offs

A USB-C power path is not just a switch between VBUS and a system rail. It must carry 3 A or 5 A at up to 20 V, survive inrush and short-circuit events, and stay inside thermal and safe operating area limits over the full lifetime of the product. Selecting suitable ICs and FETs therefore comes down to understanding a handful of design parameters and how they trade off against efficiency, size, cost and robustness.

R_DS(on), conduction loss and temperature rise

For any MOSFET-based power path, static loss is dominated by conduction loss, P_cond ≈ I² × R_DS(on). At 5 A, a 20 mΩ FET dissipates roughly 0.5 W, whereas a 10 mΩ device dissipates about 0.25 W. That difference translates directly into junction temperature rise, enclosure temperature and how often overtemperature protection needs to step in under heavy loads.

Lower R_DS(on) is attractive for efficiency and thermal margin, but usually implies a larger die, a bigger footprint or a higher device cost. Compact designs with limited copper area may accept a moderate R_DS(on) and rely on careful current sharing and airflow, while high-power adapters and docks often invest in very low R_DS(on) devices and heavier copper to keep FET case temperatures under control.

V_DS rating and voltage margin

USB Power Delivery profiles extend VBUS up to 20 V, so the power-path devices must tolerate at least this voltage under normal operation. In practice, the design should reserve margin for cable inductance, transient overshoot and tolerance on VBUS regulation. Devices with V_DS ratings in the 24–30 V range are typically more appropriate than parts that are only marginally above 20 V.

In automotive and industrial designs, the USB-C rail may be derived from a higher upstream supply, so V_DS headroom also supports abnormal conditions such as regulator failures or miswired harnesses. The chosen power-path IC and FET pair should be validated against worst-case VBUS plus transient levels, not just nominal PD contract voltages.

SOA, thermal resistance and package

Safe operating area (SOA) curves show how much voltage, current and time a device can withstand during fault conditions such as short circuits or aggressive current limiting. The chosen ILIM setting and trip delay must be consistent with the SOA so that the FET remains inside its limits during every realistic fault event. Relying only on nominal current ratings without checking SOA can result in devices that fail during rare but severe transients.

Thermal resistance and package style determine how quickly the junction heats up and how efficiently heat can be spread into the PCB. Small WLCSP or tiny QFN packages can be attractive for space-constrained consumer devices but require solid copper planes and vias to keep temperatures in check. Larger DFN or power packages may be necessary where 5 A contracts and elevated ambient temperatures coincide. Derating curves in the datasheet should be compared against realistic board stack-ups and enclosure conditions instead of ideal test boards only.

ILIM accuracy, response time and blanking

Current-limit accuracy determines how close the protection threshold can be set to the intended load current. Overly conservative ILIM settings trip frequently during inrush or high-load starts and frustrate users, while overly generous settings let fault currents rise far enough to stress connectors, cables and power-path devices. ILIM tolerances in the datasheet, along with layout sensitivity of any sense pins, should be factored into the margin calculation.

The timing of protection is equally important. Blanking intervals help prevent mis-triggering on benign inrush events, but if the combination of blanking plus response delay is too long, a genuine short-circuit can drag the device outside its SOA. For 3 A and 5 A USB-C loads, many designs place ILIM roughly 10–30% above the expected maximum load and then tune blanking and trip delays against measured inrush waveforms and SOA limits.

ESD, surge robustness and TVS coordination

USB-C ports must withstand repeated ESD strikes and, in many use cases, small surge events at the connector. Dedicated TVS arrays and port protection ICs handle most of this stress, but their clamping behavior must be compatible with the V_DS and absolute maximum ratings of the power-path devices. Clamped voltages during IEC 61000-4-2 and related tests should stay comfortably inside the power-path IC limits, with margin for production variation and temperature.

The USB-C VBUS path is only one piece of the overall EMC strategy, which also includes AC or vehicle front-end protection covered on other pages. Splitting responsibilities between a robust upstream front end and a well coordinated USB-C TVS plus power path keeps each stage within its intended stress envelope.

Practical trade-offs when tuning a USB-C power path

• Lower R_DS(on) vs package size and cost – Very low R_DS(on) reduces loss and temperature but often demands a larger, more expensive device and more board area. Moderate R_DS(on) values may be acceptable in lower-duty USB-C ports or where ambient temperatures are modest.
• Aggressive current limiting vs inrush compatibility – Tightly clamped ILIM protects connectors and cables but can prevent displays, docks and other capacitive loads from starting cleanly. Inrush testing with real peripherals is essential before finalizing ILIM.
• Latch-off vs auto-retry behavior – Latch-off mode favors safety and diagnostics, especially in industrial and automotive environments, but requires user or system intervention for recovery. Auto-retry improves user experience for momentary faults but must be configured so that repeated retries do not overheat devices or cables.
• Highly integrated vs controller plus discrete FETs – Integrated USB-C power-path ICs simplify layout and shrink footprint, while controller-plus-FET combinations allow tailoring R_DS(on), footprint and SOA to demanding 5 A or extended-temperature use cases at the cost of higher BOM complexity.

IC categories & BOM hooks

USB-C VBUS implementations rely on several classes of ICs working together: USB-C specific power-path switches, generic ideal-diode and OR-ing controllers, current-limited load switches and port-protection devices. This section groups these ICs by function, highlights what to check in each datasheet, and then ties them back to BOM hooks that help prevent unintended substitutions during component sourcing.

USB-C power-path and dual-role switches

USB-C oriented power-path switches integrate back-to-back FETs, current limiting, thermal shutdown and reverse blocking, and often expose pins or registers that coordinate with a PD controller. Devices in this class are typically placed directly between the USB-C VBUS pin and the system bus, implementing the main high-side switch for Sink, Source or dual-role operation.

• Typical features – Integrated back-to-back MOSFETs, programmable or pin-selectable ILIM, dV/dt-controlled soft-start, OT/OC protection, reverse-current blocking and fault indication pins or registers.
• Selection focus – Continuous current rating at 20 V, effective R_DS(on), support for Sink-only, Source-only or DRP roles, gate-drive and control interface requirements, and package thermal performance.

BOM hooks for this class should explicitly note whether dual-role capability and true reverse blocking are mandatory. If telemetry is used, the BOM should flag that the selected device must expose the required current, voltage or fault information to a system MCU or PMBus controller instead of being replaced by a simpler switch.

Ideal-diode and OR-ing controllers

Ideal-diode and OR-ing controllers drive external MOSFETs to combine multiple sources such as adapters and batteries into a single system rail. They monitor voltage or current direction and actively steer the FET gates so that the preferred source supplies the load while reverse current into the other sources is blocked.

• Typical features – Drive outputs for external FETs, sense inputs for voltage or current, controlled turn-on and turn-off timing, indication of active source and sometimes basic monitoring telemetry.
• Selection focus – Supported voltage range (must safely cover 20 V VBUS plus margin), number of inputs, detection method (voltage versus current direction), switch-over behavior when both rails are valid, and the required FET characteristics.

On the BOM, OR-ing controllers are often grouped with their external MOSFETs as a functional block. Notes should capture which source has priority, what reverse-blocking performance is expected and whether the combination is qualified for adapter plus battery OR-ing in a USB-C system context.

Current-limited load switches

Current-limited load switches combine a MOSFET, current limiting, soft-start and often thermal shutdown in a compact package. They are widely used for single-direction VBUS enabling, branch rails and local port protection, and can complement a main USB-C power path or protect downstream sub-systems.

• Typical features – Integrated high-side MOSFET, fixed or resistor-set ILIM, adjustable or fixed dV/dt, OT shutdown and different fault responses such as latch-off or auto-retry.
• Selection focus – Nominal current rating, R_DS(on), ILIM range and accuracy, fault behavior, reverse blocking capabilities and whether the device is rated for the full 20 V range needed by a USB-C port.

BOM annotations should distinguish between simple on/off load switches and true current-limited devices. If the design depends on controlled inrush and defined current limiting to meet connector or cable ratings, the load switch line item should be marked “do not substitute with a non-limited switch or discrete FET.”

Port-protection ICs and TVS arrays

Port-protection ICs concentrate on the connector boundary. For VBUS, they may combine ESD protection, overvoltage clamps, surge robustness and limited reverse-polarity protection. Additional TVS arrays or discrete surge protectors can share the stress and help meet IEC system-level immunity requirements without overstressing the power-path devices.

• Typical features – Low-capacitance ESD diodes for high-speed lines, VBUS OVP, short-circuit handling, basic reverse-current blocking and sometimes integrated fault flags.
• Selection focus – Compatibility with USB 2.0 / USB 3.x / DisplayPort signaling, maximum VBUS rating and OVP clamp level, ESD and surge ratings, and how well the clamped voltage aligns with the limits of the power-path devices behind it.

BOM entries for port-protection devices should make it clear whether they are USB-C specific or generic line protectors, and whether they are intended to work in tandem with external TVS arrays. This helps avoid substitutions that compromise data-integrity or VBUS clamp performance.

Example ICs and BOM hooks for USB-C power paths

The table below lists example part numbers that are often used to implement the roles described above. They are provided as reference points only, and equivalent devices from other vendors can be used as long as they meet the same electrical, thermal and protection requirements in the design.

Design checklist

This checklist brings the USB-C power-path requirements together so that a design can be reviewed quickly before layout release. It covers interface definition, topology choice, protection settings, reverse-current handling, EMC and safety, as well as thermal and SOA verification. Each item can be mapped back to the previous sections on this page when deeper context is needed.

Interface & role definition

• ☑ The USB-C port role is clearly defined as Sink-only, Source-only or Dual-Role (DRP), and this role matches the chosen power-path IC capabilities.
• ☑ Required current level is documented: default USB-C 1.5 A / 3 A, or full USB-PD with 3 A or 5 A contracts, including cable capability.
• ☑ Intended VBUS voltage profiles (5 V / 9 V / 15 V / 20 V) are known and upstream supplies are limited accordingly, leaving margin to the power-path V_DS rating.
• ☑ Role swaps, if supported, are captured in the system requirements so that power-path direction and protection behavior remain valid for both Source and Sink modes.
• ☑ Detailed PDO tables, negotiation rules and policy decisions are covered by the USB-C PD/QC/PPS controller design and are not assumed inside the power-path devices.

Topology & power-path structure

• ☑ The path between USB-C VBUS and the system rail is clearly drawn, showing whether it uses a single-direction load switch, an ideal-diode OR-ing stage or back-to-back FETs for bidirectional operation.
• ☑ For DRP and power-bank use cases, forward direction in charge mode and discharge mode is identified, and the chosen topology supports both directions without unsafe body-diode conduction.
• ☑ Any combination of adapter and battery rails is handled by a defined OR-ing strategy using ideal-diode or OR-ing controllers instead of Schottky-only OR-ing on high-current paths.
• ☑ Source priority (adapter-first, battery-first, or last-on wins) is specified and implemented in the OR-ing controller configuration.
• ☑ The boundary between the USB-C local power path and upstream eFuse / hot-swap protection is clear, so there is no unprotected gap or redundant protection stack.

Overcurrent, short-circuit and thermal protection

• ☑ The current limit (ILIM) for the USB-C power path is set above the maximum expected load current (typically 10–30 % margin) while remaining below cable and connector ratings and any upstream supply limits.
• ☑ ILIM accuracy and tolerance are taken into account, including layout effects on sense pins, so that real trip levels stay within safe bounds.
• ☑ Blanking or soft-start intervals are tuned using measured inrush waveforms for worst-case capacitive loads, preventing nuisance trips but still cutting short-circuits quickly enough to respect FET SOA limits.
• ☑ The combination of VBUS, ILIM and trip delay is checked against datasheet SOA curves for the power-path devices, including temperature and production variation.
• ☑ Overtemperature protection is enabled where available and configured so that junction and case temperatures stay inside derating curves under continuous high-load operation.
• ☑ The fault response mode is chosen deliberately: latch-off where clear fault containment is needed, or auto-retry where user experience requires automatic recovery, with duty cycle kept safe for cables and FETs.
• ☑ Estimated conduction loss I² × R_DS(on) at 3 A and 5 A is used to verify junction temperature versus ambient and RθJA. This step can be supported by an online I²R loss and temperature rise calculator.

Reverse current and reverse-polarity protection

• ☑ Scenarios where the system rail can exceed VBUS are identified, and true reverse blocking is provided using back-to-back FETs or equivalent circuitry instead of relying on a single FET body diode.
• ☑ Reverse-current detection and fast turn-off behavior are understood for role swaps, adapter removal and devices that can back-drive through loads or other ports.
• ☑ For automotive or industrial applications, any possible harness miswiring or supply reversal is analysed and protected using appropriate reverse-polarity topologies at the vehicle or system front end.
• ☑ USB-C port-protection ICs are verified for their reverse-blocking limits so that VBUS does not unintentionally feed back into upstream rails through that device.
• ☑ BOM entries for USB-C power-path devices are marked clearly where reverse blocking or back-to-back FET behavior is mandatory, to avoid substitution with simpler load switches.

EMC, ESD and safety integration

• ☑ USB-C port-protection devices and TVS arrays are selected to meet the target IEC ESD and surge levels, with clamping voltages compatible with the absolute maximum ratings of power-path ICs and FETs.
• ☑ The division of responsibility between the USB-C protection stage and upstream AC or vehicle front ends is documented so that surge and lightning tests do not exceed the intended stress for any single element.
• ☑ VBUS trace width, copper thickness and via stitching are sized for 3 A or 5 A operation with acceptable voltage drop and temperature rise along the path.
• ☑ Creepage and clearance around VBUS structures meet the applicable safety standard for the end product class (information technology, industrial or medical), including board coating or slotting if used.
• ☑ Port-protection ICs and TVS arrays are placed close to the connector to minimize lead inductance and improve ESD and surge performance.
• ☑ Required compliance standards such as IEC/UL 62368-1 or similar are listed, and the USB-C power path is checked against their relevant clauses.

Thermal, SOA and mechanical layout

• ☑ For each power-path FET or integrated switch, conduction loss, ambient temperature, board stack-up and RθJA are combined to estimate junction temperature at 3 A and 5 A, not just at typical conditions.
• ☑ Layout uses adequate copper area, thermal vias and appropriate layer stacking under the power-path devices to spread heat away from the USB-C connector region and sensitive components.
• ☑ Short-circuit and overload points (VDS, ILIM, time) are plotted onto SOA curves for the chosen devices, and auto-retry settings ensure enough cool-down between retries to keep average dissipation within limits. This step can be supported by an SOA and fault-energy calculation tool.
• ☑ High-stress components such as back-to-back FETs and OR-ing FETs are placed where probing and rework are still possible during bring-up and field service.
• ☑ Probe points or measurement pads are available along the VBUS path so that inrush, short-circuit and thermal behavior can be measured against the design assumptions during validation.

USB-C power-path FAQs

These FAQs collect common design and debug questions around USB-C power paths, from choosing the right topology to setting current limits, validating reverse blocking and coordinating with the PD controller. Each answer links back to the deeper sections on this page for further detail.