USB-C PD/QC/PPS Controller for Smart Adapters
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This guide covers the design and selection of USB-C PD controllers, offering detailed insights on protocol compatibility, power negotiation, multi-port configurations, and advanced features such as cable authentication, fault handling, and telemetry. It helps engineers understand the critical aspects of designing systems with USB Power Delivery, ensuring efficient power management and fast-charging capabilities, while providing robust protection and compatibility across various devices and power standards.
What this USB-C PD/QC/PPS controller page solves
This page focuses on the USB-C PD/QC/PPS protocol controller as the “digital brain” that manages CC logic, fast-charge negotiation and safety limits for Type-C ports. It does not attempt to re-explain AC/DC power topologies, primary/secondary controllers or the detailed design of high-current power path FETs.
System and adapter designers need a controller that can handle USB-PD 3.1, PPS and legacy fast-charge modes while passing USB-IF compliance and safety approvals. Different end equipment such as phones, tablets, notebooks, monitors, docks and car chargers all impose unique requirements on PDO tables, startup timing, fallback behavior and fault handling.
- Fast-charge standards multiply, and each device expects its own combination of PD, PPS and legacy modes.
- Misconfigured PDO/SRC_CAP tables cause compatibility issues, poor user experience or compliance test failures.
- Cables, counterfeit adapters and role swaps can push the system into over-power, overheating or EMI problems if not handled correctly.
The focus here is how to choose an appropriate USB-C PD/QC/PPS controller, how to structure PDO and AVS/PPS tables, and how to connect the controller to other rails and protection devices so that the complete adapter behaves predictably under normal and abnormal conditions.
AC input, EMI filters, PFC, flyback/LLC stages, synchronous rectification and detailed MOSFET selection are covered in sibling pages such as AC Input & EMI Front-End, PFC (CCM/CRM/Totem-Pole), Adapter Primary Controller, USB-C Power Path / Load Switch and eFuse & Hot-Swap.
Standards and fast-charge modes map
A USB-C PD/QC/PPS controller must navigate a landscape that includes Type-C base behavior, several USB-PD generations and multiple legacy or proprietary fast-charge schemes. The mapping between these standards and the controller’s hardware and firmware features drives compatibility, certification and user experience.
Type-C base behavior: 5 V default and port roles
In the Type-C baseline, a source advertises current capability through Rp on the CC pin while a sink presents Rd. Dead-battery and dual-role scenarios require the controller to implement correct attach, detach and debounce behavior before any PD communication or voltage change happens.
This translates into requirements for accurate CC comparators, current sources for Rp, robust debounce timing and support for DFP, UFP and DRP modes where needed.
USB-PD 2.0/3.0/3.1: PDO types and power levels
USB-PD 2.0 introduced fixed PDOs at defined voltage levels, while USB-PD 3.0 added refined capabilities and PPS. USB-PD 3.1 extended power delivery into the EPR range with higher voltage levels and stricter cable and adapter requirements. The controller must support the desired PD revision, PDO types and EPR behavior for the target application.
Legacy and proprietary fast-charge schemes
Quick Charge, AFC, VOOC and similar schemes often use D+/D− line signaling, resistor detection or vendor-specific handshakes. A PD controller may integrate D+/D− control, provide hooks for companion ICs or leave this entirely to the system MCU. Choosing the correct level of integration avoids unnecessary BOM or firmware complexity.
PPS and AVS: fine-grain voltage control
PPS and AVS allow the sink to request finely stepped voltage levels to optimize charging efficiency and battery conditions. The controller must translate PPS requests into DAC outputs, PWM codes or digital commands for downstream DC-DC stages while enforcing safe limits on step size, slew rate and update frequency.
Battery aging and charge-profile design are handled at the system or BMS level. This page focuses on the controller features needed to expose PPS and AVS safely to those higher-level algorithms.
CC logic, attach/detach and role detection
The CC pins define how a USB-C port discovers cable presence, negotiates source or sink roles and enters a safe attach state before any higher-power operation. Robust CC logic in the PD controller ensures that the port behaves predictably across DFP, UFP and dual-role operation, including dead-battery and role swap scenarios.
The Type-C ecosystem relies on Rp, Rd and Ra terminations: a source advertises capability through Rp, a sink exposes Rd, and accessories use Ra. The controller monitors CC1 and CC2 voltages with internal comparators and classifies each combination into valid DFP, UFP or accessory states. In dual-role ports, CC logic also implements the toggling behavior required to discover which side becomes the active source.
Attach and detach detection require precise debounce timing. Short glitches or intermittent contact must not be treated as valid attach events, yet user-perceived latency must stay low. A well-designed PD controller offers programmable or well-characterized debounce windows and guarantees that VBUS is only enabled after CC has settled into a valid attached state. Similarly, when CC voltages fall outside valid ranges for a defined period, the controller transitions cleanly into a detached state and commands the power path to disable VBUS.
Dead-battery behavior is especially important for sinks and dual-role ports. In this condition, the device has no local supply yet must still present a valid Rd termination and accept power from an external source. Many PD controllers integrate a dead-battery support mode that powers minimal CC and VBUS control internally, brings the system up at a safe 5 V level, and then hands control to the main MCU once local supplies are stable.
- CC comparators must resolve Rp, Rd and Ra levels with enough margin to meet Type-C thresholds over voltage, temperature and tolerance.
- Internal current sources that drive Rp levels determine how accurately the source advertises 5 V current capability (Default, 1.5 A, 3 A).
- CC pins require defined over-voltage and ESD robustness to survive cable plug-in transients and layout mistakes during development.
- Dead-battery support and dual-role behavior must be aligned with the system power tree and with any external power path devices.
This section focuses on CC-level detection and role decisions inside the PD controller. Detailed PD PHY signaling, Tx/Rx waveforms and full protocol stack implementation are handled by integrated PD stacks or external MCUs and are outside the scope of this page.
Power negotiation and PDO/PPS configuration
Once CC attach and roles are established, the PD controller advertises its power capability, accepts or rejects sink requests and commands the downstream power stage to the requested voltage and current. The design of the PDO and PPS tables and their mapping to the adapter’s true AC/DC capability directly determines compatibility, efficiency and thermal behavior.
The negotiation sequence flows through a few key messages. The source announces Source_Capabilities based on a PDO table stored in internal NVM or downloaded from an MCU over I²C or SMBus. The sink selects a fixed PDO or a PPS operating point and sends a Request. The controller evaluates whether the request is within the adapter’s budget and within cable and policy limits, then issues an Accept or rejects the request. After the power stage reaches the new operating point, a PS_RDY message confirms that the negotiated voltage is stable.
PDO table design begins with realistic AC/DC capability. The maximum advertised voltage and current are derived from the flyback or LLC stage rating, worst-case input voltage, efficiency and thermal derating. Typical adapters combine a low-voltage 5 V entry for legacy loads, one or two mid-voltage entries such as 9 V or 15 V and a higher voltage entry for notebooks or docks. EPR-capable designs can extend this to 28 V or beyond, subject to E-marker and connector limits.
Compatibility requires balancing older devices that only consume 5 V or 9 V against newer devices that prefer higher voltage for lower cable losses. Ordering and shaping the PDO table influences which profiles sinks tend to choose. PPS entries add fine-grain control, typically spanning a voltage range such as 3.3 V to 21 V with defined step sizes and current limits. The controller must enforce limits on PPS update rate and voltage delta to avoid stressing the power stage or destabilising control loops.
- Total Source power budget from AC/DC, including derating for low input, high temperature and efficiency.
- Fixed PDO voltage levels and currents that cover legacy 5 V/9 V devices and higher-voltage notebooks or docks.
- PPS ranges and step sizes that match target phone and tablet requirements without exceeding power-path SOA.
- Per-port PDO tables and limits in multi-port ATX, CRPS and bench supplies, aligned with global power-management policies.
On the analog side, the controller must convert the negotiation result into a concrete command for the power stage. This may be a DAC reference for a programmable DC-DC converter, a PWM or VID code for a digitally controlled regulator, or a digital command over I²C or PMBus to a multi-rail PoL or digital PSU controller. The PD page focuses on how the controller exposes these reference or command interfaces; detailed loop compensation and output filter design for the DC-DC stages are covered in the Multi-Rail PoL and digital PSU pages.
Treat the PDO and PPS tables as a contract between the adapter power stage and every downstream device. A carefully constructed table and a capable PD controller ensure that this contract is both safe and efficient across all operating conditions.
Protections, limits and fault handling
The USB-C PD/QC/PPS controller provides an important layer of protection by deciding which power profiles are allowed, when to downgrade or refuse requests and when to command the power path into a safe state. Protocol-level limits complement the hard protection implemented by eFuse, hot-swap controllers and MOSFET power paths so that faults are handled early and predictably rather than only at the point of short-circuit.
On the protocol side, the controller enforces limits by rejecting unsafe power requests, disabling EPR levels that are not supported by the detected cable and constraining PPS voltage and current steps. If a sink requests more power than the adapter or cable can safely deliver, the controller must either reject the request or negotiate a lower PDO instead of attempting to drive the power stage beyond its budget. These decisions are based on PDO and PPS tables, E-marker information and, in multi-port systems, global power management policy from a digital PSU controller or host MCU.
Internally, the PD controller monitors VBUS and VCONN to detect over-voltage and under-voltage conditions and to supervise cable power. Simple ADCs or comparators confirm that VBUS remains within defined limits during transitions and can trigger a downgrade or shut-down sequence when thresholds are exceeded. VCONN drivers integrate current limiting and short-circuit detection so that active cables do not create uncontrolled faults on the CC lines. These measurements do not replace full current sensing and eFuse protection, but they provide early warning and policy inputs that protocol logic can use.
It is useful to separate protections into two layers. The protocol layer decides which PDOs and PPS ranges are exposed, when to accept or reject a request and when to step down to a safer profile after thermal or power budget alarms. The hardware layer resides in the USB-C power path and hot-swap devices, which handle fast short-circuit turn-off, SOA-limited current limiting and thermal shutdown. A well-designed PD controller exposes clear fault flags and control outputs so that power-path devices can cut current quickly while the protocol layer recovers and re-establishes a safe contract with the sink.
Fault handling strategies depend on application requirements. Minor or transient faults may trigger a downgrade from a high-voltage PDO to a 5 V fallback while logging an event for diagnostics. Repeated faults or severe over-current conditions may force the controller to terminate the PD session, disable VBUS through the power path and require a physical re-attach before restoring service. In multi-port USB-C supplies, the controller and host firmware should treat each port independently, using fault counters and per-port status to decide whether to isolate only the failing port or adjust power limits across all ports.
The PD controller therefore acts as a policy engine: it prevents invalid or unsafe requests at the protocol level, supervises VBUS and VCONN against simple thresholds and coordinates with the USB-C power path to enter a defined safe state and recover in a controlled way after faults.
Cable detection, E-marker and authentication
High-power USB-C systems depend on accurate cable information. Passive cables provide no digital description and therefore force conservative assumptions about allowable voltage and current. Active cables integrate an E-marker device that reports capabilities such as maximum current, voltage and data modes over the CC channel. The PD controller must interpret this information correctly before enabling EPR levels, 5 A current and advanced modes.
E-marker data typically includes advertised current rating, supported voltage range, whether the cable can operate in EPR mode, lane mapping for high-speed or four-lane operation and vendor and product identifiers. From the PD controller perspective, the most critical fields are those that bound safe power transfer. If the cable does not declare EPR capability or sufficient current rating, the controller must suppress high-voltage PDO entries and clamp current limits even if the adapter power stage could deliver more.
Cable and adapter counterfeits introduce additional risk. Incorrect or forged E-marker data may claim higher capability than the cable can actually sustain. Many PD controllers and system designs therefore combine E-marker parsing with vendor ID checks or more advanced cryptographic authentication. In basic schemes, vendor and product IDs are compared against a whitelist, and unsafe combinations trigger conservative power limits or complete rejection of high-power profiles. In higher-security designs, a dedicated secure element performs challenge–response exchanges with authenticated cables or adapters, while the PD controller exposes the necessary register hooks and I²C or SPI connections.
Design priorities differ by application. A compact phone charger may focus on PPS compatibility and basic cable checks, only enabling 5 A modes when genuine high-current cables are detected. A 140 W notebook adapter must strictly gate EPR PDOs on verified E-marker information and often uses authentication to avoid overstress with counterfeit cables. Industrial and in-vehicle USB-C ports may operate at moderate power but require robust E-marker validation, strong fallbacks and detailed event logging to support maintenance and safety reviews.
Cloud-side certificate management and fleet analytics sit above the hardware. At the port level, the PD controller’s role is to read E-marker data, participate in local authentication where used and expose clear configuration and status registers so that system firmware can decide which power modes are enabled for each cable and adapter combination.
System partitioning with adapter and power path
A USB-C PD/QC/PPS adapter is easier to scale and debug when the AC/DC power train, digital power management, PD controllers and power-path hardware are clearly partitioned. System partitioning defines which devices own overall power budget, which components execute Type-C and PD protocol and which blocks handle high-current VBUS switching and protection at each port.
The AC front-end, PFC and flyback or LLC stages convert AC input into one or more DC rails such as a 5 V auxiliary supply and a higher-voltage bus for USB-C outputs. A digital PSU controller or main MCU supervises these rails, enforces total power limits, manages fan curves and arbitrates power across multiple ports and legacy outputs. USB-C PD controllers sit at the port edge, focusing on Type-C attach, PD/QC/PPS negotiation, cable evaluation and port-level fault reporting rather than global power scheduling.
Each USB-C VBUS line typically includes a dedicated power path: back-to-back MOSFETs, eFuse or hot-swap devices and current-sense elements. This power-path hardware executes microsecond-scale short-circuit protection, SOA-limited current limiting and thermal shutdown, under high-level commands from the PD controller and digital PSU block. The PD controller therefore decides what power profile is allowed and when to enable or disable a port, while the power path enforces the decision at the electrical level.
Several common partitioning schemes are used in practice. Low-cost, single-port adapters often combine the PD controller with an integrated power path and minimal current sensing, relying on conservative PDO tables and basic thermal design. Mid-range designs use discrete N-channel MOSFETs and external current sensing per port, allowing higher power and limited multi-port sharing. High-end ATX, CRPS and bench supplies combine a digital PSU controller, multiple PD controllers and per-port power paths to deliver dynamic power sharing, prioritisation and rich telemetry across many USB-C ports.
Detailed power-path topology and protection schemes are covered in the USB-C Power Path / Load Switch page. Digital control loops, PMBus interfaces and system-level power management reside in the Digital PSU Controller section, while primary-side startup, valley switching and standby behaviour are described in the Adapter Primary Controller topic.
Interfaces, telemetry and firmware handling
A USB-C PD/QC/PPS controller is ultimately a managed peripheral: it exposes registers, interrupts and telemetry to a host MCU or digital PSU controller and relies on firmware and NVM configuration to behave correctly in production. Well-designed interfaces make it straightforward to read port status, log faults and adapt PDO and PPS tables to changing system conditions without destabilising the power train.
Most PD controllers provide I²C, SMBus or SPI for configuration and status, together with GPIO-level interrupts and power control pins. The serial interface allows firmware to load PDO and PPS tables, read the current PDO index and requested power level, examine cable information and adjust policy thresholds. GPIO pins indicate attach or detach events, fault conditions and power-good status or drive enables and discharge controls for external power-path devices, reducing latency for simple decisions.
Telemetry should at minimum cover the active PDO or PPS operating point, an estimate of delivered power, key fault codes and a summary of cable and E-marker status. Advanced devices add internal temperature readings, counters for attach and fault events and decoded E-marker capabilities. In ATX, CRPS and bench supplies, these data are often forwarded through PMBus or SCPI interfaces so that system controllers and remote monitoring software can track USB-C port usage, efficiency and stress over time.
Configuration can be stored in OTP or NVM inside the PD controller, or pushed dynamically by firmware at startup. OTP-centric designs suit fixed-function adapters where PDO and protection limits rarely change; production tools program the configuration once and verify checksum and version. Runtime-configured designs allow a host controller to derive PDO and PPS tables from live power budget, input voltage range, thermal limits and policy, and to update them after firmware changes. Hybrid schemes keep a safe default table in NVM and overlay higher-power or EPR profiles only when firmware and system status allow.
Firmware can interact with the PD controller using interrupts or periodic polling, but in both cases the device should expose a clear port-state machine, sticky fault flags and well-documented NVM workflows. Cloud monitoring and remote firmware-update frameworks build on top of these primitives; the PD controller’s responsibility is to provide reliable, structured interfaces at the port level.
Design checklist & IC role mapping
This checklist helps ensure that all key aspects of USB-C PD, QC, and PPS functionality are considered during design, and clearly maps the required ICs for each part of the system.
Protocol support & fast-charge modes
- Which PD versions are supported (PD 2.0, PD 3.0, PD 3.1)? Does the system need to support PPS/EPR?
- Does the system need to support backward compatibility with QC/BC1.2?
- Is PPS and EPR required for high-power devices (e.g., laptops)?
Port count and power sharing
- Is the design single-port or multi-port?
- Does the system require power-budget management across multiple ports?
- Should the system support DRP (Dual Role Port) functionality?
- Does the design require role swap or dead-battery support?
Cable detection and authentication
- Is E-marker reading and authentication required for active cables?
- Are vendor ID checks needed to prevent counterfeit cables and adapters?
- Does the system require advanced cryptographic authentication for secure connections?
Telemetry & fault logs
- Does the system need to upload telemetry and fault logs to the host MCU or cloud?
- What data should be included in the telemetry? (e.g., current PDO, fault codes, cable status, temperature)
The checklist ensures that all important aspects of design, such as protocol support, power-sharing strategies, cable detection, and telemetry, are accounted for early in the project.
IC Role Mapping & Typical Part Numbers
| Role | Typical Application / Power Range | Features | Representative Part Numbers |
|---|---|---|---|
| Protocol-Only PD Controller | 20W–65W, single-port adapters | Supports PD 2.0/3.0, basic PDO tables, no power path integration |
|
| PD + Integrated Power Path PMIC | 20W–100W, mobile chargers, small adapters | Integrated PD and FET, limited current sensing, basic protection |
|
| PD Controller + eFuse + External Current Sense | 65W–140W, laptop chargers, high-power adapters | Supports EPR, high-current and thermal protection, external current sensing |
|
| Multi-Port Digital PSU + Multiple PD Controllers | 100W–240W, multi-port USB-C hubs, CRPS, Bench PSU | Multiple PD controllers, advanced power-sharing, telemetry and monitoring |
|
This mapping table helps clarify the role of each component in the system, and provides part numbers for each function. It is designed to guide engineers in selecting the right ICs for their designs.
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FAQs
When should you use a PD controller with PPS/EPR, instead of a simple 5V/9V fast charge?
PD controllers with PPS/EPR are typically used for high-power devices (e.g., laptops, monitors), especially when higher voltage and current adjustments are required. PPS allows for dynamic voltage and current adjustment to provide precise charging power. EPR is used to support higher voltages (28V, 36V, 48V) to meet the charging needs of devices like laptops. Compared to simple 5V/9V fast charging, PPS/EPR provides a more flexible and efficient charging solution, especially for high-power applications.
Single-port 65W vs multi-port 140W, what are the key differences in PD controller selection?
The choice of PD controller for a single-port 65W system and a multi-port 140W system differs significantly. Single-port solutions often require higher power output and may need to integrate additional power management functions such as power limit and load balancing. Multi-port solutions require managing power distribution across multiple ports and should support power-sharing and port-level coordination, with features such as dynamic voltage regulation (PPS) and fault protection.
How do you determine if dead-battery support + built-in 5V pre-power functionality is needed?
If a device needs to start charging from a USB-C port when the battery is completely dead, it must support dead-battery mode and built-in 5V pre-power functionality. Common applications include laptops, wearable devices, and power banks. In such cases, the controller can initiate a 5V output when the battery is empty, ensuring the device can boot up and enter normal charging mode.
How should the state machine and safety policies be designed for multi-protocol compatibility (PD+QC/VOOC)?
When supporting multiple protocols like PD and QC/VOOC, a well-designed state machine is essential to handle protocol conflicts. The system should implement priority policies (e.g., PD takes precedence) and properly handle protocol switching. Safety-wise, the system should incorporate multiple protection mechanisms, such as overvoltage, overcurrent protection, and fault recovery strategies in case of protocol failure.
How do you design a reasonable PDO table for mobile phones, laptops, and displays?
When designing PDO tables for different devices, the requirements vary. For mobile phones, the PDO table should include standard 5V, 9V, 12V, and 15V levels. For laptops, the PDO table should also include 20V and possibly higher voltages to support higher power levels (45W, 65W). Displays may require 20V or higher voltages to meet the power needs. It’s important to ensure each device receives the voltage and power it requires, with appropriate current steps.
What risks arise from too fast PPS step increments, and how do controllers typically limit this?
Rapid PPS step increments can cause instability in the charging system, leading to overheating or damage to the device. To prevent this, PD controllers typically limit the rate of voltage or current change. The controller uses set step times to ensure smooth transitions between voltage or current levels, avoiding large fluctuations that could destabilize the system and damage the device.
How should fail-safe procedures be implemented when an E-marker reading error occurs in a 140W EPR solution?
In EPR solutions, when an E-marker reading error occurs, the system should enter a fail-safe mode, rejecting the cable’s power supply and notifying the user. The PD controller can validate the cable’s voltage and current capabilities to ensure safety. If an E-marker error is detected, the system should downgrade to a lower power mode or stop supplying power to prevent overvoltage or overcurrent situations.
When is cable/adapter authentication (crypto) necessary, instead of relying solely on E-marker?
When high security is required, especially in applications to prevent counterfeit charging equipment and cables, cryptographic authentication is necessary. E-marker only provides basic identification, while crypto authentication ensures the authenticity of the cable and adapter, avoiding the use of incompatible or counterfeit accessories for charging.
What are the differences between integrated power path FET and separate PD controller schemes, and what scenarios are they suitable for?
Integrated power path FET solutions are typically used in compact, cost-effective applications such as mobile chargers and car chargers. They combine the PD controller and power path FET into a single chip, reducing external components and are suitable for lower power applications. Separate PD controller solutions are used for higher power outputs (e.g., laptop chargers, multi-port adapters), where the PD controller and external FETs are separate, providing better thermal management, power distribution, and flexibility.
How can the fault log of the PD controller be aligned with the system PMBus monitoring?
To align the fault log of the PD controller with the system’s PMBus monitoring, enable fault log functionality in the PD controller to record key fault information (e.g., overcurrent, overvoltage). This data can be uploaded to the host controller or remote monitoring system via I²C or PMBus interface in real-time, allowing for centralized fault management and monitoring.
How to manage PDO/configuration versions during mass production to avoid “wrong mode” quality accidents?
In mass production, managing PDO and configuration versions is crucial by using reliable programming tools and version control systems. Specialized GUI or scripting tools can be used to burn PDO configurations into the PD controller via OTP or NVM storage, ensuring the correct version is used every time during production. Production tools should include checksum and version management to verify and prevent errors during programming.
How do USB-C PD controllers and wireless charger TX/RX collaborate on fast charge strategies?
USB-C PD controllers and wireless charging TX/RX collaborate by agreeing on power distribution and voltage regulation parameters during charging. The wireless charging system can work alongside the PD controller to ensure stable voltage and power delivery, preventing overheating and inefficiencies. The PD controller’s communication interface allows for real-time power adjustments to meet the wireless charger’s needs, enabling fast charging while maintaining compatibility.
