H2-3. Motor drive choices: triac control vs inverter BLDC

Motor-drive choice must be evaluated as a controller-level contract: each path changes the dominant failure modes (brownout, EMI-induced resets, overload behavior) and defines the minimum evidence signals required for reliable protection and service diagnosis.

1) Triac path (universal motor): phase-angle vs burst-fire

• Phase-angle: fine speed control but higher sensitivity to dv/dt, brush-noise spikes, and conducted EMI; nuisance reset risk rises if the MCU rail is not hardened.
• Burst-fire: switches full cycles; often easier to manage conducted EMI at the cost of more visible torque ripple at low speed and potentially noisier suction feel.
• Controller focus: ensure deterministic gating, snubber integrity, and a current envelope that distinguishes start surge from stall/overload.

2) Inverter path (BLDC/PMSM): quieter and efficient, but bus-critical

• Requires a DC bus, a switching bridge, and gate driving; reliability depends on precharge, bus stability, and a safe start strategy under high load.
• Controller focus: current-limited ramp, startup-failure handling (retry/cooldown), and clear separation of “limit” vs “fault” states in the event log.

3) Decision factors that matter for central vacuum systems

4) Minimum viable sensing list (evidence that enables correct actions)

5) Mini evidence hook (fast isolation when symptoms look random)

• If random resets appear only during start: capture inrush current and MCU rail together; synchronous rail droop indicates a power/inrush root cause rather than a logic fault.

H2-4. Soft-start & inrush control (the #1 reliability issue)

Soft-start is a state machine that limits stress and prevents brownouts: it separates precharge from ramp, confirms stabilization using evidence (I_SENSE, rail/bus, P_SENSE), and enforces a brownout-aware retry/cooldown policy to avoid relay welding and repeated hot restarts.

1) Main inrush sources (and the evidence that reveals each one)

• Universal motor start: large current peaks early; visible in I_SENSE envelope and line/bus sag.
• Bulk capacitors (inverter path): bus rise slope and charge surge are visible in DC bus behavior.
• Relay closure / bypass: step events and arcing noise correlate with rail jitter and short spikes.
• Long mains wiring: brownout appears as bus/rail sag synchronized to inrush, often causing resets.

2) Practical techniques (controller actions, not just components)

3) Threshold setting (how to avoid nuisance trips without losing protection)

• Define three current envelopes: I_start_peak (early window), I_run_nom (steady), I_stall_env (restriction/stall upper bound).
• Use separate policies for start vs run:
  • Start limit: allows higher current for a short window but enforces a controlled ramp and rail stability.
  • Run OCP: tighter limits, combined with P_SENSE and temperature to classify overload vs restriction.
• Logging requirement: record which threshold triggered (start-limit vs run-OCP) together with rail/bus status.

H2-5. Sensing chain: current, voltage, speed/tach, temperature

A robust sensing chain is an evidence contract: fast paths protect hardware, mid-speed paths control start/load, and slow paths explain failures and support clog classification. Each signal must remain valid during the worst moments: inrush, switching noise, and brush arcing.

1) Current sensing (I_SENSE): the primary discriminator

2) Voltage sensing: energy layer vs logic layer

• Zero-cross / phase reference (triac path): anchors gating timing and prevents drift-driven control errors.
• DC bus (inverter path): verifies precharge completion and detects sag/collapse during start and overload.
• MCU rail (all paths): distinguishes “real fault” from EMI-induced reset; rail droop aligned with current peaks points to inrush/power-tree issues.

3) Speed/tach: classifies load vs stall without over-explaining motor theory

• Tach/Hall pickup separates “high load but spinning” (restriction) from “speed collapse” (stall/mechanical fault).
• Back-EMF hints (high level) can provide a coarse “rotation present” check for inverter paths.

4) Thermal sensing: slow signals that drive derating

• Motor NTC: long-term load and airflow health (heat rises when restriction persists).
• Power device NTC: switching loss and heatsink health; triggers derating before hard shutdown.
• PCB hotspot: detects enclosure/dust-driven thermal traps and local stress points.

5) Sampling strategy: fast protection vs slow explanation

H2-6. Pipe pressure / clog detection (physics → signals → discriminators)

Clog detection becomes reliable when it is treated as a classifier driven by physical signals: vacuum pressure and motor load form a stable 2D space, while ΔP across the filter adds a targeted discriminator. The objective is to separate clog, leak/open inlet, filter restriction, and normal with clear evidence windows.

1) What can be measured (practical signals)

• P_abs: absolute vacuum pressure near the canister (system-level vacuum build-up).
• ΔP_filter: differential pressure across the filter (direct indicator of filter restriction).
• Airflow proxy: combine vacuum with motor load (I or power) to infer airflow changes without a dedicated flow sensor.

2) Typical failure modes (central vacuum specific)

3) Discriminators (the key)

• Clog likely: vacuum rises abnormally (high P_abs) while airflow proxy drops; motor load changes and may climb toward the run envelope boundary.
• Leak / open inlet: vacuum remains low (P_abs low) while motor load stays high/steady; suction feel is poor despite continuous run.
• Filter clog: ΔP_filter increases and motor load increases; vacuum may still rise, but the filter differential becomes the most direct evidence.
• Canister full: persistent restriction indicators with slow drift; requires time-window logic and baseline comparison.

4) Algorithm sketch (not guesswork)

H2-7. Remote I/O & wall inlets (long wires, miswire, ESD reality)

Wall inlets and remote start loops behave like antennas. Robust design requires a three-layer input chain: energy limiting → waveform shaping → survival clamping, plus an event model that converts raw edges into reliable start/stop events with timestamps and burst detection.

1) Typical field wiring and why it fails

• Low-voltage loop shared by multiple inlets: parallel contacts and long runs create large loop area and induced noise.
• Long wire next to motor/power wiring: induced transients and burst edges appear during start and commutation.
• Real-world mistakes: loose terminals, moisture, polarity confusion (if keyed), and accidental shorts.

2) Input hardening: three layers that must cooperate

3) Debounce as an event model (not just a delay)

• Edge confirmation: start/stop changes must persist beyond a minimum time window.
• Burst detection: multiple toggles inside a short window indicates ESD/induced noise; treat as “invalid event”.
• State gating: during startup ramp, ignore rapid toggles; avoid oscillating enable outputs.
• Evidence logging: store edge timestamps, burst counts, and input state duration for service diagnostics.

4) Miswire and induced transient cases (minimum observable evidence)

• Starts by itself: verify edge burst count + edge timestamps; inspect inlet/connector area for ESD marks and routing proximity to motor wires.
• Dead input: check stuck level, clamp behavior, and whether the RC time constant is filtering legitimate closures.

5) Output controls: fail-safe off and stable indication

• Motor enable (relay/SSR): default to OFF on reset/UVLO/watchdog; require stable “run request” to re-enable.
• Status LED / buzzer: reflect validated events and latched faults, not raw bouncing inputs.

H2-8. Protection & fault handling (OCP/OVP/OTP/stall/arc/brownout)

Protection must be a system: fast hardware survival handles catastrophic events, supervised firmware limits keep the product usable, thermal derating prevents long-term stress, and brownout-safe restart rules avoid reset loops. Each fault must map to evidence → action → retry policy → clear condition.

1) Protection layers (time-scale aligned)

2) Action semantics: LIMIT → TRIP → LATCH

• LIMIT: reduce stress while staying operational (preferred for restriction/overload).
• TRIP: stop, cooldown, then retry under controlled conditions and limited attempts.
• LATCH: repeated or dangerous faults require manual reset/service.

3) Brownout-safe restart gating (avoid reset loops)

• After UVLO/watchdog reset, keep motor enable OFF until rails/bus are stable for a minimum window.
• Require the remote run request to be stable (no bursts) and present continuously before restart.
• Apply startup cooldown timers to prevent repeated hot restarts.

4) Fault table (fault → evidence → action → retry policy)

H2-9. EMC/EMI design that actually matters for this controller

Practical EMC is source → coupling path → victim signal. In central vacuum control, the victims are MCU rails, I_SENSE integrity, and remote I/O. The goal is coexistence: motor noise must stay inside the “dirty zone” so protection and diagnostics remain deterministic.

1) Noise sources that dominate field behavior

• Triac phase control: abrupt dv/dt events inject conducted noise and can create false triggering without proper snubber and gate loop control.
• Inverter switching: fast edges create common-mode noise and measurement injection unless bus decoupling and return paths are controlled.
• Brush arcing: burst EMI can cause reset susceptibility and remote-input burst edges if the system does not enforce event validation.

2) The three coupling paths to design against

3) Board-tied mitigations (what changes the outcome)

H2-10. Validation test plan (minimal but complete)

A minimal plan must still be complete: stress motor start/stop, induce realistic restriction scenarios, abuse remote I/O wiring, and confirm thermal robustness. Each test set defines what to observe and pass/fail so nuisance trips and misclassification are eliminated.

1) Minimal setup (engineering-level, not certification)

• Oscilloscope for rail/bus and I_SENSE capture; time correlation to switching patterns.
• Current measurement method (probe or defined shunt test points).
• Controllable restriction tools: partial block, full block, filter restriction, open inlet leak.
• Remote I/O abuse sources: ESD contact/air, EFT-like bursts on long wire, miswire simulations (safe levels).

2) Test groups and required observations

3) Universal pass/fail criteria (three hard requirements)