Fuel Gauge (Coulomb Counter): Algorithms, Calibration, and Validation
A fuel gauge blends OCV tables with coulomb counting—plus temperature and resistance learning— to turn “remaining time” into a testable, repeatable metric.
Algorithms
OCV–SoC LUTs, coulomb counting, and hybrid blending with adaptive weights.
Calibration
One-time learning cycle, temperature tables, resistance learning.
Accuracy Budget
Quantization, zero-offset, drift, and temperature effects—planned up front.
Validation
Matrix across temperature, load, and SoC windows with pass/fail targets.
Charger profiles, power-path switching, and hot-swap protections are covered on sibling pages under the PMIC hub to keep this topic focused.
How It Works — OCV Tables, Coulomb Counting, and the Hybrid Blend
At rest, open-circuit voltage (OCV) maps to SoC via per-temperature LUTs; under dynamic load, a coulomb counter integrates current. A hybrid mixer weights both paths and guards against drift.
Q(t) = ∫ I(t) dt
SoCt+Δ = SoCt − (1/Crated) · ∫ I(t) dt
Use short windows for current, longer windows for voltage.
SoC = α·SoCOCV + (1−α)·SoCCC
α ≈ f(rest time, |dI/dt|, temperature zone)
Increase α after long rest; decrease α for burst loads.
Next: Algorithms & Tables · Calibration · Power Path & Sleep
Algorithms & Tables — OCV LUT, Temperature Zones, Resistance Learning, Hold
Build a reliable fuel gauge by combining OCV–SoC lookup tables across temperature zones with coulomb counting, internal resistance learning, and a Hold/Relax state that prevents jumps at the end of charge or sleep transitions.
Q(t) = ∫ I(t) dt
SoCt+Δ = SoCt − (1/Crated) · ∫ I(t) dt
Short window for current; longer window for voltage.
SoC = α·SoCOCV + (1−α)·SoCCC
α = f(rest time, |dI/dt|, temperature zone)
Clamp correction rate to avoid sudden jumps.
OCV–SoC LUT (per temperature zone)
Fields: Temp_C, SoC_%, OCV_V.
Use −10/25/45 °C as a starting point; 5% SoC step or finer.
Temperature table & hysteresis
Switch zones with 2–3 °C hysteresis; raise α after long rest in a stable zone.
Resistance learning (R)
Estimate with load steps: Rest ≈ ΔV/ΔI after filtering polarization. Use R to temper OCV during dynamic loads.
Hold / Relax handling
Enter Hold near CV taper or before ship/sleep to freeze integration; on exit, apply a bounded OCV correction (e.g., ≤1% SoC/s).
Calibration & Learning Cycle — One-Time Setup, Lasting Stability
A single learning cycle establishes baseline OCV tables, temperature zones, and R-estimates so the hybrid algorithm converges quickly and stays stable across loads and climates.
What to log
timestamp, V, I, T, SoC_est, mode(run/rest), note. Keep 1–2% SoC sampling
during discharge. Repeat in at least three climates: −10/25/45 °C.
Acceptance metrics
- RMSE(SoC) ≤ ±2–3% within validation matrix.
- Rest drift after 2–3 h ≤ ±1% SoC.
- Wake-up jump ≤ 3% SoC (bounded correction rate).
Checklist (SOP)
- Record battery chemistry, rated mAh, cutoff voltage; verify CC/CV taper.
- Full charge → rest 2–3 h, capture OCV (per zone).
- Discharge @ nominal load to cutoff, log V/I/T/SoC every 1–2%.
- Rest 2–3 h, capture OCV; recharge to full.
- Populate OCV–SoC LUT and temperature table; save R-estimate.
Next: Validation Playbook · ICs from 7 Brands
Power Path & Sleep — Debounce, Freeze, and Bounded Correction
Path switching and sleep/wake transitions can inject spurious charge into the integrator. Use state-aware gating, average-current filtering, and a bounded OCV correction to keep SoC stable during hot-plug and ship/shutdown events.
States & Transitions
Run → Hold → Ship/Shutdown → Wake. Freeze integration in Ship/Hold; on wake, apply OCV correction with rate limit.
Average Current Filtering
Short window for current (tens–hundreds ms); longer window for voltage (seconds). Reset/soft-start windows after switching.
Hot-Plug / Path Switching
Interrupt → debounce (ms) → freeze integration → confirm steady state → unfreeze with gradual α ramp. Ignore one-shot inrush/backfeed.
Bounded Correction
Limit single-step jump <= 3% SoC and correction rate <= 1%/s. Log “reason + timestamp” for validation.
See also: Algorithms & Tables · Validation Playbook
Single vs Multi-Cell — Direct Gauge or AFE/Monitor Daisy-Chain
Choose direct single-cell gauging for wearables and 1S packs, or a multi-cell AFE/monitor with a host gauge/MCU for stacked series packs. Coordinate addressing and balancing to keep SoC and safety aligned.
Single-Cell Direct Gauge
- I²C/SMBus/HDQ; low quiescent; compact BOM.
- Best for wearables/IoT and 1S tool packs.
- Limits: voltage range and redundancy.
Multi-Cell via AFE/Monitor + Gauge/MCU
- Per-cell sense, daisy-chained or isolated links.
- Host-side SoC synthesis; balancing coordination.
- Address planning and alert sharing required.
Addressing & Topology
Map I²C/SMBus addresses and monitor IDs; avoid conflicts with charger/PMIC. Share ALERT/PG lines thoughtfully; keep a central address map with revision control.
Balancing Coordination
Mark balancing windows in logs, since energy moved between cells can look like load. Do not correct SoC mid-balance; recheck OCV after a short relax.
Continue to: ICs from 7 Brands · Back to PMIC Hub
Interfaces & Registers — I²C/SMBus, IRQ, Snapshots, NVM Profile
Implement the bus, interrupts, and register snapshot first. Keep units consistent, version your NVM profile, and bound any post-wake corrections. The template below mirrors the recommended fields.
Bus & IRQ Basics
- I²C/SMBus standard/fast/hs; retry on NACK; allow clock stretching if device supports it.
ALERT/INTis often open-drain: add pull-up; debounce a few ms; level/edge per datasheet.- PEC (packet error checking) optional on SMBus—enable where host stack supports it.
Register Snapshot (minimum set)
Read in one burst if available; keep units stable across firmware and logs.
- Status/Flags (alerts, state machine)
- Voltage (mV), Current (mA, signed), Temperature (0.1 °C)
- SoC (0.01 %), Cycle/Capacity if available
Scaling & Conventions
Use fixed-point fields to avoid FP on small MCUs. Confirm current polarity (charge > 0 or < 0) and two’s-complement width.
// Example scaling
Voltage_raw → mV : mV = raw * 1
Current_raw (signed) : mA = raw * LSB_mA
Temperature_raw : 0.1°C = raw
State of Charge (0.01%) : SoC% = raw / 100NVM Profile (Import/Export)
- Include thresholds, sleep/hold policy, correction limits, OCV LUT base, temperature zones.
- Write flow: unlock → page write → CRC → power-fail guard → reboot → self-check.
- Version and rollback: keep
profile_idandcrcfields; log changes.
Driver Porting Notes
- Unify error codes (timeout/NACK/CRC) and back-off policy.
- Before sleep: stop polling; on wake: read Status then main data; apply bounded OCV correction.
- Log “correction reason + timestamp” for validation.
Typical Transactions (pseudo)
// Burst read snapshot
i2c_read_block(ADDR, REG_STATUS, buf, LEN_MIN_SET)
// Write config (read-modify-write)
cfg = i2c_read16(ADDR, REG_CONFIG)
cfg |= CFG_ALERT_EN
i2c_write16(ADDR, REG_CONFIG, cfg)
// NVM profile write
enter_nvm(); page_write(profile); verify_crc(); exit_nvm(); soft_reset()
Keep units consistent with Algorithms & Tables and align snapshot cadence with Validation Playbook.
Accuracy Budget — Quantization, Zero Offset, Temperature Drift, Integration Leakage
Break SoC error into measurable parts and plan limits up front. Use the quick rules below to size ADC resolution, offset trimming, LPF windows, and bounded corrections.
Eq ≈ (0.5·LSB) / Crated (as SoC)
Set current ADC LSB < 0.1–0.2% of nominal load.
E0 ≈ Ioffset · Δt / Crated
Trim baseline or auto-zero during long rests.
EI ∝ window length & cutoff vs load spectrum
Shorter I-window for bursts; longer V-window for OCV.
|ΔSoC| per step ≤ 3% and rate ≤ 1%/s
Apply after wake or path switching only.
Worked Example (3000 mAh pack)
Sampling 100 ms, Ioffset=0.5 mA → over 1 h, E0≈ (0.5 mA·3600 s)/3000 mAh ≈ 0.06 SoC%. Keep ADC LSB < nominal_load/1000 to hold Eq small; shorten I-window during bursts to limit EI.
Inputs:
C_rated = 3000 mAh, Δt = 3600 s, I_offset = 0.5 mA, window_I = 100–200 ms
Quick results:
E0 ≈ 0.06 %SoC | Eq small if LSB < 0.1% nominal load
Bound: |ΔSoC_step| ≤ 3% and |dSoC/dt| ≤ 1%/s (after wake/switch)Tie this to Power Path & Sleep limits and verify in your Validation Playbook.
Validation Playbook — Matrix, Rest Drift, Wake-Up Jump
Validate your fuel gauge against a clear matrix of Temperature × Load × SoC windows. Track RMSE(SoC), Rest Drift, and Wake-Up Jump with the downloadable checklist and report template.
| Temp_C | Load | SoC Window | Metrics | Notes |
|---|---|---|---|---|
| −10 / 25 / 45 | 0.1C / 0.5C / 1C | 100–80% | RMSE, Rest drift, Wake-up jump | Record events; steady-state markers |
| −10 / 25 / 45 | 0.1C / 0.5C / 1C | 80–60% | RMSE, Rest drift | Burst loads if applicable |
| −10 / 25 / 45 | 0.1C / 0.5C / 1C | 60–40% | RMSE | Note convergence latency |
| −10 / 25 / 45 | 0.1C / 0.5C / 1C | 40–20% | RMSE | — |
| −10 / 25 / 45 | 0.1C / 0.5C / 1C | 20–0% | RMSE, Cutoff behavior | Log cutoff thresholds |
Compare with your Accuracy Budget and feed refined LUTs back to Algorithms & Tables.
ICs from 7 Brands — Feature Comparison (Placeholders)
This section lists feature dimensions only (interface, cells, quiescent, package, tools) as placeholders. To ensure 100% official data, specific part numbers (PNs) and values will be filled after your confirmation.
| Brand | Cells | Algorithm | Interface | Quiescent (typ) | Package | Tools | Notes |
|---|---|---|---|---|---|---|---|
| Brand A | 1S / 2–4S | OCV+CC / NVM learning | I²C / SMBus / HDQ | μA-class | DFN/QFN/WLCSP | GUI / EVB / Driver | To be confirmed |
| Brand B | 1S | Chem model support | I²C / SMBus | μA-class | WLCSP | GUI / EVB | — |
| Brand C | 2–4S / 6–16S | Host synthesis via AFE | Daisy-chain / isolated | — | QFN/TQFP | GUI / EVB / App notes | BMS-focused |
| Brand D | 1S | OCV+CC | HDQ / I²C | — | SOT/DFN | GUI / EVB | Legacy HDQ option |
| Brand E | 6–16S | AFE + host gauge | Isolated daisy-chain | — | QFP/QFN | BMS GUI / EVB | Industrial focus |
| Brand F | 1S / 2–4S | Chem profiles | SMBus / I²C | — | QFN/WLCSP | GUI / Drivers | — |
| Brand G | 1S / 6–16S | Hybrid + learning | I²C / isolated chain | — | Assorted | GUI / EVB / SDK | — |
After your PN confirmation, we will populate this grid with official datasheet values. Meanwhile, align driver work with Interfaces & Registers and LUT conventions in Algorithms & Tables.
FAQs — Design, Calibration, and Validation
Concise answers to frequent engineering questions about fuel gauges and coulomb counters. Expand any item to see practical guidance and the relevant section for deeper reading.
OCV-only vs OCV+CC: which is more reliable?
How dense should my OCV–SoC LUT be?
How do I tune the hybrid weight α?
What does the one-time learning cycle include?
How do I avoid SoC jumps after sleep or hot-plug?
What averaging windows should I start with?
How do I estimate internal resistance correctly?
What must a register snapshot include?
Single-cell or multi-cell with AFE: how to choose?
How do I build an accuracy budget that predicts KPIs?
Beyond RMSE, what should my validation matrix record?
How should I bound post-wake corrections to avoid oscillation?
What files should I version and how?
How do vendor toolchains impact bring-up time?
Resources & RFQ — Downloads and Contact
Templates and checklists to accelerate design, learning, and validation. Submit your BOM for cross-brand alternatives or contact us for tailored guidance.
- Charger PMIC — Charging stages and taper settings live here.
- Power Path — Ideal-diode ORing and hot-swap behavior.
- eFuse / Hot-Swap — Protections, inrush and short-circuit policies.
- BMS / Multi-cell Monitor — Daisy-chain AFE and balancing.
Back to PMIC Hub.
