High-Speed ESD / TVS Arrays (Ultra-Low C, IEC 61000-4-2/-4-5)
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High-speed TVS arrays are not “just ESD parts”: they must meet protection targets without consuming the eye/jitter budget. This page gives a parameter+layout+verification playbook to pick ultra-low-C, well-matched arrays and prove they pass IEC while keeping link margin.
Definition & Scope: High-Speed TVS Arrays
Focus: ultra-low-capacitance TVS / ESD diode arrays that pass IEC ESD/surge while keeping differential-channel loss, mismatch, and eye margin within budget.
What “TVS array” means in high-speed ports
- Array form factor: multi-channel protection in one package; channel-to-channel matching and shared ground return become first-order design variables.
- Differential vs single-ended: differential pairs typically use line-to-ground clamps on each line. Symmetry (device + layout) prevents diff→CM mode conversion.
- Protection target: limit transient voltage/current at the PHY pad during IEC events without creating excessive capacitance / stub inductance that degrades the channel.
When protection becomes “high-speed”
It is “high-speed” when the protector’s parasitics enter the link budget: capacitance (C) affects insertion loss; stub length / inductance (L) affects reflections and clamp overshoot; mismatch (ΔC/ΔL) creates mode conversion and EMI risk.
Practical gate (use placeholders)
- If Cdiff causes IL@f to worsen by > X dB, treat as high-speed.
- If stub length (pad→TVS branch) > X mm, reflection/overshoot risk rises sharply.
- If ΔC between pair lines > X pF or > X%, mode conversion becomes measurable.
What this page delivers (and what it does NOT)
In-scope
- Actionable spec threshold table (C, Rdyn, Vclamp, leakage, matching, S-params).
- Layout rules that preserve differential integrity and shorten return path.
- Verification checklist for IEC 61000-4-2/-4-5 + post-stress health checks.
Out-of-scope
- Full signal-integrity theory (channel modeling, full crosstalk derivations).
- Protocol-layer specifications and training algorithms (USB/PCIe/DP/HDMI details).
- System termination/impedance design as a standalone topic (only referenced where TVS interacts).
Threat Model: What Kills High-Speed Ports (ESD vs Surge vs EFT)
A correct protection design starts with a correct threat bucket. Different transients stress different parameters: return inductance dominates ESD overshoot, energy/thermal dominates surge, and repeatability/soft upset dominates EFT/burst.
Threat buckets (engineering view)
- ESD (IEC 61000-4-2): very fast edge; clamp performance is limited by package/via/return inductance. Layout often decides the peak.
- Surge (IEC 61000-4-5): higher energy; success depends on energy handling + thermal path + system return routing.
- EFT/Burst (IEC 61000-4-4): repetitive pulses; the primary risk is soft upset and gradual parameter drift that erodes margin.
Real coupling path (port-level)
External discharge couples through the connector, then splits into: (1) the TVS clamp, and (2) any unintended return path through signal/power grounds. The design goal is to keep the transient current out of sensitive references by providing a short, low-inductance path to chassis/shield (or the defined return domain).
Event → priority parameters (use placeholders)
ESD (4-2)
- Return inductance (Lreturn, Lvia): keep branch short (≤ X mm).
- Dynamic resistance (Rdyn): lower Rdyn reduces clamp voltage at high di/dt.
- Clamp level (Vclamp @ Ipp=X A): must stay below PHY stress limit (≤ X V).
Surge (4-5)
- Energy/thermal: pulse energy and junction heating dominate survival.
- System return routing: ensure current is diverted to chassis/shield (not logic ground).
- Clamp robustness: verify Vclamp stability across repeated pulses (ΔV ≤ X).
EFT/Burst (4-4)
- Repeatability: watch for soft upsets that appear only under repetition.
- Parameter drift: leakage, capacitance, and mismatch drift after bursts (ΔI/ΔC ≤ X).
- Margin erosion: confirm BER/CRC remains within limit under burst stress (≤ X).
“Pass” does not mean “risk-free”: enforce post-stress health checks
- Leakage check: Ileak @ V= X must remain ≤ X (post-stress vs baseline).
- Matching check: ΔC/ΔR between pair lines must remain ≤ X (no new mode conversion).
- Link margin check: eye/BER/CRC under load must not degrade beyond X% vs baseline.
- Thermal/temperature re-check: repeat at hot/cold if field failures correlate with environment.
How TVS Arrays Work at GHz: Equivalent Circuit That Matters
High-speed protection is governed by two regimes: a GHz small-signal channel where capacitance shapes loss and mismatch, and a large-signal transient where dynamic resistance and return inductance set clamp overshoot.
Two regimes, one device
- GHz (signal path): the dominant term is capacitance to ground (Cline/Cdiff). Excess C increases insertion loss and reduces eye margin.
- Transient (IEC stress): the dominant terms are dynamic resistance (Rdyn) and inductance (package/via/return). Inductance creates overshoot during fast di/dt.
Minimum equivalent circuit terms (do not ignore)
Cj / Cline (capacitance)
Acts as a shunt load at high frequency: C ↑ → IL ↑ → eye ↓. Bias and temperature can shift C.
Rdyn (dynamic resistance)
Sets clamp slope: Rdyn ↑ → Vclamp ↑ at the same peak current. Lower Rdyn reduces stress on the PHY.
Lpkg / Lvia / Lreturn (inductance)
Adds overshoot during fast transients: Vovershoot ≈ L · di/dt. Layout often dominates Lreturn.
Differential pair view: matching prevents mode conversion
- Cdiff / Ccm: effective differential and common-mode capacitance control how the pair loads the channel.
- Mismatch (ΔC / ΔL): converts differential energy into common-mode: ΔC ↑ → Diff→CM ↑, increasing EMI risk and jitter sensitivity.
- Symmetry rule: device matching + mirrored routing + matched vias preserve differential behavior.
Dynamic vs static: avoid datasheet misreads
- Capacitance and leakage are commonly measured as small-signal or DC values under specific conditions (frequency, bias, temperature).
- IEC events are large-signal transients where Rdyn and inductance dominate the peak voltage.
- A clamp that looks safe on paper can still overshoot on a PCB with long return inductance.
Key Specs That Actually Matter (With Threshold Placeholders)
Use a fixed review order to prevent “ESD-only” selections that break the channel. Start with channel integrity, then verify clamp strength, and finally confirm leakage and stability across temperature and bias.
Review order (three gates)
- Gate 1 — Channel integrity: C / matching / S-params (must not collapse eye margin).
- Gate 2 — Protection strength: Vclamp@Ipp / Rdyn / IEC levels (must keep PHY safe).
- Gate 3 — Stability: leakage + drift across temperature/bias + post-stress health checks.
Capacitance (Cline / Cdiff)
Why it matters: C loads the channel at high frequency:
C ↑ → IL ↑ → eye height ↓. Bias and temperature can shift C.
Threshold placeholders
Cdiff ≤ X pF @ Vbias=Y, f=Z ·
ΔC ≤ X pF (or ≤ X%)
Clamping (Vclamp @ Ipp)
Why it matters: Vclamp limits stress at the PHY, but the measured peak can be higher due to
L · di/dt on the return path.
Threshold placeholders
Vclamp ≤ X V @ Ipp=Y A (same test condition across candidates)
Dynamic resistance (Rdyn)
Why it matters: Rdyn sets the clamp slope:
Rdyn ↑ → Vclamp ↑ at a given current. If Rdyn is missing, approximate via ΔV/ΔI from clamp points.
Threshold placeholders
Rdyn ≤ X Ω (or ΔV/ΔI ≤ X Ω)
Leakage (Ileak)
Why it matters: leakage can shift common-mode bias and reduce stability over temperature.
Evaluate at the intended working voltage and hot conditions.
Threshold placeholders
Ileak ≤ X nA/µA @ V=Y, T=Z
Channel matching (ΔC / ΔR)
Why it matters: mismatch converts differential to common-mode:
ΔC ↑ → CM ↑ → EMI/jitter sensitivity ↑. Prefer explicit matching specs.
Threshold placeholders
ΔC ≤ X pF (or ≤ X%) · ΔR ≤ X Ω
S-parameters (IL / RL)
Why it matters: S-parameters capture the combined effect of capacitance, package, and layout.
Use them to screen candidates before deep compliance work.
Threshold placeholders
IL@f ≤ X dB · RL@f ≥ X dB (or Sdd11 ≤ X)
IEC levels (rating is necessary, not sufficient)
IEC ratings verify survivability under a defined setup. Post-stress health checks are still required to catch
soft failures and latent damage.
Threshold placeholders
IEC 61000-4-2: contact/air = X kV/Y kV ·
IEC 61000-4-5: surge = X (setup-specific)
Placement & Layout: The Only “Free” Performance You Can Get
Layout dominates transient overshoot and mode conversion. The same TVS array can pass or fail depending on stub length and return-path inductance. Treat placement rules as hard design constraints, not guidelines.
Placement decision: connector-side vs PHY-side
- Default (connector-side): place TVS near the port entry to divert ESD current early, reducing injection into internal grounds and references.
- Exception (PHY-side): only if the system-defined return domain (chassis/shield tie-point) and routing constraints make the connector-to-TV S segment the dominant risk; validate with post-stress checks.
- Non-negotiable: regardless of placement, minimize stub and return inductance.
Stub-length rule (primary threshold)
The branch from the main differential route to the TVS pads behaves like a high-frequency stub. Longer stubs increase reflections and make transient peaks worse.
Threshold placeholder
StubLen ≤ X mm (main line to TVS pad, including fanout/via)
Via/pad discipline: eliminate asymmetry
- Equal via count: D+ and D− must have identical via count (ViaCountDiff = 0).
- Mirrored placement: vias and fanouts should be mirror-symmetric around the pair centerline.
- No hidden stubs: avoid unused via barrels that create extra stub inductance.
Threshold placeholder
GeoSkew ≤ X mm (branch geometry mismatch between D+ and D−)
Return path: short, wide, and in the correct ground domain
- Domain first: return to chassis/shield (or the system-defined return domain).
- Geometry rule: use a short, wide path with multiple ground vias to reduce Lreturn.
- Avoid plane breaks: do not force ESD current to detour across splits/cuts in the reference plane.
One-glance mistake checklist
- TVS is far from the connector (long branch before clamp).
- Ground is a thin, long trace (single-via return).
- D+ and D− branch geometry is not mirrored.
- Layer transition without continuous reference plane (return break).
- ESD current passes through sensitive ground regions (wrong return domain).
Differential Pair Integrity: Matching, Symmetry, and Mode Conversion
Differential protection is not “two single-ended clamps”. Any mismatch (ΔC/ΔL) converts differential energy into common-mode, increasing EMI and jitter sensitivity. Preserve symmetry from the pair to the TVS and into the return path.
Mismatch sources (ΔC / ΔL) and control points
- Device: channel-to-channel mismatch in the array (ΔC, ΔR).
- Package/pads: non-mirrored fanout and unequal pad geometry.
- Vias: extra via on one line or unequal via-to-plane distances.
- Reference plane: plane splits/cuts causing asymmetric return paths.
What mismatch looks like in real systems
- Common-mode content increases (Diff→CM), degrading EMI.
- Jitter sensitivity rises; marginal links fail under cable/temperature changes.
- Receiver thresholds become more sensitive to ground bounce and external coupling.
Symmetry rules (layout checklist-ready)
- Mirror the branch geometry from D+ and D− to the TVS (same length, same bends).
- Match via count and placement (ViaCountDiff = 0; mirrored positions).
- Keep the reference plane continuous under both lines (no asymmetric breaks).
- Use symmetric ground-via stitching for the TVS return path.
Evaluation (focus on discrimination, not full SI theory)
- S-parameters: screen by Sdd21 (diff IL) and watch for common-mode growth indicators (placeholder metric).
- TDR: mismatch appears as unequal impedance spikes at the TVS location on D+ vs D−.
- Quick field check: if a symmetry-only layout tweak improves EMI/BER without changing the TVS part, the root cause is mismatch/return.
Co-Design with System Grounds & Shields (Without Turning into an SI/EMC Page)
ESD robustness is frequently limited by the return path, not the TVS array itself. The objective here is to control where discharge current flows (signal return vs shield vs chassis) so it does not traverse sensitive ground loops and collapse link margin.
Ground/shield domains (name the domains first)
- SGND (signal return): functional ground reference for circuitry and routing reference planes.
- SHIELD (cable shell): connector shell and cable shield, directly coupled to external discharge.
- CHASSIS (mechanical ground): metal enclosure/frame; may be tied to PE or floating depending on product class.
- Bond point: the intentional connection location that determines where shield current returns.
Preferred return path (design objective)
- Goal: route ESD current into SHIELD/CHASSIS as early and as directly as the architecture allows, minimizing injection into SGND.
- Action: connect the TVS return to the system-defined return domain using a short, wide path with multiple vias.
- Guardrail: avoid forcing discharge current to detour through sensitive ground islands or reference regions.
Architecture placeholder
ReturnDomain = CHASSIS / SHIELD / DEFINED
(set by product grounding architecture)
Typical failure mode: discharge current crosses sensitive ground loops
- ESD event triggers link retrain / CRC bursts even when the TVS part is “rated high”.
- Failures depend on cable posture, chassis contact, or installation state (strong sign of path sensitivity).
- Shield bonding happens far from the connector, forcing current into SGND regions first.
First localization target: verify the discharge current path is not routed through SGND sensitive islands or reference nodes.
Shield bonding decision (compact decision tree)
Step 1
Is there a defined CHASSIS (metal enclosure/frame)?
Step 2
Does the connector provide a robust shield shell / 360° contact path?
Step 3
Can SHIELD bond directly to CHASSIS near the port, or must it be bonded at a defined point?
(BondType placeholder: DC / RC / BEAD)
Output actions
- Prefer near-port shield/chassis return paths to keep discharge current out of SGND.
- Avoid long “pigtail” returns; use short, wide bonds with stitching vias.
- If a bond must exist, place it to prevent current crossing sensitive ground regions.
When common-mode devices may be needed (keep it scoped)
- ESD causes link drops even when the clamp appears adequate → suspect Diff→CM injection/return-path issues.
- EMI sensitivity is strongly cable-posture dependent near the connector region → suspect common-mode current.
- TVS insertion loss is acceptable but mode-conversion symptoms increase → fix symmetry first; then consider CM mitigation.
For common-mode suppression and impedance matching details, refer to the sibling page:
CM Chokes & Impedance Matching.
Verification & Measurements: How to Prove It Works (and Not Lie to Yourself)
Passing IEC levels is a baseline. The verification loop must also show that link margin is preserved and that post-stress drift is within limits (no latent damage). Use a staged workflow with repeatable logging.
Stage 0: establish a baseline (no baseline → no conclusions)
- Fix cable/fixture/grounding configuration; changes invalidate comparisons.
- Record before/after metrics: S-params and link behavior under the same conditions.
- Baseline outputs: IL/RL/mode-conversion placeholders + BER/training/error counters.
Pre-compliance IEC sweep: repeatability fields (template)
ESD level
Contact = X kV · Air = Y kV · Polarity = +/−
Shots & points
Shots/point = X · Points = shell / pin-area / shield-edge (placeholder)
Cable state
Length = X · Routing posture = X · Plug state = plugged/unplugged
Grounding setup
Ground strap length = X · Bond location = X (must log for repeatability)
Environment
Temp = X · RH = X · DUT state = traffic profile X
Failure bucket
Retrain / CRC / hang / latch-up / reset (placeholder)
Signal-chain checks (compare before vs after)
- VNA / S-params: Sdd21 (diff IL), Sdd11 (diff RL), and a mode-conversion placeholder metric.
- Eye / BER: same pattern/rate/channel; quantify margin loss after adding TVS or changing bonding.
- A/B logic: one variable per experiment (TVS part, layout symmetry, bond point, return path).
Threshold placeholders
IL@f ≤ X dB · RL@f ≥ X dB · ModeConv_peak ≤ X @ f=Y
Protection checks: clamp observation (measurement pitfalls included)
- Order: verify return-path topology first, then interpret clamp waveforms.
- Pitfall: insufficient bandwidth underestimates peaks (false “good clamp”).
- Pitfall: large probe ground loops add inductance and distort waveforms.
- Pitfall: inconsistent reference points make comparisons meaningless.
Post-stress checks (latent damage guardrails)
- Leakage drift: ΔIleak ≤ X @ V=Y, T=Z
- Capacitance drift: ΔC ≤ X (pF or %) · mismatch drift: Δ(ΔC) ≤ X
- Link behavior drift: retrain count ≤ X/period · CRC rate ≤ X
Always compare to baseline under the same configuration; post-stress data without a baseline is not actionable.
Production hook (sampling-only, keep it lightweight)
- SampleRate = X% (placeholder) with a reduced-level ESD sweep + leakage spot-check.
- If drift exceeds thresholds, trigger a return-path review (bond point + symmetry) and part lot review.
Reliability & Failure Modes: Soft Failures, Latent Damage, and What to Log
Passing once is not the goal. Long-term stability depends on controlling latent damage and ensuring repeatable evidence across polarity, humidity, grounding, and cumulative exposure.
Failure mode dictionary (make every mode measurable)
Short / stuck clamp
Observable: Ileak @ V=X rises sharply · Port DC level shifts · Enumeration/training may fail.
Open / lost protection path
Observable: channel discontinuity · protection margin reduced (verify via post-stress checks and drift).
Leakage rise (temperature-dependent)
Observable: ΔIleak ≤ X (placeholder) · stronger temperature slope after stress.
Capacitance drift (Cdiff/Ccm)
Observable: ΔC ≤ X (pF or %) @ f=Y, Vbias=Z (placeholders).
Matching degradation (ΔC/ΔR increases)
Observable: ΔC_match ≤ X (pF or %) · mode-conversion sensitivity increases.
Soft failures & latent damage: recognizable symptom buckets
- After ESD: intermittent CRC bursts / retrain spikes while “basic clamp” appears fine.
- Temperature becomes a trigger: hot/cold runs fail more often than room conditions.
- Failure appears after plug/unplug cycles: connector shell contact state changes the return path.
- Batch sensitivity: one lot shows higher drift or higher failure probability under the same stress profile.
Latent damage is detected by drift vs baseline, not by a single absolute reading.
What to measure to catch latent damage (baseline vs post-stress deltas)
Electrical health
Ileak @ V=X, T=Y → ΔIleak ≤ X ·
Cdiff/Ccm @ f=Y, Vbias=Z → ΔC ≤ X ·
ΔC_match ≤ X (placeholders).
Signal-chain health
SI_delta ≤ X (placeholder) using IL/RL or an agreed metric ·
ModeConv_peak ≤ X @ f=Y (placeholder).
Behavioral health
Retrain count ≤ X/period · CRC rate ≤ X · Training fail rate ≤ X% (placeholders).
Logging template (must enable reproducibility)
Exposure
Total shots = N · Polarity = +/− · Contact/Air = contact/air · Level = X kV
Environment
RH = X% · Temp = Y · Cable posture/state = X (placeholders)
Grounding scheme
ReturnDomain = CHASSIS/SHIELD/DEFINED · BondType = DC/RC/BEAD · Bond location = X
Metrics snapshot
Baseline: Ileak/Cdiff/IL/RL/BER · Post: ΔIleak/ΔC/Δmatch/CRC/retrain (placeholders)
Redundancy boundary: when a second protection stage is justified
- Shield/chassis return cannot be made low-impedance near the port (structural constraints).
- IEC passes but drift metrics exceed limits or soft-failure buckets persist.
- Repeated real-world ESD exposure is expected (field handling/plug cycles) and cumulative stress dominates.
- Clamping margin to a sensitive PHY is minimal (tight Vclamp headroom), requiring energy sharing.
Multi-stage protection is discussed only as a boundary condition; component selection details belong to sibling pages.
Engineering Checklist (Design → Bring-Up → Compliance → Production)
This section compresses the page into stage gates. Each gate lists a minimal set of checks and placeholder pass criteria to enforce consistency and manufacturability.
Design Gate
Targets + layout + grounding decision locked
Targets (placeholders)
Cdiff ≤ X pF @ Vbias=Y · IL@f ≤ X dB ·
Vclamp ≤ X V @ Ipp=Y · ΔC_match ≤ X
Layout rules (placeholders)
StubLen ≤ X mm · ViaCountDiff = 0 · Return path: short/wide/multi-via to ReturnDomain
Ground/shield decision
ReturnDomain = CHASSIS/SHIELD/DEFINED · BondType = DC/RC/BEAD · Bond location = X
Pass criteria: targets met + layout review complete + grounding decision documented.
EVT Gate
Bring-up baseline + thermal spot-check
- Baseline SI snapshot (agreed metric): SI_delta ≤ X (placeholder).
- Baseline link snapshot: BER / retrain / CRC recorded (placeholders).
- Port health: Ileak and C baseline recorded at V=X, T=Y.
- Thermal spot-check: re-run at T=X °C (placeholder).
Pass criteria: baseline evidence complete + no symptom-bucket hits under the same configuration.
DVT Gate
Pre-scan configuration repeatable + post-stress deltas within limits
- IEC pre-scan config logged (ground strap, bond point, RH/temp, points/shots).
- Pass levels: contact/air = X kV / Y kV (placeholders).
- After IEC: re-test SI and link; post-stress deltas ≤ thresholds (ΔIleak/ΔC/CRC/retrain placeholders).
Pass criteria: pre-scan passes + re-test shows no unacceptable drift vs baseline.
PVT Gate
Incoming + board test + sampling strategy
- Incoming sampling: C / Ileak / visual + lot ID (SampleRate = X% placeholder).
- Board test: simplified functional BER or training-stat test (placeholder).
- ESD sampling: reduced-level sweep + drift spot-check (ΔIleak/ΔC placeholders).
- Trend tracking: failures/drift correlated to lot and configuration fields.
Pass criteria: sampling yield ≥ X% and no drift trend beyond thresholds.
Stop-the-line triggers (hard rules)
- ΔIleak exceeds threshold → quarantine affected units and review exposure/grounding logs.
- ΔC or Δmatch exceeds threshold → re-check symmetry, via mirroring, and return-domain path integrity.
- Retrain/CRC exceeds threshold → return to return-path and bonding review before changing TVS part.
- Batch clustering appears → initiate lot review with logged fields (RH/temp/bond/fixture).
Evidence pack (handoff-ready)
- Layout evidence: TVS placement + return-path screenshot and via stitching overview.
- Baseline snapshot: SI metric + link stats + port health (Ileak/C).
- IEC log sheet: full configuration fields for repeatability.
- Post-stress delta sheet: ΔIleak/ΔC/Δmatch + CRC/retrain deltas.
- Production sampling record: lot IDs + yields + drift trends.
Applications: Interface Family → Key Differences → Threshold Placeholders
This section maps common interface families to TVS/ESD array priorities without turning interface specifications into the main topic. Each card uses a fixed 3-line structure and lists example material numbers (always verify package/suffix/test conditions).
Rule: Treat all thresholds as placeholders until validated in the target layout, grounding/shield strategy, and compliance setup.
Use baseline vs post-stress drift (ΔIleak/ΔC/Δmatch) to detect latent damage.
USB2 / USB3 / Type-C
High-rate differential · shield/return path sensitive
Key difference
Higher data rate increases sensitivity to Cdiff and insertion loss; the ESD return path to shield/chassis can dominate system behavior.
Threshold placeholders
- Cdiff ≤ X pF @ Vbias=Y, f=Z
- IL@f ≤ X dB · ΔC_match ≤ X (pF or %)
- IEC-4-2: contact/air = X/Y kV (system target)
- Post-stress drift: ΔIleak/ΔC/Δmatch ≤ X
Example material numbers (verify)
TI: TPD4E02B04, TPD4E05U06, TPD2EUSB30 ·
ST: USBLC6-2SC6 ·
Littelfuse: SP3012-04UTG, SP0503BAHT
Verify exact pinout, flow-through routing, and capacitance vs bias/frequency for the targeted lane rate.
HDMI / DisplayPort
Multi-pair · channel consistency dominated
Key difference
Many differential pairs make channel-to-channel matching and consistency more important than any single lane.
Threshold placeholders
- ΔC_match (intra-pair + cross-pair) ≤ X
- IL@f ≤ X dB · RL@f ≤ X (agreed metric)
- IEC-4-2: contact/air = X/Y kV (system target)
Example material numbers (verify)
Semtech: RClamp0524P ·
Littelfuse: SP3012-04UTG ·
ST: USBLC6-4SC6 (use only if capacitance/matching fits) ·
TI: TPD4E05U06 (per-lane style; validate multi-lane uniformity)
For multi-lane connectors, use a consistent footprint strategy and enforce drift checks across lanes.
MIPI D-PHY / C-PHY
Low-swing + high-speed · ultra-low-C dominated
Key difference
Low swing makes the link especially sensitive to extra capacitance and any mismatch-driven mode conversion.
Threshold placeholders
- Cdiff ≤ X pF (tighter than typical high-speed ports)
- ΔC_match ≤ X (tighter) · IL@f ≤ X dB
- IEC-4-2: contact/air = X/Y kV (system target)
Example material numbers (verify)
TI: TPD4E02B04 ·
Nexperia: PESD5V0S1UL, PESD5V0S2UL ·
ST: USBLC6-2SC6 (only if measured C/match passes)
Always verify capacitance vs bias and frequency; small changes can dominate low-swing links.
Ethernet / Industrial
Higher exposure · surge relevance increases
Key difference
Field cabling raises the probability of higher-energy events; system design often must consider IEC-4-5 surge in addition to IEC-4-2 ESD.
Threshold placeholders
- IEC-4-2: contact/air = X/Y kV (system target)
- IEC-4-5: surge = X (kV/A + waveform per system)
- Vclamp ≤ X V @ Ipp=Y · Rdyn ≤ X Ω
Example material numbers (verify)
Littelfuse: SP3051-04 (ESD array family; validate channel count) ·
Nexperia: PESD5V0S2UL (ESD) ·
ST: ESDAxx families (choose per line type; validate capacitance)
For surge-heavy ports, the TVS array may be only one stage of the protection boundary (system-level decision).
Automotive / Long-Cable Ports
ESD + surge stacking · temperature/drift dominated
Key difference
Long-cable exposure and automotive thermal range make drift + consistency as important as initial compliance.
Threshold placeholders
- T range: Tmin/Tmax = X/Y °C (system requirement)
- Drift limits: ΔIleak/ΔC/Δmatch ≤ X across temperature
- IEC-4-2 and IEC-4-5 targets defined per system: X
Example material numbers (verify)
TI: TPD2E007 (automotive-grade family; validate for lines) ·
Nexperia: PESDxx automotive options (choose exact variant) ·
Littelfuse: SP05xx automotive options (choose exact variant)
Select only variants explicitly qualified for the required temperature and reliability grade.
IC Selection Logic: Datasheet Traps → Decision Flow → Part Buckets + Example Material Numbers
Selection is a fixed order. The output is a parameter profile and a device bucket. Example material numbers are provided as starting points only—always verify capacitance test conditions, pinout, package/suffix, and supply consistency.
Step 0 — Required inputs (do not skip)
- Interface family + lane count + routing style (flow-through vs stub-style)
- Eye/IL budget: target Cdiff/IL (placeholders)
- Exposure target: IEC-4-2 and (if needed) IEC-4-5 (placeholders)
- Return domain: shield/chassis/defined system ground (placeholder)
- PHY tolerance: acceptable clamp margin (placeholder)
- Leakage sensitivity (bias/detect pins) + operating temperature range (placeholders)
- Supply/consistency requirement: lot drift tracking + qualification grade (placeholder)
Datasheet traps (common misreads)
- Capacitance conditions: C depends on frequency, bias, and sometimes temperature; do not compare C across parts without matching conditions.
- Clamp current conditions: Vclamp depends on Ipp/test pulse; a “lower” clamp at a different current is not comparable.
- IEC rating equivalence: device-level IEC pass does not guarantee system-level pass; return path and layout dominate.
- Matching disclosure: some datasheets omit max matching or only show typical; enforce Δmatch by measurement if needed.
- “All channels are identical” assumption: multi-channel arrays can differ by routing/footprint; verify across lanes.
Decision flow (must follow this order)
- Rate & eye/IL budget → set target Cdiff ≤ X and IL@f ≤ X.
- Exposure target → set IEC-4-2 X/Y and (if needed) IEC-4-5 X.
- Clamp robustness → set Vclamp ≤ X @ Ipp=Y and Rdyn ≤ X.
- Leakage budget → set Ileak ≤ X @ V=Y, T=Z.
- Matching + package + routing fit → enforce ΔC_match ≤ X and pick footprint style (flow-through vs stub).
- Consistency & supply → require lot tracking and post-stress drift limits (ΔIleak/ΔC/Δmatch ≤ X).
Output: a threshold profile + a device bucket (do not jump to a part number before the profile is defined).
Device buckets (example material numbers — verify package/suffix/spec/availability)
Bucket 1 — Ultra-low-C differential arrays
Priority: Cdiff ↓, Δmatch ↓, IL ↓ · Examples: TI TPD4E02B04 · Nexperia PESD5V0S1UL
Bucket 2 — Flow-through routing ESD arrays
Priority: minimize stub + preserve impedance · Examples: Semtech RClamp0524P · Littelfuse SP3012-04UTG
Bucket 3 — Multi-channel arrays for multi-lane connectors
Priority: cross-lane consistency + matching · Examples: Semtech RClamp0524P · Littelfuse SP3012-04UTG
Bucket 4 — Low-leakage focused parts (bias/detect sensitive)
Priority: Ileak ↓ across temperature · Examples: Nexperia PESD5V0S2UL · ST USBLC6-2SC6 (validate leakage and capacitance conditions)
Bucket 5 — USB3/Type-C oriented ESD arrays (validate per lane)
Priority: high-rate diff support with acceptable C · Examples: TI TPD4E05U06 · TI TPD2EUSB30
Bucket 6 — Automotive/extended-temp qualified families
Priority: drift control + grade compliance · Examples: TI TPD2E007 (family; verify exact variant) · Nexperia PESDxx automotive variants (choose exact)
Mandatory note
Example parts are not a recommendation list. Verify: (1) capacitance vs bias/frequency, (2) clamp conditions, (3) matching specs or measured matching, (4) footprint symmetry, (5) qualification grade and suffix, (6) supply and lot-to-lot consistency.
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FAQs (Troubleshooting, 4-line answers)
Each FAQ stays within the TVS/ESD array boundary: C / ΔC / Rdyn / Vclamp / Ileak / Lvia / return path / symmetry / measurement pitfalls / latent damage. Use placeholders (X/Y/Z) and validate on the real layout and grounding/shield strategy.
Global pass metrics (placeholders):
Cdiff ≤ X pF @ Vbias=Y, f=Z · ΔC_match ≤ X pF (or X%) · Sdd21(IL)@f ≤ X dB · Scc21@f ≤ X dB ·
Vclamp ≤ X V @ Ipp=Y A · Rdyn ≤ X Ω · Ileak ≤ X nA/µA @ V=Y, T=Z ·
BER ≤ X / CRC rate ≤ X · Stub length ≤ X mm · IEC 61000-4-2 contact/air = X/Y kV · IEC 61000-4-5 = X (kV/A + waveform)
TVS changed to “lower C” but ESD failures get worse — check Vclamp first or return path first? Discriminate clamp weakness vs current-path injection (no protocol-layer discussion).
Likely cause: Lower-C device has higher Rdyn/Vclamp under the relevant pulse, or the ESD current return path injects into sensitive ground (long loop / wrong domain).
Quick check: Compare Vclamp@Ipp under the same condition (TLP or standardized pulse) and inspect return path impedance (TVS-to-chassis/ shield vs TVS-to-signal ground). Verify peak at PHY pin with a defined probe method.
Fix: Prioritize lower Rdyn (not only lower C); shorten TVS-to-return with via-in-pad / dense ground vias; route discharge to the correct domain (chassis/shield where defined). Candidate examples to validate: Semtech RClamp0524P, Littelfuse SP3012-04UTG, TI TPD4E02B04 (verify clamp vs C trade).
Pass criteria: Vclamp ≤ X V @ Ipp=Y A AND peak-at-PHY ≤ X V; IEC 61000-4-2 contact/air = X/Y kV pass; post-stress Ileak ≤ X and BER/CRC within X.
Passes IEC-4-2 in lab, but field hot-plug still drops the link — latent damage or layout inconsistency? Convert “passed once” into “stays stable”.
Likely cause: Latent TVS/port damage (Ileak↑, C drift, Δmatch↑) or field return-path differs (shield contact, chassis bonding, cable/fixture differences) causing a new current path.
Quick check: Measure baseline vs post-event Ileak, Cdiff, ΔC_match, and lane-level BER/CRC; log insertion count, polarity, humidity RH, and ground/shield scheme. Compare shield-to-chassis continuity and contact resistance.
Fix: Add a defined discharge route to chassis/shield, lock footprint + assembly control, and add post-stress drift screening (ΔIleak/ΔC/Δmatch). If needed, tighten matching or move to flow-through arrays (e.g., RClamp0524P / SP3012-04UTG per routing style).
Pass criteria: After N insertions + M ESD hits: CRC rate ≤ X (per GB) and training fail ≤ X%; ΔIleak ≤ X, ΔC_match ≤ X under defined RH/T.
After ESD, USB/PCIe trains but CRC spikes under load — measure leakage first or mode conversion first? Separate DC bias shift vs symmetry loss.
Likely cause: Ileak increases and perturbs bias/threshold, or ΔC/ΔL asymmetry increases Diff→CM conversion and jitter under stress.
Quick check: First do two fast discriminators: (1) Ileak vs V,T,RH sweep; (2) VNA lane check of Scc21 (mode conversion) and compare to pre-ESD baseline. Correlate CRC rate vs temperature/humidity.
Fix: If leakage-driven: choose a lower-leakage variant and improve surface cleanliness/coating; if mode-conversion-driven: enforce mirrored geometry and tighter Δmatch arrays (candidates to validate: TI TPD4E02B04, Nexperia PESD5V0S2UL, Semtech RClamp0524P).
Pass criteria: Ileak ≤ X @ V=Y, T=Z, RH=W AND Scc21@f ≤ X dB; CRC rate ≤ X (per GB) under load; post-stress drift ΔIleak/ΔC ≤ X.
Eye looks worse but insertion loss seems unchanged — how to quickly detect TVS mismatch (ΔC)? IL can stay similar while symmetry collapses.
Likely cause: ΔC/ΔL imbalance creates reflections and/or mode conversion; common-mode injection reduces eye even if Sdd21 magnitude appears similar.
Quick check: Use VNA to compare Scc21 (and optionally Sdc21) before/after; use TDR to find asymmetry “bumps” near the TVS footprint; measure ΔC on samples under the same bias/frequency condition.
Fix: Enforce tighter matching specs, use flow-through routing, and mirror vias/pads; reduce branch stub length. Validate candidates with published matching focus (e.g., RClamp0524P, SP3012-04UTG) and confirm ΔC on incoming samples.
Pass criteria: ΔC_match ≤ X pF (or ≤ X%) and Scc21@f ≤ X dB; TDR Zdiff deviation ≤ X Ω; eye height/width ≥ X under defined test.
Same board, different lots behave differently — check device matching first or pad/via process first? Distinguish part distribution shift vs PCB parasitic shift.
Likely cause: Lot-to-lot spread in C/ΔC/Ileak, or PCB process variations changing Lvia/stub geometry and return continuity.
Quick check: Incoming AQL: measure Cdiff, ΔC_match, Ileak distributions under the same conditions; on-board: compare lane S-params/TDR across lots; inspect via drill/plating and solder mask/finish around the TVS footprint.
Fix: Lock exact PN + suffix + footprint, require matching/drift limits in incoming test, and tighten PCB fabrication controls (via count/geometry symmetry, stub control). If multi-channel: verify lane-to-lane uniformity on each lot.
Pass criteria: Lot Cdiff σ ≤ X and ΔC_match ≤ X; lane-to-lane IL variation ≤ X dB; yield ≥ X% with BER/CRC within X over defined T/RH.
Errors appear only in humid conditions — leakage increase or ESD/return path changes? Use RH sweeps to separate surface leakage vs path change.
Likely cause: Surface leakage/contamination raises Ileak, or moisture changes shield/chassis contacts and the discharge path (unexpected current injection).
Quick check: Chamber test: sweep RH and log Ileak/BER/CRC; inspect residues near TVS/connector; check shield-to-chassis resistance/continuity vs RH; compare with “dry-cleaned” boards.
Fix: Improve cleaning and conformal coating strategy (where allowed), increase creepage around sensitive nodes, pick lower-leakage arrays, and define a robust chassis discharge connection. Example candidates to validate: Nexperia PESD5V0S2UL, TI TPD4E02B04 (verify Ileak vs RH/T).
Pass criteria: At RH=X%, Ileak ≤ X and BER/CRC within X; post-RH cycle drift ΔIleak/ΔC ≤ X.
TVS moved closer to connector: ESD passes, but EMI fails — check CM conversion first or ground/shield path first? EMI spikes often come from symmetry + return domain.
Likely cause: Mode conversion rises due to ΔC/ΔL asymmetry near the connector, or the return path now drives common-mode current onto shield/cable.
Quick check: Measure Scc21 and compare to baseline; measure common-mode current on cable (clamp probe) and correlate with EMI peaks; verify the TVS return path is to the intended chassis/shield domain with a short, wide connection.
Fix: Restore perfect symmetry (mirror vias/pads, equal branch length), switch to tighter matching/flow-through arrays, and correct the return domain bonding. If needed, add a common-mode mitigation component as a separate design decision (do not compensate a bad return path).
Pass criteria: Scc21@f ≤ X dB and EMI peak ≤ X (dBµV) under defined setup; ESD target maintained (IEC-4-2 X/Y kV) with BER/CRC within X.
IEC-4-5 surge causes reset/hang, but TVS is not damaged — where did the current go and how to reroute it? Surge is an energy/path problem, not only a “TVS survived” problem.
Likely cause: Surge current couples into system ground/power rails (ground bounce / rail droop) via an unintended return path; the TVS can survive while the system resets.
Quick check: During surge, scope rail droop and ground potential difference (chassis vs signal ground) with a defined probing method; use a current probe to identify the dominant surge return path; verify bonding impedance in the shield/chassis network.
Fix: Provide a low-impedance path to the intended domain (chassis/shield bonding), shorten and widen return traces, add stitching vias, and treat surge as a boundary decision (may require an additional dedicated surge stage elsewhere in the system, without turning this page into an EMC course).
Pass criteria: Under IEC-4-5 target X (kV/A + waveform), no reset/hang; rail droop ≤ X mV; post-event Ileak/ΔC drift ≤ X; functional BER/CRC within X.
Multi-channel TVS array: one differential pair is much worse — channel mismatch or routing asymmetry? Use swap tests to force a root-cause decision.
Likely cause: Intrinsic channel mismatch (ΔC/ΔR) or lane routing asymmetry (branch length, via count, reference plane discontinuity).
Quick check: Do a lane swap (swap channels or remap pairs if possible): if the problem follows the TVS pins, it is channel-related; if it stays with the routing, it is layout-related. Measure lane-by-lane Sdd21/Scc21 and TDR.
Fix: Enforce mirrored geometry and equal via count/placement; select arrays with better documented matching (validate on incoming samples). Candidate examples to validate: Semtech RClamp0524P, Littelfuse SP3012-04UTG.
Pass criteria: Lane-to-lane IL variation ≤ X dB; ΔC_match ≤ X; Scc21@f ≤ X dB; BER/CRC within X across lanes.
Clamp waveform always “looks too high” — probe/ground spring issue or Lvia really too large? Measurement artifacts can dominate fast ESD edges.
Likely cause: Probe inductance/ground lead loop (artifact) or real inductance from via/return loop causes high overshoot (L·di/dt).
Quick check: Repeat with a defined method: ground spring/coax pigtail, controlled bandwidth, fixed reference point. If peak drops dramatically with better probing, it was artifact; if not, suspect Lvia/return loop.
Fix: For real L: via-in-pad, minimize via count, add dense ground stitching, shorten return to the intended domain. For artifact: standardize the probing procedure and record setup parameters.
Pass criteria: Under the defined probing method, Vpeak ≤ X V and Vclamp ≤ X V @ Ipp=Y A; estimated Lvia/loop ≤ X nH (or structural rule met); IEC target passes.
ESD passes, but PHY performance degrades after temperature cycling — what latent-damage indicators are most common? Focus on drift: Ileak/C/Δmatch and link statistics vs T.
Likely cause: Latent junction damage increases Ileak, shifts C, worsens Δmatch, or degrades clamp under temperature, shrinking margin over time.
Quick check: Sweep temperature and log Ileak(V,T), Cdiff/ΔC_match(V,T), and BER/CRC vs T; compare pre-ESD and post-ESD curves. Look for hysteresis or drift after soak.
Fix: Tighten drift screening (post-stress checks), improve return path to reduce injected stress at the PHY, and consider a more robust array (not only low-C). Candidate examples to validate: RClamp0524P, SP3012-04UTG, TI TPD4E05U06 (verify trade-offs).
Pass criteria: Across Tmin/Tmax=X/Y °C: Ileak ≤ X, ΔC_match ≤ X, IL/Scc21 within limits, and BER/CRC ≤ X; post-cycle drift ΔIleak/ΔC ≤ X.
Protection is strong but signal margin is insufficient — what to cut first (C, package, or placement)? Use a fixed priority order to avoid trading into a worse design.
Likely cause: Branch stub + package parasitics + Δmatch consume the eye/jitter budget more than expected; “strong protection” is achieved at the cost of high C or poor symmetry.
Quick check: A/B compare: (1) remove/short the footprint with a controlled coupon, (2) swap to flow-through footprint, (3) swap to tighter matching/lower C variant; measure Sdd21/Scc21, TDR, and BER/eye.
Fix: Priority order: (1) reduce stub/optimize placement & flow-through package, (2) enforce symmetry/Δmatch, (3) reduce C while keeping clamp/IEC. Example candidates to validate by bucket: flow-through RClamp0524P, SP3012-04UTG; low-C TI TPD4E02B04; USB3-oriented TI TPD2EUSB30/TPD4E05U06.
Pass criteria: IL@f ≤ X dB and Scc21@f ≤ X dB with eye/BER meeting X, while IEC-4-2 (X/Y kV) and clamp (Vclamp ≤ X @ Ipp=Y) remain satisfied.
