LVDS / FPD-Link / GMSL SerDes: Single-Coax & Twisted Pair Links
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LVDS / FPD-Link / GMSL SerDes extends camera/display data over a single coax or twisted pair, optionally carrying control and remote power. This page focuses on channel design, margin budgeting, and bring-up/production hardening to keep the link locked with measurable BER, EMI, and sync-consistency targets.
Scope: PHY/link engineering only (channel, EQ/training, PoC coupling, diagnostics, sync). Protocol deep-dives are linked out.
Definition & page scope (Scope guard)
LVDS / FPD-Link / GMSL SerDes is a camera/display physical-link family that transports high-speed data plus remote control and (optionally) remote power (PoC) over a single harness, with equalization/training and diagnostic hooks for production and field reliability.
This section answers
- What this page covers (and what it never expands).
- Whether FPD-Link/GMSL-class SerDes fits a camera/display harness problem.
- Which engineering targets must be defined before picking silicon or cable.
Typical systems
- Sensor/Camera ↔ ECU/SoC (video data + I²C/GPIO control; PoC optional).
- Display panel ↔ Head unit (pixel stream + panel control; power depends on platform).
When this link class is a strong fit
- Harness simplification matters: pin count and skew risk must drop (single coax or single STP).
- Distance/EMI is the constraint: long runs, noisy environments, strict emissions targets.
- Production/field maintainability is required: link lock state, error counters, cable diagnostics.
- Remote power is desired: PoC reduces cabling and enables compact remote modules (camera pods).
When this page will not help (scope guard)
- Not protocol-stack content: no application/driver stacks, no ISP algorithms, no system ECU architecture.
- No deep alternative-link tutorials: other camera links are referenced only as a decision link-out.
- No generic CDR theory chapter: only practical tolerances, measurements, and pass criteria.
Alternative links (mention-only, replace targets with your site paths): MIPI D-PHY/C-PHY, CoaXPress / SLVS-EC.
Owned topics on this page
- Channel/harness: coax vs STP, connectors, impedance, return path.
- Link budget: insertion loss/return loss, equalization/training, margin logic.
- Control/backchannel: tunneling and robust remote configuration.
- PoC (remote power): injection/filtering, hot-plug, ripple-to-BER traps.
- Bring-up, test, production: PRBS/BER, loopback, diagnostics, logging.
Mention-only (linked), not expanded here
- System-level EMI remediation playbooks (only interface-side hooks are covered).
- General CDR theory (only measurable tolerances and settings are used).
- Non-LVDS camera/display PHY families (decision reference only).
Key engineering targets (placeholders)
Distance: × m · Line: coax / STP · Data rate: × Gbps
Target BER: ≤ 1e-x · Lock time: ≤ × ms
Temperature: × °C to × °C · EMI target: Class × (placeholder)
Remote power (PoC): × V · × A · × W (optional)
Architecture map: LVDS vs SerDes; generations & link modes
The key transition is not “parallel vs serial” as a slogan. It is a shift from pin/skew-limited harness design (parallel LVDS) to margin-driven link engineering (SerDes), where equalization, training, and diagnostics make distance, EMI, and production variability measurable and controllable.
Why parallel LVDS hits a wall (engineering consequences)
- Harness complexity: more pairs → larger connectors, higher cost, higher contact-failure probability.
- Skew becomes the first limiter: pair-to-pair delay mismatch consumes setup/hold margin (skew budget: ≤ X ps placeholder).
- EMI scales badly with pair count: parallel pairs act like an antenna array; common-mode conversion is harder to bound.
- Distance/bit-rate coupling: insertion loss + crosstalk + skew stack together; performance degrades unpredictably across harness batches.
What SerDes adds (deliverable capabilities)
- Embedded/forwarded clock + CDR: timing recovery is engineered as a tolerance budget, not a wiring lottery.
- Adaptive EQ & training: CTLE/DFE/presets compensate loss and variation (preset count: X placeholder).
- Diagnostics as a product feature: lock states, error counters, cable open/short hints, temperature/voltage monitors (device-dependent).
- Backchannel control: remote configuration and telemetry without extra wires (I²C/UART/GPIO tunneling patterns).
- Optional remote power (PoC): power injection/filtering integrated into the link architecture for compact remote modules.
Common link modes (system patterns, not protocol details)
Mode A: One-way data + backchannel control
Best for remote camera pods and stable topologies. Verify: lock robustness, backchannel retries, cold/hot boot recovery time (≤ × ms).
Mode B: Dual-link aggregation (higher throughput)
Used when payload grows faster than a single lane budget. Verify: lane-to-lane skew alignment, aggregation stability across temperature and harness batches.
Mode C: Point-to-point vs hub/distribution
Point-to-point maximizes margin. Hub/distribution adds convenience but increases reflection/EMI risk. Verify: channel map, isolation between ports, failure containment.
Capability dimensions to compare (use the same axes later in selection & test)
- Reach (distance margin) · Coax vs STP behavior.
- EMI emissions/immunity hooks (common-mode control, shielding strategy).
- Diagnostics depth (error counters, cable faults, telemetry).
- PoC readiness (power budget, ripple tolerance, hot-plug handling).
- Sync/latency determinism needs (multi-camera alignment, trigger distribution).
Architecture fields (placeholders; reused in later chapters)
Lane count: × · Clocking: embedded / forwarded · Encoding overhead: ×%
Fault tolerance: CRC / retry (×) · Adaptive EQ: CTLE/DFE presets (×)
Built-in test hooks: PRBS / loopback / BER counter (yes/no, device-dependent)
Physical channel: coax vs twisted pair, harness/connectors, impedance & return path
A camera/display SerDes link typically fails for one of three physical reasons: loss (insertion loss), reflection (return loss / discontinuities), or common-mode conversion (return-path and shielding mistakes). This section turns the “harness” into a measurable map: where discontinuities live and what to verify first.
Channel model (measurable primitives)
- IL (Insertion Loss): predicts long-run margin collapse (rate & distance coupling).
- RL (Return Loss): reveals discontinuities (connectors, stubs, vias, transitions).
- Common-mode conversion: exposes shielding/return-path mistakes that look like “random” errors and EMI spikes.
Cable & harness (coax vs STP)
Recommended
- Coax: clear return path + strong shielding; often preferred for longer reach and PoC-friendly layouts.
- Shielded twisted pair (STP): flexible and cost-effective; control pair-to-pair coupling and shield termination consistently.
- Freeze harness part numbers and length bins early; treat “harness batch” as an engineering variable.
Common pitfalls
- Shield discontinuity (pigtail grounds, partial crimps) → common-mode conversion and intermittent errors.
- Uncontrolled stubs (branch, unused connector pinout, “service loop”) → strong reflections that training cannot fully hide.
- Mixed shield strategy across the chain (one end grounded, other floating by accident) → unpredictable EMI and immunity.
Quick checks
- Correlate failure probability with harness length and bend radius (simple A/B).
- Run TDR across the full harness; flag any large spikes at connectors/branches.
- Confirm shield termination is intentional (single-end vs both-ends) and mechanically repeatable.
Connectors & transitions (where reflections are born)
Recommended
- Use connector families specified for the target impedance and bandwidth; control transitions at both ends.
- Keep any “stub” length effectively zero at the connector interface (avoid optional branches).
- Maintain shielding continuity (360° termination where applicable) through the connector stack.
Common pitfalls
- Connector spec mismatch → good on short cable, fails on long cable (reflection + loss stacking).
- “Hidden” branch in harness/adapter → training loops or repeated lock/unlock cycles.
- Ground/shield contact intermittency → errors sensitive to vibration or touch.
Quick checks
- TDR at each connector boundary; compare “good” vs “bad” harnesses to isolate the delta.
- Swap connectors only (same cable) to test reflection sensitivity.
- Inspect shield continuity mechanically (crimp/contact) rather than visually only.
Board entry & return path (impedance + common-mode control)
Recommended
- Route with a continuous reference plane; keep differential geometry stable into the Ser/Des pins.
- Minimize via stubs and pad discontinuities at the board entry; keep test pads controlled.
- Place protection/filtering elements without creating long stubs; preserve symmetry to reduce mode conversion.
Common pitfalls
- Reference-plane breaks → common-mode spikes and EMI; errors become “environment sensitive”.
- Over-sized test pads or probe headers → reflection point inserted right at the receiver.
- Asymmetric protection placement → differential-to-common-mode conversion and reduced eye margin.
Quick checks
- TDR at the board entry (connector → Ser/Des) to detect via/pad discontinuities.
- Compare BER with/without nearby aggressors (DC/DC, motor drivers) to expose common-mode coupling.
- Audit return path continuity (planes/stitching) across the entire entry region.
Channel targets (placeholders)
Zdiff: × Ω (tolerance: ± ×%) · Shield termination: single-end / both-ends
RL (Return Loss): ≥ × dB @ f = × (connector + transitions)
IL (Insertion Loss): ≤ × dB @ f = × (end-to-end harness)
Link budget: loss, eye margin, EQ/training, and tolerance logic
“Short cable works but long cable fails” is a budget problem, not a mystery. Link budget engineering breaks the chain into contributions that can be measured and tuned: Tx energy shaping, channel IL/RL, Rx equalization (CTLE/DFE), plus noise/crosstalk and jitter tolerance. Training is valuable for temperature and batch variation, but it cannot fully mask hard reflections and large stubs.
Budget decomposition (each item: contribution → measure → tune → side effects)
Tx swing / pre-emphasis
Contribution: initial eye opening and ISI shaping.
Measure: near-end eye proxy or BER vs presets (device hooks).
Tune: adjust swing and pre-emphasis presets stepwise.
Side effects: too aggressive can raise EMI and stress the receiver.
Channel IL / RL
Contribution: reach and stability across cable batches.
Measure: VNA (IL/RL) or TDR (discontinuity map).
Tune: remove stubs, fix transitions, improve connector selection.
Side effects: hard reflections can cause training loops and “rate fallback”.
Rx CTLE
Contribution: high-frequency boost to compensate loss.
Measure: BER vs CTLE steps; watch for a “sweet spot” then degradation.
Tune: increase CTLE until BER stops improving, then back off.
Side effects: CTLE can amplify noise and make eye “look bigger” while BER worsens.
Rx DFE
Contribution: cancels ISI in long/reflective channels.
Measure: compare fixed preset vs adaptive; check error bursts vs steady BER.
Tune: enable/limit DFE adaptiveness; lock stable presets for production where possible.
Side effects: over-adaptation can cause mode-dependent behavior and intermittent failures.
Noise / crosstalk
Contribution: random errors, environment sensitivity, EMI coupling.
Measure: BER vs aggressor on/off; temperature and supply ripple correlation.
Tune: shielding/return path fixes, routing symmetry, filtering strategy.
Side effects: EQ may “unmask” noise by boosting the same band as the aggressor.
Jitter tolerance (JTOL)
Contribution: lock robustness and recovered-clock stability under stress.
Measure: device JTOL mask (placeholder) or stress via controlled perturbations.
Tune: reduce reflection sources, stabilize supply/noise, choose stronger tolerance modes.
Side effects: borderline JTOL often shows as “rare dropouts” instead of steady BER.
Symptom cards (avoid wide tables)
Short cable OK, long cable fails
Likely causes: IL too high, RL spikes at connectors, over-stubs.
First check: VNA/TDR for IL/RL; compare harness bins.
Pass criteria: IL@f ≤ × dB; RL ≥ × dB (placeholders).
Training loops or rate fallback
Likely causes: strong reflection points, stub branches, unstable supply/noise.
First check: reflection-point map + fixed preset vs adaptive comparison.
Pass criteria: lock time ≤ × ms; no repeated retrain within × minutes.
Eye looks bigger, but BER is worse
Likely causes: CTLE noise amplification, DFE over-adaptation, measurement artifact.
First check: BER vs CTLE steps; fixed vs adaptive; repeat with different probing/bandwidth.
Pass criteria: BER ≤ 1e-x and stable across presets (placeholders).
Link pass criteria (placeholders)
Eye margin: height/width ≥ ×% (measurement mode: PRBS / live)
BER: ≤ 1e-x (test time: ≥ × s)
Jitter tolerance: mask @ freq (placeholder) · Retrain rate: ≤ × / hour
Clocks, latency & synchronization: forwarded/embedded clock, frame sync, deterministic latency
Multi-camera systems fail synchronization for three practical reasons: recovered clock quality changes with environment, latency contains variable components (lock/buffer), and re-training events are not tracked and re-aligned. This section decomposes clock paths and latency into measurable contributors and defines deterministic-latency conditions.
Clock source modes (forwarded vs embedded)
Forwarded clock (separate clock path)
- Strength: direct phase/frequency relationship across the link.
- Risk: clock path sees its own IL/RL and mode-conversion issues.
- What to log: clock integrity proxy + link state (placeholders).
Embedded clock (CDR recovered)
- Strength: simplified harness; clock travels with data.
- Risk: CDR/PLL noise transfer and lock behavior introduce variability.
- What to log: lock state / retrain count / error counters (placeholders).
Latency decomposition (contributors → measurement → control → failure signature)
Serializer pipeline (tSER)
Measure: device timing hooks (placeholder) · Control: fixed mode/preset (placeholder) · Signature: constant offset shift if mode changes.
Channel propagation (tCH)
Measure: length/bin correlation (placeholder) · Control: harness length bins/part number freeze · Signature: consistent inter-link delta across vehicles.
CDR lock & phase alignment (tLOCK)
Measure: lock-time counter (placeholder) · Control: stable supply/noise, reflection mitigation · Signature: occasional frame slips after retrain events.
Elastic buffer / deskew (tBUF)
Measure: buffer level/deskew state (placeholder) · Control: fixed buffering where supported · Signature: non-deterministic latency when buffering adapts.
Deserializer + SoC capture (tSOC)
Measure: capture timestamps (placeholder) · Control: consistent capture configuration · Signature: “OK on bench, off in system” due to buffering policies.
Sync strategies (single link vs multi-camera)
Single link
- Define a stable reset/bring-up order and treat retrain as a re-alignment event.
- Prefer fixed presets for production if margin allows; log any adaptive changes.
- Pass criteria: link latency ≤ × µs (placeholder).
Multi-camera
- Distribute a frame sync/trigger via sideband GPIO or dedicated sync wiring (placeholder).
- Align using a defined policy (master/slave, star/daisy chain), then re-sync after retrain.
- Pass criteria: inter-link skew ≤ × ns (placeholder).
Timing targets (placeholders)
Link latency: ≤ × µs · Lock time: ≤ × ms
Multi-link skew: ≤ × ns · Retrain events: ≤ × / hour
Control & return channel: I²C/UART/GPIO tunneling, register access, address mapping & resilience
The return channel is a production-critical subsystem: remote configuration, status/fault reporting, GPIO/interrupts, and recovery after link loss. Most “can’t read I²C” issues fall into four buckets: address/mapping mistakes, pull-up/timing limits, ground-reference shifts, and missing re-apply logic after retrain/reset events.
What the return channel typically carries
I²C tunnel: remote register read/write (sensors, serializers, remote PMICs).
GPIO/INT: frame sync, interrupts, status pins, wake signals.
Fault/status: error counters, lock state, diagnostics flags (device-specific).
Control-channel checklist (wiring → pull-ups → timing → capture/logs)
1) Wiring
- Confirm intended ground reference and shielding strategy on the harness.
- Avoid hidden branches/stubs for sideband lines.
- Keep control lines away from high-dV/dt aggressors where possible.
2) Pull-ups
- I²C speed: × kHz (placeholder).
- Pull-up range: ×–× Ω (placeholder) based on total capacitance.
- Validate rise time margin (scope capture) before blaming software.
3) Timing & stretching
- Test at lower speed bins to isolate timing/capacitance limits.
- Check clock stretching behavior (if used) and master timeouts.
- Watch for threshold drift with temperature or power states.
4) Capture & logs
- Log mapping/alias table for each remote node (placeholder).
- Log retry count and NACK rate (placeholder); correlate with link retrain events.
- Capture bus transactions (logic analyzer) on “good vs bad” units for delta isolation.
Symptom cards (fast isolation without wide tables)
I²C cannot read at all
Likely cause: mapping/address mistake, missing pull-ups, link not locked.
First check: scan addresses + verify link state counters (placeholders).
Pass criteria: stable ACK rate; no mapping ambiguity.
Remote config is intermittent
Likely cause: rise time margin, ground reference shifts, retries/timeouts too tight.
First check: reduce I²C speed; measure rise time; correlate with power/EMI states.
Pass criteria: retry count ≤ × per minute (placeholder).
Address conflict across multiple cameras
Likely cause: identical sensor address + missing aliasing/segmentation.
First check: isolate one node at a time; verify alias/mapping table (placeholder).
Pass criteria: unique address map per node; deterministic enumeration.
After link loss, registers revert and system misbehaves
Likely cause: missing re-apply sequence, watchdog not enforced, no read-back validation.
First check: log link-loss/retrain; enforce ordered restore + read-back (placeholders).
Pass criteria: recovery time ≤ × ms (placeholder).
Control-channel targets (placeholders)
I²C speed: × kHz · Pull-up: ×–× Ω · Retry: ×
Link-loss recovery time: ≤ × ms · NACK rate: ≤ × (placeholder)
Remote power over cable (PoC): Bias-T, filtering, hot-plug/inrush & ground bounce
Power-over-cable superimposes DC power onto the same physical link used for high-speed data. A Bias-T network splits the DC path and the AC (data) path, but field failures usually come from dynamic events: inrush during hot-plug, ripple coupling into clock recovery, filter resonance, and unintended return/shield current paths that inject common-mode noise.
PoC network blocks (inject → isolate → filter → protect)
1) Inject
Role: place DC onto the cable without collapsing data margin.
Common pitfall: injection impedance and layout create AC leakage into the power rail.
Quick check: verify DC drop across harness and correlate error counters vs load steps (placeholders).
2) Isolate
Role: keep AC data energy out of the DC rail and keep DC out of sensitive PHY nodes.
Common pitfall: the “split” is not clean due to parasitics and return-path coupling.
Quick check: compare link stability with/without additional local decoupling at the remote node (placeholder).
3) Filter
Role: attenuate ripple and block noise back-injection into the link.
Common pitfall: resonance creates ripple “peaks” at specific bands (worse than no filter).
Quick check: sweep operating states and look for narrow-band ripple bursts vs retrain events (placeholders).
4) Protect / limit
Role: survive short/reverse/hot-plug and limit inrush so the host rail does not sag.
Common pitfall: protection trips repeatedly, causing reset loops and repeated link training.
Quick check: log fault flags + inrush peak and compare against the pass budget (placeholders).
Power-up / power-down sequencing (placeholders)
Recommended power-up order
- Apply PoC and confirm DC rail reaches × V within × ms (placeholders).
- Release remote reset only after ripple stabilizes to ≤ × mVpp (placeholder).
- Start link training/lock and wait for lock state stable for × ms (placeholder).
- Enable control tunneling (I²C/GPIO) after link is stable; apply configuration + read-back (placeholders).
Recommended power-down order
- Freeze/record link state and error counters (placeholders) to enable post-mortem correlation.
- Disable high-activity streams first; then remove remote loads (order placeholder).
- Remove PoC; ensure hold-up time ≥ × ms (placeholder) to prevent brownout oscillations.
PoC budgets (placeholders)
PoC voltage/current: × V / × A · Ripple: ≤ × mVpp
Inrush peak: ≤ × A · Hold-up time: ≥ × ms · Recovery: ≤ × ms
Reliability & protection: ESD/surge, common-mode threats, ground offsets & diagnostics
In real deployments, the link is stressed by ESD strikes, surge transients, ground potential differences, and strong common-mode noise. Interface-side protection must preserve high-speed margin: low-capacitance TVS with tight differential matching, properly placed common-mode chokes, controlled shield termination, and diagnostics that can distinguish open/short/intermittent harness faults from noise-driven retraining.
Threat → symptom → first check (card list; no wide tables)
ESD events
Symptom: instant sparkle, black frame, or link drop on strike.
First check: TVS placement and capacitance matching; inspect connector ground/shield contact quality.
Pass criteria: ESD level ±× kV (placeholder) without retrain bursts.
Surge / load-dump-like transients
Symptom: retrain loops during power events; remote node resets unexpectedly.
First check: PoC rail sag vs inrush; compare recovery time against budget (placeholders).
Pass criteria: surge ×/× µs at × V (placeholders) with stable link.
Common-mode noise & ground offsets
Symptom: worse in rain/high-load states; intermittent errors without obvious harness damage.
First check: shield termination strategy (single/double-end placeholder) and return current paths.
Pass criteria: common-mode range ±× V (placeholder) without BER bursts.
Harness open/short/intermittent
Symptom: bursty error counters, link toggles with vibration or connector movement.
First check: diagnostic flags (open/short/overload placeholders) + wiggle correlation test + shielding continuity.
Pass criteria: retrain frequency ≤ × / hour (placeholder) in the worst-case motion profile.
Interface-side protection stack (connector → PHY)
Low-C TVS (differential-matched)
Keep capacitance low and match the pair; place near the connector to clamp before energy reaches inner structures.
CMC (common-mode choke)
Use where common-mode energy dominates; maintain symmetry and avoid layout that converts CM into differential imbalance.
Shield termination strategy
The shield is a current path; define single-end vs multi-point termination (placeholder) and validate ground offset tolerance.
Diagnostics hooks
Track lock state, retrain count, CRC/error counters, and open/short flags (placeholders) to separate noise from harness faults.
Protection targets (placeholders)
ESD: ±× kV · Surge: ×/× µs at × V
Common-mode: ±× V · Retrain: ≤ × / hour · BER: ≤ 1e-×
Bring-up flow: fastest path from no-lock to stable video
A shortest-path bring-up avoids guesswork by gating layers in order: power stability → control tunnel reachability → link lock → valid frames → quick margin sanity → long-run stability. Each step below is a “stop/go” gate with concrete probes and pass criteria (placeholders) to prevent the common trap: Lock ≠ Margin.
Step 1 — Power rail is stable (PoC / local rails)
Goal: eliminate brownout/UVLO loops before chasing link issues.
Probe: PoC V/I, ripple at remote rail, ramp time, inrush peak (placeholders).
Pass: V = × V, ripple ≤ × mVpp, inrush ≤ × A, no periodic sag (placeholders).
Next: verify control tunnel reachability (Step 2).
Step 2 — Control tunnel works (I²C/UART/GPIO)
Goal: confirm the remote node is reachable and address mapping is correct.
Probe: read fixed ID registers, scan addresses, check NACK rate, IRQ/GPIO status (placeholders).
Pass: consistent read-back; NACK ≤ ×%; no address conflicts (placeholders).
Next: move to link lock (Step 3).
Step 3 — Link locks and stays locked (Lock state + counters)
Goal: achieve stable lock without retrain bursts.
Probe: LOCK pin/status reg, retrain count, CRC/line error counters (placeholders).
Pass: lock time ≤ × ms; retrain ≤ ×/hour; error count ≤ ×/window (placeholders).
Next: validate frames/data (Step 4).
Trap: Lock ≠ Margin
A stable LOCK bit without counter trends can hide a near-edge link. Always gate on counters over time windows (placeholders).
Step 4 — Data is valid (video / frames)
Goal: prove the pipeline produces valid frames, not just link lock.
Probe: video-lock flag, frame/line counters, SoC receiver status (placeholders).
Pass: frame counters monotonic; no sustained drops at target mode (placeholders).
Next: quick margin sanity (Step 5).
Step 5 — Quick margin sanity (EQ / presets)
Goal: detect “edge-of-cliff” configurations early.
Probe: sweep EQ presets (or CTLE/DFE steps), watch counter sensitivity (placeholders).
Pass: meets error thresholds across adjacent presets; margin ≥ × steps (placeholders).
Next: long-run stability (Step 6).
Step 6 — Long-run stability (temperature / vibration / bend)
Goal: surface intermittent faults caused by drift or mechanical stress.
Probe: time series of retrain + error counters vs temperature and motion profile (placeholders).
Pass: relock ≤ ×/hour; burst errors ≤ ×/window; stable video for ≥ × h (placeholders).
Next: if failing, map back to the earliest gate that breaks (power/control/link/sync).
Bring-up pass metrics (placeholders)
Lock time ≤ × ms · BER counter threshold ≤ × / window
Temp-drift relock ≤ × / hour · Margin ≥ × steps
Test & production: PRBS/BER, loopback, margin, diagnostics logs & consistency
Production consistency requires repeatable hooks and traceable logs. Use loopback and PRBS/BER counters to turn “it works on the bench” into measurable margin; then record the minimum field set (harness, presets, lock timing, error distributions, and environment) so failures can be reproduced and binned instead of debated.
Production test checklist (grouped; avoid wide tables)
A) Functional
- What: link lock + video lock (placeholders). Pass: lock within × ms.
- What: control tunnel read/write (placeholders). Pass: stable ID read-back.
- What: no fault flags (open/short/overload placeholders). Pass: 0 active faults.
B) Margin
- What: PRBS/BER counter over duration ≥ × s. Pass: BER ≤ 1e-× (placeholders).
- What: loopback (internal/external). Pass: error-free window (placeholders).
- What: EQ sweep / preset stepping. Pass: margin ≥ × steps (placeholder).
C) Reliability sampling
- What: temperature/voltage corners (placeholders). Pass: retrain ≤ ×/hour.
- What: harness bins (model/length placeholders). Pass: yield ≥ ×% (placeholder).
- What: motion/bend profile sampling (placeholder). Pass: no burst errors.
Mandatory log fields (factory form template)
Harness & build
Harness model / length / batch (placeholders) · Connector type / batch (placeholders) · Assembly station ID (placeholder)
Configuration
EQ preset / training result (placeholders) · PoC configuration (placeholder) · Firmware/ID versions (placeholders)
Timing & counters
Lock time (placeholder) · Retrain count (placeholder) · CRC/BER/error distribution (placeholders) · Fault flags (placeholders)
Environment
Temperature (placeholder) · Supply voltage (placeholder) · Test duration (placeholder) · Operator notes (optional)
Production pass targets (placeholders)
BER ≤ 1e-× · Test duration ≥ × s · Margin ≥ × steps
Yield threshold ≥ ×% · Retrain ≤ × / hour (sampling plan placeholder)
Engineering checklist (Design → Bring-up → Production)
This checklist turns a “works on bench” SerDes link into a reproducible, auditable, and manufacturable system. Each item is written as Action → Pass criteria (criteria placeholders can be replaced with project targets).
1) Design (channel + power + protection + layout) Goal: “Known-good channel” before firmware tuning.
- Pick media (coax 50Ω vs STP 100Ω) → return-path defined, shielding strategy documented.
- Ban stubs (tees, long test pads, branch harness) → reflection points minimized; branch length ≤ [x].
- Connector coding locked → wrong-mate prevented; coding SKU fixed in BOM.
- Define Bias-T blocks (inject / isolate / decouple) → DC path separated from HF path; resonance checked.
- Inrush control added → peak inrush ≤ [x A]; no brownout on host rail.
- Ripple budget allocated → PoC ripple at Ser/Des rails ≤ [x mVpp].
- ESD zoning (connector → TVS/CMC → IC) → discharge current kept out of SerDes reference ground.
- Common-mode control planned → CMC/return strategy present; imbalance risk reviewed.
- Shield termination decided → single-end vs both-ends documented with rationale (noise vs ground loops).
- ESD TVS (HS lines): TI TPD4E05U06-Q1 (quad, low-C).
- Single-line ESD (sideband/GPIO): Nexperia PESD5V0S1ULS (automotive-qualified variant available).
- Common-mode choke (EMI helper): Murata DLW21SN670SQ2# (example CMC family part).
- Signal line CMC family: TDK ACT45B-101-2P-TL003 (example ordering code).
- Power inductors (PoC / rails): Würth 74437324033, Coilcraft XAL7030-103ME (examples; values must match PoC network).
2) Bring-up (fast isolate: power → control → lock → data) Goal: “Lock is repeatable” before image quality tuning.
- Freeze a minimal link (known-good cable + one sensor/display) → lock time ≤ [x ms] across 10 resets.
- Prove control tunnel (I²C/UART/GPIO) → error retries = [0] over [x] transactions.
- Validate EQ preset window → at least [x] adjacent presets pass BER threshold.
- Stress the harness (bend/vibration/temperature ramp) → relock events ≤ [x/hour].
- Do not confuse “locked” with “margin” → margin test required before feature enablement.
3) Production (repeatability + logging + correlation) Goal: “Same test, same result” across stations and weeks.
- PRBS/BER enabled → BER ≤ [1e-x] for ≥ [x s].
- Loopback modes defined → isolate sensor/display vs link vs SoC.
- Margin sweep captured → ≥ [x steps] pass window.
- Cable type / length / vendor / revision.
- Connector coding SKU; shield termination method.
- EQ preset ID; lock time; error counters; temperature.
- PoC rail voltage/current (if used); inrush signature.
- Golden harness maintained → isolate ATE fixture issues.
- Corner replay (temp/voltage/bend) → reproduce within [x min].
- Station correlation → same DUT result variance ≤ [x%].
Applications & IC selection notes (with concrete material numbers)
Selection is driven by media (coax/STP), remote power (PoC), sync/deterministic latency, and diagnostics. The parts below are reference anchors to speed up system planning (exact suffix/package/grade must match project requirements).
- Need PoC? → include Bias-T + inrush + ripple budget + thermal.
- Need multi-camera sync / deterministic latency? → require defined clocking + alignment strategy + logging.
- Need deep diagnostics? → favor SerDes families with link counters, cable fault detect, remote sensors.
- Harsh EMC/ESD? → enforce protection zoning + connector coding + shield termination rule.
Concrete MPN list (examples; verify suffix/package/grade)
- Camera Serializer: DS90UB953-Q1
- Camera Deserializer: DS90UB954-Q1 (dual)
- Camera Hub: DS90UB960-Q1 (quad hub)
- Display Serializer: DS90UB941AS-Q1 (DSI→FPD-Link III)
- Display Deserializer: DS90UB948-Q1 (FPD-Link III→oLDI/LVDS)
- Serializer: MAX9295D (GMSL2/GMSL1)
- Deserializer: MAX9296A (dual serial → CSI-2)
- Deserializer (legacy option): MAX9290 (pairs with coax/STP-capable GMSL serializers)
- HSD coding plugs (TE): 0-2112507-3 (coding C / blue), 0-1823271-1 (coding A / black) (examples)
- FAKRA coax (Rosenberger catalog examples): 59K24K-1M4A4-y, 59K2RK-1M4A4-y (-y = coding placeholder)
- Cable note: keep cable group and sealing option locked in BOM (watersealed vs unsealed).
- ESD array: TI TPD4E05U06-Q1
- ESD single-line: Nexperia PESD5V0S1ULS
- CMC: Murata DLW21SN670SQ2#
- CMC (ordering code example): TDK ACT45B-101-2P-TL003
- Power inductor examples: Würth 74437324033, Coilcraft XAL7030-103ME
- Do not overfit EQ to one harness. Require a passing preset window across cable lots.
- Treat PoC as a jitter source until proven otherwise (ripple/inrush/resonance logging).
- Diagnostics are part of the architecture (counters, fault detect, tunnel robustness).
- Connector coding is a quality lever (wrong-mate prevention reduces “mystery” returns).
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FAQs (troubleshooting only) + structured pass criteria
This section is intentionally narrow: it closes long-tail troubleshooting without expanding the main text. Each answer is Likely cause → Quick check → Fix → Pass criteria. Thresholds use placeholders like [x] for project-specific targets.
