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MIPI D-PHY/C-PHY CSI-2/DSI Link Extension (Bridges & Retimers)

MIPI D-PHY/C-PHY CSI-2/DSI Link Extension (Bridges & Retimers)

← Back to:Interfaces, PHY & SerDes

This page turns MIPI CSI-2/DSI D-PHY/C-PHY “extension problems” into measurable budgets and a device-choice decision: repeater for loss, retimer for jitter tolerance, and bridge for protocol/lane/VC handling. The goal is to make long-reach links stable by controlling loss/skew/jitter and HS↔LP behavior with clear pass/fail criteria.

H2-1 · Scope & Reader Outcomes

This page is a link-extension playbook for MIPI D-PHY / C-PHY carrying CSI-2 / DSI, focused on board-level / short-reach extension using repeaters, retimers (CDR), and bridges. The goal is to make decisions and debugging measurable: error counters, A/B comparisons, and pass criteria placeholders.

Scope
What this page solves (action + constraint + outcome)
  • Extend CSI-2/DSI across FPC / connectors / board-to-board while keeping packet errors / frame drops below a defined acceptance threshold X.
  • Select the lowest-risk architecture under D-PHY/C-PHY: repeater vs retimer (CDR) vs bridge, considering latency, transparency, jitter tolerance, diagnostics.
  • Debug instability with measurable signals: CRC/ECC counters, SoT/EoT/HS-entry flags, lane deskew/skew margin, and A/B tests (short vs long interconnect, low-rate vs full-rate, cold vs warm).
Reader outcomes: identify whether the bottleneck is loss, skew, jitter/PI, or HS↔LP switching, then select the correct extension category and build a verification plan with pass criteria X.
Not-in-scope
Topics intentionally excluded (to prevent page sprawl)
Long-reach automotive SerDes (FPD-Link / GMSL / A-PHY)
HDMI / DisplayPort / SDI video interfaces
Sensor/ISP/panel timing algorithms and system tuning
Only interface-side checks appear here (error counters, A/B tests). System-layer tuning belongs to the application stack pages.
Generic ESD/EMI theory libraries (broad)
Non-MIPI retiming (USB/PCIe/SATA) deep dives
Go to the corresponding retimer/redriver pages under High-Speed Serial & Backplane.
Driver stacks / OS frameworks (V4L2/DRM) implementation details
This page focuses on PHY + bridge behavior, registers, and verification signals—not OS integration.
Start here
Symptom → where to start (anchors prepared for later chapters)
CRC/ECC spikes, frame drops, burst errors
Start: H2-4 (Link budget) → H2-10 (Debug playbook). Output: isolate loss vs jitter vs crosstalk with A/B tests.
HS entry/exit failures, SoT/EoT errors, LP ok but HS fails
Start: H2-8 (HS↔LP switching). Output: verify termination, thresholds, timing margins.
Works at low rate, fails at full rate (or with longer FPC/connector)
Start: H2-2 (Need extension?) → H2-4 (Budget). Output: decide repeater vs retimer.
Warm-up failures, batch-to-batch FPC sensitivity, “only on Mondays” behavior
Start: H2-6 (Clock recovery) → H2-11 (Engineering checklist). Output: add guard bands and production logging.
Pass criteria placeholder style (used throughout): “Error counter ≤ X per Y frames/time under worst-case conditions (rate, temperature, supply noise, interconnect).”
MIPI Link Extension Problem Map Diagram showing CSI-2/DSI endpoints on the left, an extension device in the middle, and interconnect on the right with risk tags for loss, skew, jitter, and HS/LP switching. Endpoints CSI-2 Source DSI Sink D-PHY / C-PHY Extension Device Repeater Retimer (CDR) Bridge Interconnect Connector / FPC Long Trace Board-to-Board Loss Skew Jitter HS↔LP Focus: measurable debugging + architecture selection for MIPI link extension
Figure H2-1 — A page map: endpoints → extension device → interconnect, with the four recurring risk axes (loss, skew, jitter, HS↔LP switching).

H2-2 · When You Need Extension

This section decides whether a layout-only fix is sufficient, or whether an extension device is required—and if required, which class (repeater, retimer (CDR), or bridge) best matches the failure signature with the lowest integration risk.

Trigger conditions
Turn “suspects” into measurable A/B tests
Longer route / FPC / extra connector / board-to-board hop
Observation: high-rate errors rise sharply; reducing lane rate or shortening the interconnect improves stability.
Fast A/B: short jumper vs target interconnect; full-rate vs one-step-lower rate; compare error counters.
Points to: start with repeater (loss/EQ) → escalate to retimer if jitter/PI dominates.
EMI coupling / return-path discontinuity / sensitive mechanical state
Observation: burst errors correlate with nearby aggressors (motors, RF, ESD events) or with cable/FPC touch and flex.
Fast A/B: add temporary shielding/ground stitch; re-route return path continuity; compare error bursts per minute.
Points to: prioritize layout/return-path fixes; device changes alone rarely eliminate field-coupled bursts.
Supply noise / warm-up sensitivity / batch-to-batch behavior
Observation: failures appear after warm-up, under load transients, or only with certain FPC/connector lots.
Fast A/B: isolate rails (temporary LDO), add local filtering, log error counters vs temperature and rail ripple.
Points to: consider retimer (CDR) for jitter tolerance, but treat PI/EMI as a co-design requirement.
Interface conversion required (CSI↔DSI, D-PHY↔C-PHY, lane-count change)
Observation: the link cannot be “transparent” because PHY type, protocol direction, or lane organization must change.
Fast A/B: list the non-negotiable conversions (one item is enough to decide).
Points to: bridge (protocol-aware) + a validation plan for mapping/latency/flags.
Decision corridor
Four gates: classify the fix path in minutes
Gate 1 — Layout-only fix?
Rule: if errors are highly sensitive to shielding/ground/physical position, prioritize return-path and coupling fixes first.
Quick check: add a temporary ground stitch or shield → error bursts should drop measurably.
Gate 2 — Only loss extension?
Rule: if lower rate or shorter interconnect monotonically improves stability, loss/EQ is the primary lever.
Quick check: compare full-rate vs one-step-lower rate error counters. Strong monotonicity points to repeater.
Gate 3 — Need CDR (retimer)?
Rule: if failures correlate with temperature, supply ripple, or load transients, jitter tolerance is the limiting margin.
Quick check: isolate the rail or reduce ripple → stability should improve. If yes, evaluate retimer (CDR) plus PI fixes.
Gate 4 — Need conversion (bridge)?
Rule: if CSI↔DSI, D-PHY↔C-PHY, or lane-count/mapping must change, transparency is broken by definition.
Quick check: list the required conversions (≥1) → select bridge and validate mapping/latency/flags.
Pass criteria placeholder: after the chosen fix path, total link errors must remain ≤ X per Y frames/time at the target lane rate, worst-case temperature, and worst-case interconnect assembly.
Fast classification
Symptom → discriminator → next step (with measurable outputs)
Pattern A — Low rate OK, high rate fails
Likely cause: link margin dominated by insertion loss / reflection or crosstalk that scales with edge rate.
Quick discriminator: step down lane rate by one notch and compare CRC/ECC per minute; monotonic improvement indicates “budget-first”.
Next step: repeaters first (EQ), then evaluate retimer only if jitter/PI sensitivity persists.
Pass criteria: error counter ≤ X over Y frames at target rate.
Pattern B — Burst errors / “only when environment changes”
Likely cause: EMI coupling, return-path discontinuity, or mechanical modulation of the interconnect.
Quick discriminator: add temporary shield/ground stitch and re-measure burst density; strong improvement indicates coupling dominance.
Next step: fix layout/return path before changing architecture; retimers do not remove coupled noise sources.
Pass criteria: burst errors ≤ X per minute under worst-case aggressor conditions.
Pattern C — LP reliable, HS unreliable (SoT/EoT / HS-entry flags)
Likely cause: HS termination/threshold/timing margin, or skew/deskew limit near HS entry.
Quick discriminator: check whether HS-entry errors appear before payload errors; if yes, treat as HS entry margin rather than protocol mapping.
Next step: validate HS↔LP switching behavior, termination, and lane skew budget before adding complex bridges.
Pass criteria: HS entry succeeds across temperature with ≤ X switching failures per Y cycles.
MIPI Extension Decision Flow Flowchart that routes symptoms through decisions: rate sensitivity, environment sensitivity, need for CDR, and need for conversion, resulting in repeater, retimer, or bridge. Start: observe the failure signature CRC / Drops HS Entry Fail Warm / PI Need Convert Rate sensitive? lower rate helps YES Repeater NO Environment sensitive? YES Layout Fix NO Need CDR? PI/Temp linked YES Retimer Bridge Output: choose the simplest architecture that closes the measured margin gaps
Figure H2-2 — A decision corridor: rate sensitivity → environment sensitivity → CDR need → conversion need, mapping to repeater/retimer/bridge.

H2-3 · D-PHY vs C-PHY Essentials (Extension-Relevant Differences)

This section keeps only the PHY differences that change extension feasibility, failure signatures, and device selection. It avoids protocol deep dives and focuses on four decision axes: clocking, skew sensitivity, mode behavior, and extension implications.

D-PHY
Clock lane + data lanes; HS/LP switching dominates many extension failures
  • Clocking: a dedicated clock lane defines the sampling reference. Extension devices may treat clock/data differently; clock-path integrity often becomes the first limiter.
  • Skew: lane-to-lane skew grows quickly across connectors/FPC. Deskew limits become visible as HS-entry instability or lane-specific errors.
  • Mode: explicit LP↔HS transitions create threshold/timing traps. “LP stable, HS unstable” strongly points to termination/entry margin rather than protocol mapping.
  • Extension implication: loss-driven issues often fit a repeater; temperature/supply-linked instability escalates toward a retimer (CDR); any PHY/protocol/lane re-organization requires a bridge.
Verification focus: monitor HS entry/exit flags and compare error counters under rate step-down, short/long interconnect A/B, and cold/warm conditions.
C-PHY
Triox (embedded clock); trio balance and coupling shape extension robustness
  • Clocking: clock is embedded in each trio. Extension feasibility depends on how well the trio maintains symmetry through the interconnect.
  • Skew: trio imbalance and coupling degrade margin without looking like a “clock-lane problem”. Sensitivity is often highest across asymmetric connectors and non-uniform return paths.
  • Mode: low-power behaviors still matter, but the dominant trap is not a separate clock lane— it is trio integrity during entry/hold across flex and EMI.
  • Extension implication: “C-PHY supported” does not guarantee stable extension. Confirm whether the device is transparent, whether it retimes, and whether it changes lane/trio organization (mapping/deskew/diagnostics).
Verification focus: A/B compare different interconnect builds (connector lots, FPC flex states), and correlate errors with mechanical/EMI conditions to reveal trio-coupling dominance.
D-PHY vs C-PHY Link Form Side-by-side diagram showing D-PHY with a dedicated clock lane and multiple data lanes, and C-PHY with trios carrying embedded clock. D-PHY C-PHY TX/RX RX/TX Clock lane Data lanes (xN) LP HS TX/RX RX/TX Trio (embedded clock) Trios (xN) LP HS Extension impact: clocking path, skew sensitivity, LP↔HS behavior, and device transparency/retiming
Figure H2-3 — D-PHY uses a dedicated clock lane; C-PHY uses trios with embedded clock. These forms change skew sensitivity and extension-device requirements.

Link extension failures can be decomposed into five measurable budget items. Each budget item below is written as a consistent, actionable 4-line block: Phenomenon → Quick check → Fix direction → Pass criteria (threshold placeholder X).

Budget: Loss
Insertion loss / reflections vs equalization headroom
Phenomenon
High-rate fails while lower rate is stable; longer interconnect (extra connector/FPC) sharply increases errors.
Quick check
A/B: short jumper vs target interconnect; full-rate vs one-step-lower rate; compare CRC/ECC density.
Fix direction
Restore impedance/return-path continuity first, then add controlled EQ (repeater). Escalate to retimer only if jitter/PI coupling remains dominant.
Pass criteria
Total link errors ≤ X per Y frames/time at target rate and worst-case interconnect build.
Budget: Skew
Lane-to-lane timing alignment vs deskew tolerance
Phenomenon
Lane-specific errors, intermittent HS entry, or sensitivity to connector/FPC flex and lane ordering.
Quick check
Compare multiple interconnect assemblies (different FPC lots/flex states). Check whether HS-entry flags fail before payload errors.
Fix direction
Improve length/symmetry and return-path balance across lanes/trios; confirm device support for remap/polarity/deskew where PCB cannot guarantee alignment.
Pass criteria
Lane alignment failures ≤ X per Y HS entries or resets across temperature and interconnect variation.
Budget: Jitter
Sampling window vs RJ/DJ/SSC and supply-induced modulation
Phenomenon
Errors correlate with warm-up, load transients, or supply ripple; rate step-down may not fully stabilize the link.
Quick check
Temporarily isolate/clean the rail (LDO or added filtering). Log error counters vs temperature and measured ripple.
Fix direction
Reduce the noise source first (PI/EMI co-design). Evaluate retimer (CDR) only as a margin tool, not as a substitute for rail integrity.
Pass criteria
Error density ≤ X per Y frames/time at worst-case temperature and worst-case load transients.
Budget: XTALK
Coupling and return-path integrity vs burst-error susceptibility
Phenomenon
Burst errors triggered by nearby aggressors, physical touch, or mechanical movement; errors cluster in time rather than appearing uniformly.
Quick check
Add temporary shielding/ground stitch or improve return continuity; re-measure burst density (errors/min) under the same aggressor conditions.
Fix direction
Restore reference-plane continuity, optimize connector ground pinning, and enforce spacing/guarding. Treat device selection as secondary until coupling is controlled.
Pass criteria
Burst errors ≤ X per minute (or per event) in worst-case EMI/mechanical scenarios.
Budget: HS↔LP
Mode-switch margin vs thresholds/delays introduced by extension devices
Phenomenon
LP is reliable but HS entry fails; switching-time errors appear before payload errors; reset/wake sequences are fragile.
Quick check
Check whether HS-entry flags (SoT/EoT/entry) fail before CRC/ECC. A/B compare reset and wake timing sequences.
Fix direction
Validate termination, thresholds, and entry/exit timing first. Confirm that any extension device preserves mode behavior and does not violate entry margins.
Pass criteria
HS↔LP switching failures ≤ X per Y cycles across temperature and interconnect variation.
Link Budget Margins (Concept) Bar chart concept with five rows: loss, skew, jitter, crosstalk, and mode switch; each row shows used budget and remaining margin without numeric values. Budget Margins (Concept: no numeric values) Used Margin Loss OK Skew Risk Jitter OK XTALK Risk HS↔LP OK Use the five budgets to route debugging: each margin gap maps to a specific fix lever and a pass threshold X
Figure H2-4 — Margin-only budget bars (no numbers): Loss, Skew, Jitter, Crosstalk, and HS↔LP switching.

H2-5 · Extension Architectures (Repeater vs Retimer vs Bridge)

Extension devices fall into three architectural classes with different “what changes / what stays the same” properties. The sections below summarize each class using a consistent 5-line engineering format: What it changes, What it preserves, Typical failure, Best for, Avoid when.

Linear Repeater / Redriver
Improves amplitude / frequency response; does not re-time sampling
What it changes
Adds gain and/or EQ (e.g., CTLE-like shaping) to recover edge rate and eye opening caused by interconnect loss.
What it preserves
Protocol transparency and sampling timing behavior (no CDR). The link still “behaves like a wire,” just with more analog headroom.
Typical failure
The eye looks larger but errors increase because the device also amplifies coupled noise, supply-induced modulation, or reflections that were already dominant.
Best for
Loss-dominated links where errors scale monotonically with length/rate and where jitter/PI coupling is not the primary limiter.
Avoid when
Failures correlate with temperature, load transients, or supply ripple; or HS↔LP entry is fragile (threshold/timing margins cannot be fixed by linear EQ).
Retimer / CDR-based
Rebuilds sampling clock and re-times data; introduces lock behavior and latency
What it changes
Uses CDR/PLL to recover timing and re-clock data, often improving jitter tolerance by restoring a clean sampling reference.
What it preserves
Many designs keep protocol framing transparent, but electrical “wire-like” behavior no longer applies because acquisition/lock dynamics and re-timing exist.
Typical failure
Intermittent drops or frame loss tied to state transitions (power-up, warm state, sleep/wake) when lock boundary conditions are not met.
Best for
Jitter-dominated links where errors correlate with supply/temperature/transients and where restoring a timing reference increases usable sampling margin.
Avoid when
The system cannot tolerate added latency/lock time, or frequent resets/wakes cannot be controlled or validated across temperature and production variation.
Protocol-aware Bridge
Converts or re-frames links (CSI↔DSI, D↔C, lane count/map); adds state machines and buffering
What it changes
Handles packet/framing and lane organization (CSI-2↔DSI, D-PHY↔C-PHY, lane mapping/count), often re-creating the PHY at the output side.
What it preserves
End functionality (camera-to-processor or processor-to-panel) can remain intact, but timing and error visibility may change due to buffering and re-framing.
Typical failure
Initialization sensitivity (HPD/wake/reset sequencing) and “symptom translation” where a physical-layer margin issue appears as a protocol-level error.
Best for
Structural mismatches: PHY conversion, lane count change, lane remap, or a required CSI↔DSI functional bridge that cannot be solved by pure signal conditioning.
Avoid when
The problem is purely loss/jitter margin and can be solved with a simpler architecture; added complexity increases validation scope, power, and debugging cost.
Extension Architecture Signal Paths Three-row diagram: repeater uses EQ/AMP, retimer uses CDR and reclocking, bridge uses packet handling, lane mapping, and PHY recreation. Extension Architectures — Signal Path View Repeater / Redriver Retimer (CDR) Bridge (Protocol-aware) Input Output EQ / AMP Analog shaping T Input Output CDR RECLK Retimed Input Output Packet VC/DT Lane Map PHY Reframed
Figure H2-5 — Repeater shapes analog loss; retimer rebuilds timing; bridge re-frames packets and re-creates PHY outputs.

H2-6 · Robust Clock Recovery (What Retimers Fix — and What They Can Break)

“Robust clock recovery” means stable acquisition and stable hold across power-up, warm state, and sleep/wake cycles. Retimers can restore sampling margin by rebuilding the timing reference, but they also introduce loop bandwidth trade-offs and lock boundary conditions.

Common traps (x3)
Retimers improve timing margin, but only if boundary conditions are controlled
Trap #1 — “A retimer removes the noise source”
Impact: supply/EMI-induced modulation still reaches the sampling process and can destabilize lock.
Correct approach: confirm power and return-path integrity before loop tuning.
Trap #2 — “Steady-state test is enough”
Impact: lab-long runs can pass while field sleep/wake cycles fail (state-transition boundary condition).
Correct approach: validate repeated power-up/warm/wake loops and track pass rate.
Trap #3 — “Loop BW is chosen only by lock time”
Impact: a wide loop follows noise; a narrow loop cannot track drift/transients.
Correct approach: choose BW based on noise spectrum + state transitions, not only “fast vs slow”.
Tuning order
Control boundary conditions first, then adjust loop parameters
Step 1 — Reference sanity
Verify reference stability and confirm that the retimer is not being asked to “track” a modulated reference.
Step 2 — Power integrity correlation
Correlate errors with ripple/transients; isolate rails temporarily to confirm whether jitter is supply-induced.
Step 3 — Coupling / trio balance / return path
Stabilize return-path continuity and coupling first (especially for C-PHY trio symmetry). Treat loop tuning as a second-order tool.
Step 4 — Loop BW and lock policy
Choose loop bandwidth to avoid “following noise” (too wide) and “missing drift/transients” (too narrow). Validate on power-up, warm state, and sleep/wake loops.
Loop BW intuition: Too wide → follows noise Too narrow → misses drift
CDR / PLL Loop (Concept) Block diagram showing PD, LPF, VCO, Divider in a feedback loop with jitter in and jitter out arrows and lock/acquire states. CDR / PLL Loop (Concept) Data in Ref / Clk PD LPF VCO DIV jitter in jitter out Recovered clk Retimed data Acquire Lock
Figure H2-6 — Conceptual CDR/PLL loop: PD → LPF → VCO → DIV with feedback. Robustness depends on boundary conditions and loop bandwidth choice.

H2-7 · Lane Extension Mechanics (Lane Count, Mapping, Polarity, Deskew)

Lane extension fails most often due to mapping mismatches and alignment gaps, not because the protocol is “unknown”. Treat lane work as a controlled, testable transformation: lane-count plan → order/polarity → deskew → CSI/DSI identity checks.

Lane-count change
x2↔x4 is a margin trade: per-lane rate vs alignment burden
x4 → x2 (lane reduction)
Effect: higher per-lane rate increases loss sensitivity and jitter pressure, shrinking usable margin.
Risk signature: high-speed modes fail first; errors scale rapidly with temperature/supply ripple.
Pass criteria: per-lane margin ≥ X (placeholder).
x2 → x4 (lane increase)
Effect: lower per-lane rate improves loss margin, but alignment/deskew becomes stricter across connectors/cables.
Risk signature: intermittent frame/CRC faults under movement, thermal drift, or connector tolerances.
Pass criteria: lane-to-lane skew ≤ X (placeholder).
Who fixes what
Separate PCB-solvable issues from device-required capabilities
PCB can usually solve
  • Lane order planning at connectors (pin map matches endpoint expectations)
  • Length matching to control skew (routing symmetry + return-path continuity)
  • Reducing coupling hot-spots (guard/spacing and stable reference plane)
Device support is required when
  • Runtime deskew is needed across cables/hinges or hot-plug environments
  • Lane remap must be changed without respinning the PCB
  • Polarity handling is not tolerant at endpoints and must be corrected in silicon
Scope guard: CSI-2 VC/DT and DSI mode specifics are treated only as identity and buffering risk checks. Full protocol encyclopedias belong on dedicated CSI-2/DSI pages.
Mapping Checklist
Validate physical transformation before blaming the protocol
1) Lane-count & rate plan
Confirm the new per-lane rate and required margin; ensure “rate-up” cases are not silently over budget. (margin ≥ X)
2) Lane order (0…N)
Verify lane0..laneN mapping through every connector/cable. Treat “one swap” as a deterministic fault, not a random error.
3) Polarity (per differential pair)
Confirm whether endpoints tolerate polarity inversion. If not, the mapper must correct it (capability check).
4) Deskew budget
Confirm lane-to-lane skew is within compensable range across temperature, bending, and connector tolerance. (skew ≤ X)
5) CSI-2 identity (VC/DT)
Confirm VC/DT expectations match at both ends; treat mismatches as “wrong stream identity”, not “signal noise”.
6) Error visibility (flags/counters)
Ensure packet error flags/counters can be read to distinguish deterministic mapping faults from margin-related sporadic faults.
7) Frame sync sanity
Validate stable frame/line boundaries. A stable electrical link can still fail functionally when boundaries are re-timed or buffered incorrectly.
Lane Mapping and Deskew (Concept) Four input lanes pass through an input PHY into a lane mapper with swap, polarity, and deskew tags, then to output lanes and output PHY. Lane Mapping + Polarity + Deskew (Concept) Input PHY Output PHY Lane Mapper SWAP POL DESKEW lane0 lane1 lane2 lane3 lane0 lane1 lane2 lane3 Check: order polarity skew VC/DT error flags frame sync
Figure H2-7 — Lane mapping is a controlled transformation: order, polarity, and deskew must be validated end-to-end across connectors and cables.

H2-8 · HS/LP Mode Switching & Low-Power Pitfalls (LP OK, HS Fails)

Many bring-up failures are not “protocol issues” but LP↔HS boundary condition problems: LP levels can look correct while HS entry collapses due to pull-ups, leakage, IOFF behavior, termination changes, ESD parasitics, or power-up timing. Debug should start from symptoms and probe points.

Symptom: LP config works, but HS request shows no stable transition
Most likely cause: LP pull-up/leakage shifts the effective threshold, IOFF/partial-power creates back-bias, or power-up sequence leaves the link in an invalid entry window.
Quick probe point: LP level at the far end, rail ramp timing, and any clamp/ESD leakage path on LP nodes.
Symptom: HS entry occurs, then immediate CRC/frame errors
Most likely cause: HS termination/common-mode behavior changed by an extender/bridge, connector discontinuity, or ESD/TVS parasitics that load the HS edge.
Quick probe point: HS clock presence, termination equivalence, and whether the data eye collapses only after entry.
Symptom: intermittent failures after warm-up or under load transients
Most likely cause: leakage and threshold drift with temperature, or supply ripple modulating entry/termination behavior at the HS boundary.
Quick probe point: correlate errors with rail ripple, temperature points, and HS eye changes over time.
Symptom: hot-plug causes failure; cold boot recovers
Most likely cause: common-mode/ground shift and transient conditions push the state machine into an invalid path, especially when termination and ESD networks are near the boundary.
Quick probe point: LP/HS node waveforms during insertion, common-mode spikes, and whether HS entry repeats consistently.
Probe priority
Probe LP level → HS clock → data eye (in that order)
LP level
Confirms pull-ups/leakage/IOFF and entry threshold integrity in real wiring, not only at the source.
HS clock
Confirms HS entry actually happened and whether termination/common-mode conditions are compatible after extension.
Data eye
Confirms whether the failure is loss/jitter/coupling dominated after HS entry. Use margin placeholders as pass criteria: X.
LP ↔ HS Switching (Simplified) Four-state diagram: LP idle, HS request, HS active, Exit; probe point cards for LP level, HS clock, and data eye. LP ↔ HS Switching (Simplified) + Probe Points LP idle HS request HS active exit entry lock exit Probe points: LP level HS clock Data eye TERM
Figure H2-8 — Debug HS failures by probing LP level, HS clock, and data eye at the far end; HS entry is dominated by thresholds, termination, and transients.

H2-9 · PCB & Interconnect Co-design (MIPI Extension-Critical Only)

Co-design problems in MIPI extension are usually not subtle: return-path breaks, connector/FPC asymmetry, power-to-jitter coupling, and “protective” ESD networks that silently load the differential channel. This section focuses only on the mistakes that most often collapse HS margin across connectors, cables, and cross-board paths.

Return path / Ref plane
Reference continuity beats “perfect impedance” on paper
Do
  • Keep a continuous reference plane under the diff pair across the connector region
  • Use ground stitching (via fence) near transitions to preserve return current
  • Control layer changes: provide an explicit return bridge when swapping reference layers
Don’t
  • Route across plane splits/voids without a defined return path (classic HS margin killer)
  • Create long stubs at transitions (uncontrolled discontinuities scale with rate)
  • Assume “diff pair cancels everything” when return current has no place to flow
Quick check: look for any HS segment crossing a reference split/keep-out near connectors and FPC launches.
Connector / FPC
Symmetry + ground distribution define stability under bending and tolerance
Do
  • Maintain pair symmetry through the connector footprint and via escape
  • Place ground pins/grounds adjacent to high-speed lanes when available
  • Prefer controlled transitions (short, matched, with nearby reference) at FPC launches
Don’t
  • Route one side with extra meanders near the connector while the other stays straight
  • Leave high-speed lanes surrounded by sparse ground (coupling hot-spot at the interface)
  • Ignore “bend sensitivity” — intermittent burst errors often point to connector/FPC coupling
Quick check: if light bending/pressing on the FPC changes errors, treat it as coupling/return-path/launch geometry first.
Power → Jitter
Make the coupling observable: correlate rail ripple with error bursts
Do
  • Measure ripple at the extender/bridge supply pins (near decoupling), not only at the regulator
  • Log error counters while capturing rail ripple to find time correlation
  • Compare near-end vs far-end behavior (short link vs extended link) to isolate coupling paths
Don’t
  • Assume “voltage looks fine” without bandwidth-aware probing and ground-spring technique
  • Change equalization/retiming settings before verifying power integrity at the critical device
  • Treat intermittent failures as protocol issues when they follow load transients or EEE/clock events
Quick check: error bursts that align with rail ripple spikes point to jitter injection rather than deterministic mapping faults.
ESD / TVS at interface
“Protection” can silently kill the eye: parasitics and mismatch dominate
Do
  • Use low-cap, tightly matched differential protection parts when HS margin is tight
  • Place interface protection with controlled geometry (short, symmetric, minimal stubs)
  • Validate that the two sides are electrically matched (avoid differential imbalance)
Don’t
  • Add high-C protection by default on HS lanes without verifying eye impact at target rate
  • Create long stubs to protection devices (stubs scale into notches at high speed)
  • Mix unmatched parts/placements across the two lines (differential becomes common-mode trouble)
Quick check: if HS fails at entry or margin collapses after adding protection, suspect parasitic C and mismatch first.
PCB & Interconnect Co-design (Concept) Two-panel diagram: recommended layout and common mistakes for differential pairs through connector/FPC and TVS placement. PCB + Interconnect Co-design (MIPI Extension-Critical) Recommended Common mistakes Ref plane (continuous) return path intact Diff pair Connector GND pins FPC / Cable (symmetric) TVS (matched) short / symmetric Plane split / void return path broken X Diff pair Connector Sparse GND FPC / Cable (coupling) TVS (high C) Mismatch
Figure H2-9 — The biggest extension failures come from return-path breaks, asymmetric launches, and protection parasitics that silently load HS lanes.

H2-10 · Validation & Debug Playbook (Engineering Runway)

Debug becomes fast when verification is layered and repeatable: PHY entry → lane alignment → packet integrity → frame stability. Each step below includes a pass criterion placeholder X so the playbook can be turned into a lab checklist.

10-step runway
From symptom → classification: Loss / Skew / Jitter / Mode switch / Mapping
Step 1
Freeze the symptom and setup
Goal: define the failure mode (no video / flicker / frame drop / CRC).
Quick check: lock the config (rate, lanes, mode, extender settings).
Probe/Log: start error counters + timestamped logs.
Pass criteria: symptom classification is stable for ≥ X minutes.
Step 2
Validate HS entry (LP↔HS)
Goal: confirm HS entry happens reliably.
Quick check: check LP levels at far end; verify HS clock presence.
Probe/Log: LP level, HS clock, entry timing (placeholder).
Pass criteria: HS entry success rate ≥ X%.
Step 3
Check lane alignment & deskew
Goal: prove alignment is within deskew capability.
Quick check: confirm lane order + polarity mapping end-to-end.
Probe/Log: lane deskew/alignment counters (if available).
Pass criteria: deskew errors = 0 over ≥ X frames.
Step 4
Packet integrity snapshot
Goal: decide if failures are electrical (sporadic) or deterministic (mapping/identity).
Quick check: read CRC/ECC counters; note SoT/Sync-related errors.
Probe/Log: CRC/ECC rate, SoT/Sync errors, burst length (placeholder).
Pass criteria: CRC/ECC ≤ X per X seconds.
Step 5
A/B: short vs extended
Goal: isolate interconnect-driven loss/skew/coupling effects.
Quick check: compare short direct link vs long/connector/FPC link.
Probe/Log: error counters and any eye/clock proxy measurement.
Pass criteria: delta error rate between A/B ≤ X.
Step 6
A/B: bypass vs extender/bridge
Goal: decide whether the device adds the failure (mode switch / CDR / mapping).
Quick check: run direct path and extended path with the same cabling if possible.
Probe/Log: HS entry stability, lock behavior, counter signatures.
Pass criteria: extender-induced failures ≤ X.
Step 7
Rate sweep: reduce speed to classify margin
Goal: confirm whether the problem scales with bandwidth (loss/jitter dominated).
Quick check: test a lower lane rate or fewer lanes if supported.
Probe/Log: error slope vs rate (placeholder).
Pass criteria: stable operation at target rate with margin ≥ X.
Step 8
Make it repeatable: inject a controlled stress
Goal: convert intermittent faults into reproducible triggers.
Quick check: apply light FPC bend, small load transient, or temperature shift (controlled).
Probe/Log: burst error timing and which counters spike first.
Pass criteria: trigger causes consistent signature within ≤ X seconds.
Step 9
Attribute the root class
Goal: map the signature to a dominant class: loss / skew / jitter / mode switch / mapping.
Quick check: use: rate sensitivity → loss/jitter; deskew errors → skew; deterministic wrong output → mapping/identity.
Probe/Log: top-3 counters and first-failing layer (entry/align/integrity/frame).
Pass criteria: root class confidence ≥ X.

H2-10 · Validation & Debug Playbook (Engineering Runway)

Debug becomes fast when verification is layered and repeatable: PHY entry → lane alignment → packet integrity → frame stability. Each step includes a pass criterion placeholder X.

10-step runway
From symptom → classification: Loss / Skew / Jitter / Mode switch / Mapping
Step 1
Freeze the symptom and setup
Goal: define the failure mode (no video / flicker / frame drop / CRC).
Quick check: lock the config (rate, lanes, mode, extender settings).
Probe/Log: start error counters + timestamped logs.
Pass criteria: classification stable for ≥ X minutes.
Step 2
Validate HS entry (LP↔HS)
Goal: confirm HS entry happens reliably.
Quick check: check LP levels at far end; verify HS clock presence.
Probe/Log: LP level, HS clock, entry timing (placeholder).
Pass criteria: HS entry success rate ≥ X%.
Step 3
Check lane alignment & deskew
Goal: prove alignment is within deskew capability.
Quick check: confirm lane order + polarity mapping end-to-end.
Probe/Log: lane deskew/alignment counters (if available).
Pass criteria: deskew errors = 0 over ≥ X frames.
Step 4
Packet integrity snapshot
Goal: separate deterministic identity faults from margin-driven sporadic errors.
Quick check: read CRC/ECC counters; note SoT/Sync-related errors.
Probe/Log: CRC/ECC rate, SoT/Sync errors, burst length (placeholder).
Pass criteria: CRC/ECC ≤ X per X seconds.
Step 5
A/B: short vs extended
Goal: isolate interconnect-driven loss/skew/coupling effects.
Quick check: compare short direct link vs long/connector/FPC link.
Probe/Log: error counters and any clock/eye proxy measurement.
Pass criteria: delta error rate between A/B ≤ X.
Step 6
A/B: bypass vs extender/bridge
Goal: determine whether the device introduces the failure (mode switch / CDR / mapping).
Quick check: test direct path and extended path with identical interconnect if possible.
Probe/Log: HS entry stability, lock behavior, counter signature.
Pass criteria: extender-induced failures ≤ X.
Step 7
Rate sweep: reduce speed to classify margin
Goal: confirm rate sensitivity (loss/jitter dominated) vs deterministic mapping faults.
Quick check: try a lower lane rate or fewer lanes if supported.
Probe/Log: error slope vs rate (placeholder).
Pass criteria: stable at target rate with margin ≥ X.
Step 8
Make it repeatable: inject controlled stress
Goal: convert intermittent faults into reproducible triggers.
Quick check: apply light FPC bend, small load transient, or temperature shift (controlled).
Probe/Log: which counter spikes first (entry/align/integrity/frame).
Pass criteria: trigger reproduces within ≤ X seconds.
Step 9
Attribute the dominant root class
Goal: map the signature to Loss / Skew / Jitter / Mode switch / Mapping.
Quick check: rate sensitivity → loss/jitter; deskew errors → skew; deterministic wrong output → mapping/identity.
Probe/Log: top-3 counters + first-failing layer.
Pass criteria: root class confidence ≥ X.
Step 10
Lock the fix with a pass window
Goal: prove the fix holds across stress and time.
Quick check: re-run Steps 2–8 after the change (layout, protection, settings).
Probe/Log: error counters + temperature/load/bend sweep notes.
Pass criteria: 0 critical errors over ≥ X hours under defined stress.
Debug Flow (Symptom → Root Class) Flowchart from symptom entry points to layered checks and final root cause classes: loss, skew, jitter, mode switch, mapping. Debug Flow: Symptom → Layer → Root Class No video Flicker Frame drop CRC Layer 0: HS entry / mode switch Layer 1: lane alignment / deskew / mapping Layer 2: packet integrity (CRC/ECC/SoT signatures) Layer 3: frame stability (burst / time / temperature / bend) Loss Skew Jitter Mode switch Mapping
Figure H2-10 — A layered playbook turns “random failures” into a classified root class: Loss, Skew, Jitter, Mode switch, or Mapping.

H2-11 · Engineering Checklist (Design → Bring-up → Production)

This section turns the extension topics of this page into a closed-loop checklist: design assumptions become bring-up measurements, then become production guard bands and field diagnostics. Each item is written to be executable and auditable.

Design checklist (freeze assumptions early) Definition of done: the architecture, interconnect, power/clock, and protection choices have no hidden “must-fail” risks.
  • Classify the extension need before schematics: loss-only extension → ReDriver/Repeater (e.g., Diodes PI2MEQX2505 / PI2MEQX2503A); jitter/clock tolerance need → Retimer (e.g., TI SN65DPHY440SS / SN75DPHY440SS); lane/format/aggregation need → Bridge/Protocol-aware (e.g., Lattice CrossLink/CrossLink-NX families such as LIF-MD6000-6KMG80I, LIFCL-40-9BG400C as design-in platforms). Pass: a single architecture is chosen and justified by the dominant failure mode (X).
  • Lock the “transparent vs non-transparent” expectation: identify whether the chosen device preserves packet boundaries, error flags, and lane ordering “as-is,” or can reorder/map/retime. Pass: the expected behaviors are documented as acceptance tests (X).
  • Interconnect strategy is treated as a first-class block: define the longest segment, connector/FPC count, via transitions, and reference-plane continuity. Pass: every segment has an SI margin owner (X).
  • ESD protection is selected for MIPI bandwidth, not only IEC rating: use ultra-low capacitance parts with tight channel matching for high-speed pairs. Example single-line devices: Nexperia PESD5V0F1BSH (0.2 pF class), Littelfuse SESD0402X1UN-0020-090 (ultra-low C discrete TVS). Pass: ESD parts do not dominate the eye/edge-rate risk (X).
  • Power-noise-to-jitter path is explicitly bounded: define which rails feed the extender/bridge PHY and how they are isolated (beads/LDOs), and where the measurement points are. Example bead anchor: Murata BLM18AG601SN1D (0603 ferrite bead class). Pass: rails have a measurable noise budget and probe plan (X).
  • Decoupling is not “generic” for PHY blocks: place a small-value, low-ESL capacitor close to each PHY rail pin and a local bulk cap per island. Example MLCC anchors: Murata GRM155R71C104KA88D (0.1 µF, 0402 class), Murata GRM21BR60J226ME39L (22 µF, 0805 class). Pass: layout review confirms shortest return paths (X).
  • Lane mapping/polarity rules are finalized before layout: decide what can be solved by PCB swap/polarity and what must be supported by the device/firmware. Pass: mapping matrix is frozen and traceable to register settings (X).
  • LP↔HS entry/exit requirements are treated as an interface contract: confirm the extender/bridge supports ULPS/LP states used by the system and does not change thresholds or pull strengths unexpectedly. Pass: LP idle and HS request timing are testable (X).
  • Diagnostics and observability are design requirements: require access to counters (CRC/ECC/SoT/deskew errors), and a “known-good configuration snapshot.” Pass: the configuration can be exported/imported and hashed (X).
  • Vendor questions are prepared before committing: confirm max per-lane rate class (X), supported lane counts, retimer lock behavior after sleep/wake, and error propagation behavior. Pass: vendor answers are tied to acceptance tests (X).
Bring-up checklist (establish baselines and isolate layers) Definition of done: the system has a “zero-error” baseline at a known configuration, and failures can be reproduced on demand.
  • Start with shortest path + lowest rate: short cable/FPC, minimal connectors, and reduced lane rate. Pass: CRC/ECC counters remain at 0 for X minutes.
  • Record a “known-good configuration snapshot”: store register dumps (device + host) and a config hash. Pass: the system can restore the same state and reproduce the baseline (X).
  • Verify lane order + polarity deterministically: prove mapping by controlled pattern/traffic (or vendor BIST/PRBS if available). Pass: mapping checks pass across power cycles (X).
  • Validate LP↔HS entry/exit under real sequences: test boot, sleep/wake, and hot-plug (if applicable). Pass: no HS-entry failures across N cycles (X).
  • A/B tests must be built into the plan: direct-connect vs with extender; short vs long; reduced rate vs full rate. Pass: each A/B change shifts only one “budget axis” (X).
  • Correlate errors with physical probes: observe rail noise at near-end and far-end (same event window), and compare eye/transition quality at the critical segment boundaries. Pass: a single dominant correlation is identified (X).
  • Make “random failures” reproducible by controlled stress: temperature steps, intentional supply ripple injection, or gentle FPC bend (within spec). Pass: failure rate becomes stable enough for before/after comparisons (X).
  • Treat ESD parts as a bring-up variable: compare with/without ESD population (if pads allow) or swap between ultra-low-C options (e.g., PESD5V0F1BSH vs SESD0402X1UN-0020-090). Pass: ESD choice impact is quantified (X).
  • Retimer/Redriver tuning changes must be logged: equalization/edge-rate settings (e.g., Diodes PI2MEQX2505 EQ presets; TI SN75DPHY440SS behavior) must be versioned. Pass: each tuning change maps to a measurable margin shift (X).
  • Define a “field-like” pass gate: stable video/capture for X minutes with counters ≤X and no re-training loops. Pass: the gate is repeatable across resets (X).
Production checklist (control variation and enforce guard bands) Definition of done: production fixtures and interconnect batches do not shift the link outside guard bands, and every failure is traceable.
  • Fixture and cable/FPC batch control is mandatory: record batch IDs, connector insertion cycles, and fixture contact maintenance intervals. Pass: AQL gates are defined with counters ≤X.
  • Guard bands are derived from bring-up baselines: set production thresholds for counters, recovery attempts, and warm-up time. Pass: guard bands maintain yield across temperature and supply corners (X).
  • Configuration control is enforced on the line: program and verify extender settings (EQ/retime/LP behavior) and store a config hash in logs. Pass: wrong config is detectable in seconds (X).
  • ESD population and placement are audited: verify the correct ultra-low-C parts are placed (e.g., PESD5V0F1BSH or SESD0402X1UN-0020-090) and orientation is correct. Pass: no “silent BOM drift” occurs (X).
  • Thermal behavior is validated as a production variable: confirm stability after a defined warm-up and during temperature transitions. Pass: the link meets counters ≤X after X seconds from wake.
  • A/B failure triage is standardized: swap one dimension only (fixture → golden fixture, FPC batch, extender board) and re-run the pass gate. Pass: root cause category is assigned within X minutes.
  • Field diagnostics hooks are left enabled: counters remain readable and error snapshots can be exported without disassembly. Pass: field returns can be classified without “guesswork” (X).
  • Approved alternates list is explicit: define qualified alternates for key “margin killers” (ESD, beads, decouplers, extender). Example alternates must be pre-qualified by the same gate. Pass: alternates do not change the guard band requirement (X).
Diagram: engineering loop (assumptions → measurements → guard bands → diagnostics)
Engineering closed-loop for MIPI CSI-2/DSI extension Four stages: Design, Bring-up, Production, Field. Arrows form a loop with minimal labels. Design Architecture Interconnect Power + ESD Bring-up Baseline counters A/B isolation Reproduce stress Production Fixture control Guard bands Config hashes Field Diagnostics readout Error snapshots Assumptions Measurements Guard bands Diagnostics

H2-12 · Applications & IC Selection Notes (before FAQ)

Selection is organized by real deployment scenarios. The goal is to ask the supplier the right questions and avoid the common traps that appear only after cables, connectors, power noise, and sleep/wake sequences are introduced.

Mobile / Tablet (hinge FPC + strong EMI)

Typical topology: SoC ↔ long FPC ↔ camera/panel (multiple connectors, frequent LP↔HS).
Dominant risk: LP↔HS entry failures, connector-induced loss/return-path breaks, ESD parasitics.
Prioritize: clean LP behavior + controlled edge-rate/EQ; ultra-low-C ESD at the interface.
Pass criteria (placeholder): counters ≤X over X minutes; wake-to-stable ≤X seconds.
Must-ask vendor questions (3–5)
  • Does the device fully support ULPS/LP states and bi-directional LP mode required by DSI/CSI-2? (X)
  • What EQ/edge-rate presets exist for FPC + connector loss? Example ReDriver anchors: PI2MEQX2505 / PI2MEQX2503A.
  • How does the solution behave after sleep/wake across temperature? If retiming is needed: SN75DPHY440SS class retimer behavior must be characterized.
  • Is channel-to-channel matching and ESD recommendation documented? Example ESD anchors: PESD5V0F1BSH, SESD0402X1UN-0020-090.
  • What are the required probe points and counters to qualify “no intermittent link” in mass production (X)?

Industrial camera short-reach extension (board-to-board, noisy environment)

Typical topology: sensor board ↔ connector ↔ compute board (moderate length, strong ESD/EMI exposure).
Dominant risk: burst errors under EMI, power-noise-to-jitter coupling, ESD clamp distortion.
Prioritize: observability (counters), repeatable A/B tests, and stable behavior across supply variation.
Pass criteria (placeholder): error bursts ≤X per hour at full rate; stable across supply ripple X.
Must-ask vendor questions (3–5)
  • Which counters exist (CRC/ECC/SoT/deskew), and can they be latched for post-mortem? (X)
  • If using a retimer, what is the lock behavior under power ripple and temperature? Example anchor: SN65DPHY440SS / SN75DPHY440SS.
  • What ESD/TVS guidance is validated for high-speed MIPI? Example anchors: PESD5V0F1BSH, SESD0402X1UN-0020-090.
  • Is the recommended power filtering documented? Example anchor bead: Murata BLM18AG601SN1D.
  • What is the qualification flow to prove “EMI does not create intermittent link drops” (X)?

Dual / multi-camera aggregation (lane + VC/DT handling)

Typical topology: multiple sensors → aggregator/bridge → single CSI-2 output to SoC.
Dominant risk: VC/DT mismatches, packet boundary artifacts, lane mapping/deskew issues after aggregation.
Prioritize: protocol-aware behavior + deterministic mapping + transparent error reporting.
Pass criteria (placeholder): no frame boundary corruption; packet errors ≤X under stress (X).
Must-ask vendor questions (3–5)
  • How are VC/DT and packet boundaries preserved (or modified), and what buffering is used? (X)
  • Is lane mapping/polarity configurable, and is deskew deterministic across resets? (X)
  • Is there a reference design/platform for CSI-2 bridging/aggregation? Example platform anchors: Lattice LIF-MD6000-6KMG80I, CrossLink-NX LIFCL-40-9BG400C (platform/device family examples).
  • Can error flags and counters be surfaced to the host for production/field triage? (X)
  • What is the maximum sustainable throughput with worst-case VC mix and line blanking patterns (X)?

Display (DSI): video mode vs command mode (latency + wake behavior)

Typical topology: SoC DSI → connector/FPC → panel; frequent low-power states.
Dominant risk: LP↔HS timing mismatch, wake-to-stable variability, and “looks OK on bench” issues after integration.
Prioritize: deterministic wake behavior + LP state correctness; avoid ESD parts that distort HS edges.
Pass criteria (placeholder): no flicker/frame drops for X minutes; wake-to-image ≤X sec; counters ≤X.
Must-ask vendor questions (3–5)
  • Does the solution support bi-directional LP mode and the exact ULPS/wake sequences used by the panel? (X)
  • If a retimer is used, what is the lock time distribution after wake and across temperature? Example anchor: SN75DPHY440SS class retimer.
  • What EQ/edge-rate tuning is recommended for long FPC and multiple connectors? Example ReDriver anchors: PI2MEQX2505 / PI2MEQX2503A.
  • What ESD recommendation is validated at the panel-side interface? Example anchors: PESD5V0F1BSH, SESD0402X1UN-0020-090.
  • Which counters/indicators can gate production acceptance for flicker-free behavior? (X)
Selection dimensions (what must be “answerable” in a design review)
PHY support
D-PHY/C-PHY support, lane count, max per-lane rate class (X), LP state support.
Architecture
ReDriver (e.g., PI2MEQX2505) vs Retimer (e.g., SN75DPHY440SS) vs Bridge/Aggregator (e.g., LIF-MD6000-6KMG80I).
Clocking / recovery
CDR/retime behavior, lock time, sleep/wake stability, jitter tolerance (X).
Diagnostics
Counter availability, register access, snapshot/export, BIST/PRBS (if supported).
Power / thermal
mW per Gbps (X), package θJA/derating, rail filtering anchors (e.g., BLM18AG601SN1D, GRM155R71C104KA88D).
Diagram: minimal selection decision tree (Bridge vs Retimer vs ReDriver)
Selection decision tree for MIPI CSI-2/DSI extension Three decisions lead to three device types: Bridge, Retimer, ReDriver. Minimal labels. System need? Protocol / lane change? Need strong clock recovery? Mostly loss extension? Bridge packet • lane map Retimer CDR • lock • jitter ReDriver EQ • transparency YES YES YES
Concrete material numbers (BOM anchors for this page)
  • MIPI D-PHY retimer: TI SN65DPHY440SS / SN75DPHY440SS (CSI-2/DSI DPHY retimer class).
  • MIPI D-PHY ReDriver: Diodes PI2MEQX2505 (4-lane + clock), PI2MEQX2503A (2-lane + clock).
  • Ultra-low capacitance ESD/TVS: Nexperia PESD5V0F1BSH; Littelfuse SESD0402X1UN-0020-090 (verify directionality and placement rules).
  • Power filtering bead: Murata BLM18AG601SN1D (ferrite bead class for rail isolation).
  • Decoupling anchors: Murata GRM155R71C104KA88D (0.1 µF, 0402 class), Murata GRM21BR60J226ME39L (22 µF, 0805 class).
  • MIPI bridging/aggregation platform examples: Lattice LIF-MD6000-6KMG80I, CrossLink-NX example board device LIFCL-40-9BG400C (use-case dependent; verify PHY/throughput requirements).

Note: part-number suffix, package, temperature grade, and availability must be verified per project. Use these as starting anchors, not as a final AVL.

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H2-13 · FAQs (fixed 4-line answers + JSON-LD)

These FAQs close long-tail debug questions without expanding the main text. Each answer is constrained to four executable lines: Likely cause / Quick check / Fix / Pass criteria. Thresholds are placeholders (X) to be filled by the project’s acceptance gates.

Direct connect is stable, but adding a repeater causes intermittent frame drops — over-EQ noise boost or return-path/crosstalk? Symptom class: ReDriver/EQ side effects vs interconnect return path
Likely cause
Over-aggressive EQ/edge boost increases broadband noise and crosstalk coupling; return-path discontinuity converts common-mode noise into differential errors; rail noise modulates the slicer thresholds.
Quick check
Reduce EQ by 1 step (or disable) and compare CRC/ECC and frame-drop counters; repeat with a shorter interconnect (short FPC/cable). Probe repeater VDD ripple at the moment of the error (rail ripple = X mVpp).
Fix
First: de-rate EQ/edge boost and remove stubs. Next: repair return path (continuous reference, grounded connector pins, minimize via transitions). If loss/jitter margin remains insufficient, upgrade to a retimer (e.g., SN75DPHY440SS class) instead of a pure repeater.
Pass criteria
Frame drops = 0 for ≥X minutes at full rate; CRC/ECC ≤X per 106 packets; HS entry retries ≤X per hour; rail ripple at repeater VDD ≤X mVpp during steady state.
Reduced lane rate is stable, but full rate makes CRC spike — check loss first or jitter first? Symptom class: “rate-dependent failures” (budget axis classification)
Likely cause
Insertion loss / impedance discontinuity exceeds equalization margin; or sampling window collapses due to random/deterministic jitter (power-induced, crosstalk-induced, or retimer lock margin).
Quick check
Sweep rate with unchanged topology and record CRC per 106 packets vs rate. Toggle EQ (on/off or ±1 step). If EQ reduces errors significantly, loss dominates; if EQ has little effect, jitter/power/clock recovery dominates.
Fix
Loss-first path: improve connector/FPC launch, reduce stubs, shorten the worst segment, tune ReDriver (e.g., PI2MEQX2505 class). Jitter-first path: isolate/quiet PHY rails, reduce crosstalk coupling, or adopt a retimer (CDR-based) with verified lock behavior.
Pass criteria
At full rate: CRC/ECC ≤X per 106 packets; no link retrain/HS re-entry loops for ≥X minutes; error rate slope vs temperature ≤X (%/°C) at steady state.
LP is always fine, but HS entry fails — termination/threshold issue or timing issue? Symptom class: LP↔HS mode switching
Likely cause
HS termination/common-mode expectations are violated (device changes termination behavior), LP thresholds are shifted by leakage/ESD, or HS request/settle timing is outside the bridge/retimer requirements.
Quick check
Capture one successful and one failed HS entry: verify LP idle level (LP = X V), HS request timing (Tprep, Tzero = X ns), and whether termination turns on as expected. Temporarily replace ESD/TVS with ultra-low-C (e.g., PESD5V0F1BSH class) to isolate parasitic effects.
Fix
Align HS-entry timing to the device’s requirements; correct termination enable sequencing; reduce LP leakage (ESD placement, IOFF behavior); remove stubs and ensure return path continuity through the connector/FPC.
Pass criteria
HS entry success ≥(1 − X%) over N = X cycles; HS entry time ≤X ms; SoT/EoT-related errors ≤X per 106 packets during steady streaming.
It only starts flickering after warm-up — power-noise coupling or CDR/lock margin? Symptom class: thermal-dependent margin crossing
Likely cause
Rail noise increases with temperature (regulator efficiency/ESR changes), retimer lock margin shrinks, or interconnect impedance/contact quality shifts under mechanical/thermal stress.
Quick check
Log temperature (T = X °C), retimer/bridge status registers (lock/state = X), and CRC/error counters in the same timestamp window. Measure PHY rail ripple hot vs cold (Δripple = X mVpp). If errors track rail ripple, PI dominates; if errors track lock/state, CDR dominates.
Fix
Improve local decoupling/rail isolation (short return paths, bead + MLCC), reduce crosstalk sources, and ensure the retimer’s lock/wake parameters are configured for thermal corners. If the weakest segment is mechanical, add strain relief and tighten connector/FPC specs.
Pass criteria
Stable at hot condition for ≥X minutes: flicker events = 0; CRC/ECC ≤X per 106 packets; rail ripple ≤X mVpp; wake-to-stable ≤X seconds across T range.
One C-PHY trio is much more sensitive — trio imbalance or connector crosstalk? Symptom class: C-PHY trio asymmetry
Likely cause
Trio routing is imbalanced (length/return path/launch), one trio sees higher aggressor coupling through the connector/FPC, or protection parasitics are mismatched among the three wires.
Quick check
If mapping is configurable, remap the trio to a different physical channel and see if the sensitivity follows the physical path. Compare per-trio error indicators (trio_err[0..N] = X). Swap connector/FPC sample and repeat.
Fix
Rebalance trio geometry (symmetry, reference continuity), adjust connector pinout/ground distribution, and enforce matched protection parasitics (same part/placement per wire). Reduce aggressor coupling near the trio.
Pass criteria
Per-trio error ratio ≤X (max/min) under the same workload; total errors ≤X per 106 packets; stable for ≥X minutes at full rate and worst-case flex/EMI condition.
After a bridge, VC/DT does not match expectations — lane mapping error or packet-handling configuration? Symptom class: protocol-aware bridge behavior
Likely cause
Lane order/polarity is incorrect, or the bridge is rewriting/filtering VC/DT (routing rules, aggregation policy, or “transparent” mode is not truly transparent).
Quick check
Read and snapshot the bridge’s VC/DT routing registers (route_table_hash = X) and compare with the input stream’s expected VC/DT list. Check whether packet error flags are forwarded or masked (err_fwd = X).
Fix
Lock lane mapping/polarity first; then configure VC/DT passthrough/rewriting rules explicitly; ensure aggregation buffers do not violate frame/line boundary assumptions; keep error reporting enabled for bring-up and production.
Pass criteria
Expected VC/DT presence = 100% of configured routes; packet error flags are observable; frame boundary corruption events = 0; CRC/ECC ≤X per 106 packets over ≥X minutes.
It fails only with one FPC batch — how to quickly separate insertion-loss variation from impedance discontinuity? Symptom class: batch variation (production relevance)
Likely cause
Batch-to-batch loss increases (dielectric/trace variation), connector plating/contact changes, or impedance discontinuity at the launch amplifies reflections and deskew stress.
Quick check
A/B swap the failing vs passing FPC on the same unit and run at full rate and half rate. If halving rate fixes it, loss/ISI dominates; if not, check for sharp discontinuities via a simple TDR sample (Z step = X Ω, reflection peak = X%).
Fix
Add incoming inspection limits (loss proxy or TDR bounds), tighten launch/connector constraints, and reserve SI margin with ReDriver/retimer settings. If batch variation is unavoidable, convert the acceptance gate into a guard band (AQL thresholds).
Pass criteria
Across qualified batches: yield ≥X%; CRC/ECC ≤X per 106 packets at full rate; TDR/impedance variation within ±X Ω; no intermittent drops during ≥X minutes stress test.
Visible jitter/flicker occurs but error counters stay low — upstream timing jitter or bridge buffering/latency behavior? Symptom class: “quality issues without CRC”
Likely cause
Frame-level timing instability (upstream clocking/blanking jitter) can create visible artifacts without CRC; or the bridge’s buffering/latency crosses a boundary condition (under/overflow not always exposed as CRC).
Quick check
Correlate flicker timestamps with VSYNC/TE timing (Δt = X µs) and bridge buffer flags (buf_uf/of = X). Increase blanking or reduce bandwidth temporarily: if flicker improves with bandwidth relief, buffering is likely; if not, upstream timing is likely.
Fix
Upstream path: stabilize the source timing (clock/blanking), reduce injected supply noise. Bridge path: increase buffer headroom, adjust scheduling/VC policy, and prevent near-100% utilization operation.
Pass criteria
Flicker events = 0 over ≥X minutes; VSYNC/TE timing variation ≤X µs; buffer under/overflow flags = 0; CRC/ECC remains ≤X per 106 packets.
It fails after wake or hot-plug — reset sequencing issue or HS-entry training/lock behavior? Symptom class: state transitions (sleep/wake/hot-plug)
Likely cause
Reset/enable ordering leaves the PHY in an unexpected LP/ULPS state; HS entry timing is violated; retimer/bridge needs additional lock time after wake (distribution tail issue).
Quick check
Timestamp the wake/hot-plug sequence and log device state registers immediately after each step (state[step] = X). Insert a controlled delay (Δt = X ms) between reset release and HS entry; if pass rate increases, lock/settle time is the lever.
Fix
Enforce a deterministic reset/enable order; verify LP/ULPS state before HS entry; add bounded retries; configure retimer lock parameters for wake. Avoid relying on “typical” lock time—qualify worst-case.
Pass criteria
Wake/hot-plug success ≥(1 − X%) over N = X cycles; wake-to-stable video ≤X seconds; HS entry retries ≤X per 100 cycles; no persistent stuck states observed in logs.
Adding TVS changes “intermittent” to “always fail” — how to confirm it is capacitance/mismatch destroying the eye? Symptom class: protection parasitics
Likely cause
TVS/ESD capacitance is too high, channel mismatch creates differential imbalance, or placement introduces a stub that increases reflections at HS edges.
Quick check
Bypass or depopulate the TVS (if pads allow) and re-run the same test; then substitute an ultra-low-C device (e.g., PESD5V0F1BSH class or SESD0402X1UN-0020-090 class). Compare CRC/ECC and HS-entry success rate.
Fix
Select ultra-low-C matched parts; place protection close to the connector with minimal stub; keep differential symmetry; avoid mixing different ESD parts across lanes; validate protection + SI together.
Pass criteria
With protection populated: full-rate CRC/ECC ≤X per 106 packets; HS entry success ≥(1 − X%); no new reflection-induced failures over ≥X minutes stress run.
After multi-camera aggregation, one stream always drops — deskew margin or bandwidth/VC allocation? Symptom class: aggregation scheduling vs lane alignment
Likely cause
Deskew window is exceeded under load, per-stream buffering crosses an overflow/underflow boundary, or VC scheduling starves one stream during peak throughput.
Quick check
Reduce only that stream’s bandwidth (fps/resolution) by X%: if drops disappear, bandwidth/buffering dominates. Check deskew error counters (deskew_err = X) and buffer flags (buf_uf/of = X). Swap VC assignment and repeat.
Fix
Fix lane alignment/mapping first; then rebalance bandwidth and VC scheduling; increase buffering headroom; avoid running at utilization >X% without guard band; validate worst-case line blanking + VC mix.
Pass criteria
All streams at full load stable for ≥X minutes; per-stream drops = 0; deskew_err = 0; buffer under/overflow flags = 0; CRC/ECC ≤X per 106 packets.
It fails only at one temperature point — what registers/counters must be logged for a meaningful comparison? Symptom class: “single-point” thermal failure (data-driven correlation)
Likely cause
A single margin axis crosses a threshold (rail noise, HS/LP thresholds, lock margin, or interconnect drift). Without consistent logs, the failure looks random and unrepeatable.
Quick check
For both PASS and FAIL at the same workload, log: (1) config hash (cfg_hash = X), (2) status/lock/state registers (state = X), (3) error counters (CRC/ECC/SoT/deskew = X), and (4) rail ripple at PHY VDD (ripple = X mVpp) with temperature (T = X °C).
Fix
Use the log delta to identify the single dominant lever (noise vs lock vs threshold). Tighten the guard band on that lever: improve rail isolation/decoupling, adjust lock/wake sequencing, or increase SI margin at the weakest segment.
Pass criteria
Stable across Tmin..Tmax with the same config hash; CRC/ECC ≤X per 106 packets; no HS-entry loops; rail ripple ≤X mVpp at all corners; logs are complete for 100% of tested units.
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