SDI (3G/6G/12G) SerDes for Broadcast Coax Links
← Back to:Interfaces, PHY & SerDes
Delivering an SDI SerDes link means turning coax loss, reflections, and jitter into a measurable link budget—and using EQ and reclocking to recover eye and jitter margin to a production-stable state.
This page provides an engineering workflow from channel modeling and Tx/Rx equalization to CDR jitter budgeting and compliance/production evidence, with reusable threshold placeholders for consistent bring-up and manufacturing.
Scope & Quick Navigation: what this page solves (and what it does not)
This page focuses on the SDI physical link over 75 Ω coax—equalization, retiming, jitter/eye compliance, ANC/timing handling on the serial path, and broadcast-grade bring-up and production readiness.
The 6 most common SDI link blockers (symptom → module)
- Long coax / poor cable reach → channel loss & reflections, Rx EQ strategy
- CDR locks but errors still appear → jitter tolerance, PLL loop bandwidth, power-noise injection
- Eye mask / compliance fails → Tx return-loss, Rx EQ mis-training, measurement traps
- ANC/timing insertion makes the link worse → CDC/FIFO placement, pattern stress, reclock boundary
- Hot-plug / ESD / field dropouts → port protection, chassis return path, ground potential events
- Inconsistent production results → fixture/cable binning, mandatory logs, deterministic reset behavior
What this page delivers (copy-ready engineering assets)
- Link budget template: cable type/length, connector count, board trace, loss estimate → recommended EQ/retime decision
- EQ strategy template: fixed vs adaptive, convergence flow, when to lock presets for production
- Jitter budget & JTOL checklist: where jitter is created/filtered, what to probe, and how to report margin
- Compliance + production gates: bring-up → qualification → manufacturing (required tests + required logs)
Not in scope (to avoid cross-page overlap)
- No register-level walkthroughs or clause-by-clause SMPTE standard commentary (only engineering-critical fields used for measurement and bring-up).
- No HDMI/DisplayPort/MIPI/LVDS deep dives (handled by dedicated sibling pages).
- No video processing / codec / color pipeline explanations (only effects that change SDI physical behavior: rate, patterns, jitter/eye risk).
Page map (sections follow)
Dashed items are planned sections that will be added below; the anchor buttons will become active once those H2 blocks exist.
SDI PHY skeleton: how the link “runs” (rate, scrambling, patterns, and why retiming matters)
SDI over coax is a high-speed serial channel where frequency-dependent loss and reflections rapidly close the eye as line rate increases. Equalization and retiming are not optional “features”—they are the primary tools that restore margin and make compliance repeatable.
Multi-rate in engineering terms (3G / 6G / 12G)
Typical SDI line rates scale roughly as: ~2.97 Gb/s (3G), ~5.94 Gb/s (6G), ~11.88 Gb/s (12G). Higher rate compresses unit interval, increases sensitivity to discontinuities, and reduces tolerable jitter/ISI.
- Rate ↑ → loss looks worse: same coax behaves like a stronger low-pass filter; ISI rises quickly.
- Rate ↑ → reflection cost ↑: connectors, stubs, and impedance steps consume more eye width/height.
- Rate ↑ → “reclock boundary” matters: placing ANC/timing insertion pre/post retime changes how jitter and patterns propagate.
Scrambling and “pathological” patterns (why worst-case tests matter)
Scrambling improves transition density and makes the channel friendlier to clock recovery, but worst-case pattern stress still exists. Certain sequences reduce useful transitions or increase low-frequency content, which can raise CDR stress and worsen baseline recovery behavior on AC-coupled paths.
The essential PHY modules (and what to observe in the lab)
- Tx driver: output swing/edge control and return-loss friendliness (avoid “protection-as-a-reflector”).
- Rx EQ (CTLE/DFE): restores high-frequency content but can amplify noise or mis-train on reflections.
- CDR / retimer: defines jitter transfer and lock behavior; “lock” does not guarantee margin.
- Descrambler + ANC/timing boundary: insertion/extraction placement affects CDC risk, latency stability, and pattern stress.
Minimum observability recommended: lock state, EQ preset/state, error counters (pre/post retime if available), and a deterministic reset sequence with logged capture timestamps.
Why retiming is a first-class design decision (not a checkbox)
Equalization re-opens the eye in amplitude; retiming restores timing margin by filtering accumulated jitter and reshaping edge placement according to the CDR/PLL transfer. The choice impacts compliance, long-cable robustness, and reset-to-reset determinism.
- When retiming helps most: high loss, heavy connector count, noisy power/ground environments, tight mask margin.
- Primary risk: added latency and PLL loop settings that must be verified with JTOL and stress patterns.
Coax channel model (coax + connectors + reflections): the root cause of closed eyes
SDI over 75 Ω coax behaves like a frequency-shaped channel with discontinuity-driven echoes. Treating the link as a measurable “channel card” (loss + reflections + return path) is the fastest way to decide whether the dominant limiter is loss/ISI or reflections/echo, and to prevent EQ mis-training.
Channel Card (recommended minimum record)
A channel card turns “it works on some cables” into a repeatable engineering artifact. Record the fields below before tuning EQ or declaring a retimer requirement.
- Cable type (model/series) + length
- Connector count (BNC, adapters, patch points)
- Board path length (connector → IC pin, incl. vias)
- Any stubs (test pads, tees, long branch)
- Shield/chassis return path (how the coax shield bonds)
- Loss-dominant: eye closes smoothly with length; EQ improves margin predictably.
- Reflection-dominant: “double edges” / ripples; EQ can mis-train and worsen errors.
75 Ω coax engineering model: frequency-shaped loss (ISI driver)
- Loss rises with frequency: higher rates compress the unit interval, so the same cable consumes more eye width/height.
- ISI is the visible symptom: the channel acts like a low-pass filter that smears edges into neighboring bits.
- Engineering takeaway: loss-dominant links typically benefit from CTLE/FFE; extreme loss often pushes toward retiming.
Reflections / echoes: discontinuities that create pattern-dependent failures
- Discontinuities (connectors, adapters, stubs, layout steps, protection parts) create echoes that re-enter the receiver.
- Echoes can show up as eye ripples, double edges, or CDR stress, and may worsen with “better” EQ if the equalizer converges to the wrong solution.
- Practical approach: locate and reduce strong reflection points first, then optimize EQ on a cleaner channel.
Common “hidden killers” (fast check direction)
Measurement discipline (to avoid false conclusions)
- Keep instrument bandwidth, equalizer mode, and fixture unchanged during A/B.
- Change one variable at a time (cable length, connector path, stub removal, board segment).
- Log the channel card fields with each test run to make results reproducible.
Tx driver design that behaves like SDI (return loss, overshoot, EMI, and jitter injection control)
A “good-looking” waveform at the output pin is not enough. For SDI over coax, the Tx path must behave like a controlled 75 Ω launch: predictable swing and edge behavior, low reflection sensitivity, and minimal supply-to-edge jitter injection.
Tx path objectives (what must be “true” in hardware)
- Controlled launch: maintain 75 Ω behavior from driver to BNC.
- Stable swing & edge: avoid excessive overshoot/ringing and avoid overly slow edges.
- Return-loss friendly: minimize near-end echoes that EQ cannot reliably fix.
- Low jitter injection: power noise should not translate into edge timing noise.
Key output metrics → typical failure modes
Pre-emphasis / feed-forward (if available): when it helps vs when it hurts
- Useful when the channel is predominantly loss/ISI-driven and cable profiles are known or binned.
- Risky when reflections dominate (connectors/adapters/stubs): sharper edges can increase ringing and worsen EMI.
- Decision rule: reduce strong reflection points first; use pre-emphasis to recover high-frequency loss after the launch is clean.
Most common Tx-side mistakes (fast mitigation direction)
Minimal Tx validation set (3 checkpoints)
- Near-end eye: establish a launch baseline before long-cable tuning.
- Return loss / reflection check: verify the port does not behave like a reflector.
- Emission hotspot scan: locate radiation peaks near the connector and the launch region.
Pass criteria are system- and standard-dependent; keep thresholds as project placeholders until the compliance chapter defines them.
Receiver equalization (CTLE / DFE / Adaptive EQ): opening the eye for SDI cable reach
SDI reach is rarely limited by “link lock” alone. Equalization must be treated as a controlled engineering loop: decide whether the channel is loss-dominant or reflection-dominant, choose the right mix of CTLE/DFE, run a deterministic lock sequence, and verify with measurable pass criteria rather than “it looks open.”
EQ playbook (copy-ready workflow)
- Start from the channel card (cable type/length, connector path, stubs, board segment).
- Decide the dominant limiter: loss/ISI → CTLE first; reflections/echo → fix discontinuities before relying on adaptive EQ.
- Run a deterministic lock sequence: coarse sweep → fine tune → lock preset.
- Verify with pass criteria (eye + BER + lock time) and log EQ state for repeatability and production binning.
CTLE: best for smooth loss, but can amplify noise when over-applied
- Strength: compensates frequency-shaped attenuation and restores high-frequency content for loss-dominant channels.
- Typical win condition: eye degradation is “smooth” (edges rounded, eye height/width shrink gradually with length).
- Typical failure mode: CTLE gain ↑ also raises high-frequency noise/crosstalk → eye looks thicker and BER can worsen.
DFE: powerful against ISI, but adds convergence time and pattern dependence risk
- Strength: cancels post-cursor ISI by learning channel memory, improving eyes that have strong “tails.”
- Costs: convergence/settle time increases; mis-convergence becomes possible when reflections are strong.
- Pattern dependence: some content and stress patterns can expose weaknesses that “easy video” hides.
Adaptive strategy: deterministic lock flow (coarse → fine → lock → optional track)
Quantifiable pass criteria (threshold placeholders)
- Eye height ≥ X (mV or %)
- Eye width ≥ X (UI)
- BER ≤ X (e.g., 1e-12)
- Lock/settle time ≤ X ms
- Worst-case cable length ≥ X m (per cable bin)
Common symptoms → first check item
Retiming & jitter: CDR/PLL “lock” is not the same as stability
In SDI systems, “CDR locked” can still hide marginal behavior: periodic errors, occasional unlock, or visible artifacts. Treat jitter as a budget and validate margin with a JTOL-style test recipe. Retiming and PLL bandwidth settings determine which jitter components are followed, filtered, or amplified.
This chapter delivers (jitter budget + JTOL test recipe)
- A jitter budget map (source + channel-induced + PLL transfer).
- A repeatable JTOL-style validation flow to produce margin numbers.
- A symptom-to-first-check list (power, reference, EQ state, reflections).
Jitter types (verification-relevant distinctions)
CDR/PLL loop bandwidth: lock time vs filtering (hard trade-off)
- Wide BW: faster lock and better tracking, but less filtering of incoming jitter.
- Narrow BW: stronger filtering and potentially cleaner output, but longer lock/settle time.
- Engineering rule: choose BW based on the stress environment (cable loss, spur risk, plug events) and prove it with JTOL margin.
JTOL-style margin recipe (template steps)
- Select stress patterns and define the BER observation window (fixed duration).
- Record baseline: lock state, EQ state, BER at zero injection.
- Sweep injected jitter amplitude across a frequency set (placeholders are acceptable).
- Failure conditions: BER > X, unlock, or repeated re-lock cycles.
- Output margin: maximum tolerable injection per frequency + the configuration state (EQ + PLL mode/BW).
“Locked but unstable” symptoms → first check item
Timing & ANC embed/extract (physical-layer relevant paths only)
Timing/ANC/audio/timecode features matter at the physical layer primarily through placement and timing behavior: where insertion/extraction occurs relative to reclocking, how it perturbs data statistics seen by CDR/PLL, and whether CDC/FIFO choices introduce latency variance or narrowband spurs. Protocol encyclopedics are intentionally out of scope.
This chapter delivers (embed/extract placement + verification fields)
- Placement options: pre-reclock vs post-reclock (what risk moves where).
- CDC/FIFO risk map: where latency variance and re-lock drift originate.
- Verification checklist: mask margin, spur correlation, CRC/error counters, latency variance.
Placement: pre-reclock vs post-reclock (what “moves” between CDR risk and CDC risk)
Physical-layer impacts: CDR pressure, spur risk, and burst behavior
- Pattern statistics: embed/extract can change transition density and spectral content, shifting where margin is consumed.
- Bursty updates: sudden changes can create short transients that look like additional phase noise to the loop.
- Spur mechanisms: a periodic activity or CDC boundary can correlate with narrowband spurs observed at recovered clocks.
CDC/FIFO: where latency variance is born (and how it becomes visible)
Verification fields (threshold placeholders + must-log)
- Mask/eye margin change after embed: Δmargin ≥ X (placeholder)
- Recovered clock spur amplitude ≤ X dBc (placeholder)
- CRC/error counter rate ≤ X (placeholder)
- Latency variance ≤ X (placeholder)
Return-channel (return video / control / diagnostics): selecting an architecture that remains stable
“Return-channel support” must translate into an engineering choice: what category of return traffic is required, which physical approach carries it, what risks are introduced to the main SDI link, and how stability is proven through verification (interference, EMI, recovery, unlock behavior, and margin impact).
Split the requirement into three categories (to avoid ambiguous “support” claims)
Three common architecture paths (choose by risk tolerance and verification budget)
- Dual-coax / dual-channel: physical separation; lowest interference risk to main link.
- Overlay modem on coax: low-speed overlay via FDM/TDM/modem; strongly implementation-dependent and must be validated.
- ANC-carried control/diag: rides the embedded path; limited capacity/real-time behavior and inherits CDC/FIFO risks.
Option A — Dual-coax / dual-channel (separation-first)
- Benefit: return traffic is isolated; main-link jitter/BER is least impacted.
- Cost: more connectors/cables and board routing complexity.
- Verify focus: cross-talk between channels, hot-plug recovery, simultaneous plug events.
Option B — Overlay modem on coax (FDM/TDM/modem): validate compatibility, never assume
- Risk: added energy on the line can change main-link margin (jitter, BER, unlock thresholds).
- EMI: overlay activity can introduce new peaks or worsen susceptibility.
- Verify focus: main-link mask/BER impact while toggling overlay on/off, recovery time after overlay bursts.
Option C — ANC-carried control/diagnostics (capacity and timing bounded)
- Benefit: no additional analog overlay; leverages the embedded sideband path.
- Limit: payload and real-time behavior are bounded; bursty updates may be visible as timing activity.
- Verify focus: insertion impact on mask/BER, CDC/FIFO latency variance and re-lock determinism.
Verification checklist (interference, EMI, recovery, unlock behavior, margin impact)
- Main-link BER/mask margin must not degrade beyond X when return traffic toggles (placeholder).
- Spur correlation: no new narrowband spurs exceeding X dBc (placeholder) during return activity.
- Recovery: after plug events and burst activity, re-lock time ≤ X ms (placeholder) and behavior is repeatable.
- EMI: return activity should not create new emission peaks that threaten compliance margins (log before/after).
Practical selection rules (short and strict)
Protection & immunity: ESD / surge / EMI + grounding & return paths (often underestimated in coax systems)
In field deployments, hot-plug events, long coax runs, and chassis ground potential differences are common. Protection must be treated as controlled energy steering: where transient current flows, how short the loop is, and whether the chosen clamp becomes a new reflection point that reduces eye and margin.
Field symptoms → first correlation checks (engineering-first)
- Hot-plug causes video glitches or unlock → correlate plug events to error counters and recovered clock stability; verify clamp-to-chassis current path.
- Long cables trigger intermittent errors → suspect chassis potential difference and shield current; inspect how shield meets chassis near the connector.
- Adding TVS worsens the eye → check whether the clamp placement or parasitics created a reflection point near the 75 Ω port.
Port risk map: what stresses a coax port and how it appears
Protection device selection (TVS) without turning it into a reflection source
- Low capacitance matters at multi-Gb/s: excessive C reduces eye height and shifts impedance near the connector.
- Dynamic behavior matters: the clamp must actually steer current during the event, not just look good on a DC datasheet plot.
- Placement dominates: locate at the connector with a direct, short path to chassis ground to prevent current from entering sensitive ground.
Clamp & return-path rules (keep the loop short; keep the port “75 Ω-like”)
EMI strategy: shield bonding and chassis connection (stop common-mode current from entering sensitive ground)
- EMI issues often originate from incorrect return paths, not from “fast edges” alone.
- The coax shield should be bonded so that disturbance energy is contained on chassis metal rather than driven across signal ground.
- The verification target is simple: changing shield-to-chassis strategy should not worsen link margin, and should improve emission/immunity behavior.
Quick verification: minimum evidence for protection & immunity
- Time-align plug/unplug actions to error counters, lock/unlock logs, and recovered clock observations.
- Compare mask/BER margin with protection variants (or bonding variants) while keeping EQ/PLL settings fixed.
- Confirm that the clamp return path remains local to chassis (no sensitive-ground traversal) by inspection and correlation with the failure signature.
Must-log fields (to keep failures reproducible)
- TVS part + footprint + placement distance to connector: X mm (placeholder)
- Shield-to-chassis bonding style and exact location(s)
- Port topology: via count, stub presence, connector adapters in use
- Event timestamps: hot-plug, surge exposure (if applicable), and the error window
Compliance & test: eye masks, jitter templates, stress cases, and an auditable evidence chain
Deliverable SDI is not “it worked once.” It is a reproducible flow: defined specs, controlled setup, bounded stimuli, measured margin, and a report that can be audited. This chapter provides a test template that scales from bring-up to production evidence.
Compliance dimensions (engineering meaning, not a standards catalog)
- Eye mask: margin visible at the receiver under defined conditions.
- Return loss: discontinuities that reduce reach and increase jitter sensitivity.
- Jitter: tolerance and transfer across the CDR/PLL path.
- Stress patterns: worst-case ISI and pattern statistics for EQ/CDR robustness.
- Cable reach: validated by bins (cable type, length, adapters) rather than a single claim.
Bring-up flow template (short → long, fixed EQ → adaptive, room → drift)
Stress cases (designed to expose boundaries)
- Pattern stress: worst-case ISI for EQ/DFE convergence.
- Reflection stress: adapters/connectors that increase return loss and echo.
- Power/EMI stress: supply noise and shielding changes that modulate jitter margin.
- Reset/re-lock stress: repeatability and lock time distribution, not a single “best run”.
Required test hooks (to make failures localizable)
- Loopback: isolate Tx/Rx/channel faults quickly.
- PRBS / BERT: remove content dependence; measure BER margin directly.
- Error counters: time-windowed stats with timestamps.
- EQ/PLL state readout: final CTLE/DFE mode, loop mode/BW, and lock state codes.
Pass criteria placeholders (make them measurable and repeatable)
- Mask margin ≥ X (placeholder)
- BER ≤ X (placeholder)
- Lock time ≤ X ms (placeholder)
- Post-reset repeatability: state consistent or variation ≤ X (placeholder)
- Reach coverage: validated bins to X (cable type/length/adapters) (placeholder)
Evidence chain: make the result auditable (not anecdotal)
Common pitfalls (short, actionable)
- A single “good screenshot” is not evidence: use time-windowed stats and repeatability runs.
- Eye-only or BER-only is insufficient: correlate mask, BER, lock behavior, and EQ states.
- Without timestamps, plug/drift events cannot be correlated to counters and lock stability.
Board-level SI/PI/Clock-domain rules for SDI (cut failure probability)
This section focuses strictly on the PCB path from the coax connector to the SerDes pins. The goal is to remove avoidable failure modes (reflection points, uncontrolled return paths, and supply-noise-to-jitter coupling) before equalization and retiming are tuned.
Fast triage: symptom → first board-level check
- Short coax works, long coax fails → look for discontinuities near the port (connector launch, via stubs, ESD footprint, test-point stubs). Confirm return-loss and TDR around the first centimeters.
- Random errors change with fans / DC-DC load → supply noise is coupling into CDR/PLL jitter. Validate decoupling loop geometry and measure ripple/noise in the “PLL-sensitive band” (set threshold = X mVrms placeholder).
- After reset the link “lands in different margins” → check clock-domain crossings, boot-time mode straps, and whether adaptive EQ/retiming state is deterministic (lock strategy and register image must be reproducible).
SI rules: 75 Ω launch, controlled impedance, and “no new reflection points”
- Keep the port-to-device path as a single, controlled 75 Ω route. Avoid sudden width changes, ground cutouts, and unexpected reference-plane swaps.
- Treat every footprint as a potential impedance step: connector launch, TVS pads, series components, and measurement pads must be designed to minimize parasitics.
- No stubs near the port: forbid long test pads and branch traces. If a test point is required, use the smallest geometry and place it away from the connector region. Stub length budget = X mm placeholder.
- Via usage budget: minimize count; if vias are unavoidable, control stub (back-drill / blind/buried strategy per stackup). Via count budget = X placeholder.
- Amphenol RF 12G-optimized 75 Ω BNC PCB jack (through-hole): 031-70536-12G (example). Verify mechanical form factor and board thickness.
- Amphenol RF 12G-optimized 75 Ω BNC PCB jack family (broadcast-focused): see related 12G-SDI PCB connectors list (example series).
PI rules: supply noise → jitter coupling (make it measurable)
In SDI SerDes, “lock” does not guarantee margin. Supply ripple can translate into phase noise and output jitter through CDR/PLL-sensitive nodes. The board must enforce short decoupling loops and isolation from switch-node return currents.
- Place high-frequency decoupling closest to the SerDes/PLL rails; prioritize shortest loop area over “nice placement”.
- Keep DC-DC switch node and its return loop away from the SDI port region and away from the refclk region. Do not let power return currents cross the SDI signal return corridor.
- Define a measurable limit: ripple/noise on the SerDes/PLL rail within the sensitive band ≤ X mVrms (placeholder), under worst-case thermal and load conditions.
- 0.1 µF X7R 0402 MLCC (example): Murata GRM155R71C104KA88D
- 10 µF X5R 0402 MLCC (example): Murata GRM155R60J106ME15D
- Ferrite bead for local isolation (example): Murata BLM18AG601SN1D (choose impedance vs frequency intentionally)
- Low-noise LDO options for jitter-sensitive rails (examples): TI TPS7A4700, Analog Devices ADM7150 (verify noise/PSRR vs band)
Clock + return-path rules: keep references deterministic and returns continuous
- Refclk routing: no plane splits underneath; keep away from switch nodes and high-dv/dt regions. If buffering is needed, place the buffer to preserve return continuity.
- Ground strategy: do not force SDI return current to traverse noisy digital ground regions. Preserve the shortest, most direct return path.
- Determinism rule: after reset, the same register image and the same lock procedure must lead to the same EQ/retiming state. “Auto” features must be bounded or logged.
Example SDI IC material numbers (for board-level integration references)
These are commonly used SDI equalizer/reclocker/driver devices. Final selection depends on system architecture, cable reach, power, and compliance plan. Always verify package, suffix, and vendor ordering codes.
- 12G cable equalizer + integrated reclocker (example): TI LMH1219
- 12G dual-output reclocker (example): TI LMH1226
- 12G dual-output cable driver + integrated reclocker (example): TI LMH1228
- 12G long-reach cable equalizer + integrated reclocker (example family): TI LMH1229 / LMH1239
- 12G reclocking cable equalizer/cable driver (example): Semtech GS12190
- 6G adaptive cable equalizer (example): Semtech GS6042
Port protection materials (keep capacitance low and returns controlled)
Protection parts can become new reflection points. Place them close to the connector and return to chassis ground with the shortest path. Confirm return loss / eye impact after adding protection.
- Ultra-low capacitance TVS array (example): Semtech RClamp0524P (capacitance class ~0.3 pF; verify layout and line assignment)
- Low/ultra-low capacitance TVS array (example): Littelfuse SP3003-02XTG (verify capacitance class vs signal integrity)
Engineering checklist for SDI deliverables (Design → Bring-up → Production)
This checklist is a gate-based workflow. Each gate defines what must be recorded, what must be demonstrated, and what counts as pass (thresholds left as placeholders to match the compliance plan and cable classes).
Gate A — Design freeze (before layout release)
- Channel record sheet: cable type, max length class, connector count, board trace length, via count, protection topology, and chassis/ground strategy.
- Mode determinism plan: which EQ/retiming states are allowed to adapt, which must be fixed, and which registers must be logged at boot and after relock.
- Protection + return review: confirm clamp placement, chassis return routing, and that added capacitance does not destroy return loss targets.
- Pass criteria placeholders: return loss ≥ X dB in the relevant band; stub length ≤ X mm; via count ≤ X; PLL rail ripple ≤ X mVrms.
- Evidence to archive: reviewed schematics, PCB stackup notes, impedance report, and a frozen BOM revision.
- 12G-capable 75 Ω SDI coax (example): Belden 1694A
- Mini 75 Ω SDI coax (example): Belden 1855A
- 12G-optimized PCB BNC jack (example): Amphenol RF 031-70536-12G
Gate B — Bring-up (turn “works” into “has margin”)
- Short-cable baseline: capture eye/mask margin, lock time, and error counters. Store the exact EQ/retiming state used.
- Long-cable stress: sweep cable classes and confirm the same pass criteria; record “last-pass” boundaries (length class = X placeholder).
- Temperature drift: validate lock stability and error counters across temperature; log rail voltages and key PLL/EQ status bits.
- Hot-plug behavior: validate recovery time and whether relock is deterministic; confirm no “stuck” EQ/DFE states.
- Reset consistency: after N resets, margin distribution must stay within X (placeholder). Archive register images and event logs.
- Equalizer + reclocker (example): TI LMH1219
- Reclocker fanout (example): TI LMH1226
- Driver + reclocker (example): TI LMH1228
- Reclocking EQ/driver (example): Semtech GS12190
Gate C — Production (fixture consistency and evidence chain)
- Fixture normalization: identify fixture cable bins (loss class), connector wear limits, and a periodic verification routine.
- Counter logging policy: define measurement window, threshold (BER ≤ X placeholder), and how counters are cleared and stored.
- Sampled compliance: define sampling ratio and the evidence format (mask margin ≥ X, JTOL margin ≥ X, lock time ≤ X).
- Reproducibility rule: a known-good unit must pass on any validated station within X margin (placeholder). If not, the station is the suspect.
Gate D — Field diagnostics (minimum viable logs)
- Lock state and mode (CDR/PLL status, relock events)
- EQ/DFE/adaptation state (preset index, convergence flags)
- Error counters with time window and timestamps
- Temperature and rail voltages (at the time of errors)
- Cable/port identity (cable class, connector changes, hot-plug markers)
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FAQs (SDI 3G/6G/12G): fast triage with measurable pass criteria
Each answer is intentionally short and executable. Every item ends with numeric placeholders so teams can align on the same acceptance thresholds across bring-up, compliance, and production.
- X_MASK: eye-mask margin floor (UI or % margin, per rate)
- X_BER + X_SEC: BER / error-count limit over a fixed window
- X_LOCK_MS: max lock / relock time
- X_RL_DB: return loss minimum (dB) in the defined band
- X_TDR_RHO: max reflection coefficient / TDR ripple limit
- X_RIPPLE_MVRMS: PLL/SerDes rail ripple/noise limit (mVrms) in the sensitive band
- X_TEMP_C: temperature corners to validate
- X_RESET_N: number of resets / hot-plug cycles for consistency checks
- X_EMI_DB: EMI margin target (dB) at the relevant limit line
- X_BIN: cable bin boundary metric (loss/RL/TDR) and limits
1) Long cable fails 12G mask, short cable passes — check reflection first or EQ margin first?
Likely cause: a hidden reflection point (adapter/connector/via stub) or insufficient high-frequency boost for the actual channel loss.
Quick check: run TDR/return-loss around the port and compare the location of the largest reflection with physical features; then lock a known-good EQ preset (no adaptation) and re-check mask.
Fix: if reflection dominates, remove adapters, upgrade to 12G-rated 75Ω BNC (e.g., Amphenol RF 031-70536-12G), shorten/avoid stubs; if loss dominates, use a reclocking EQ/driver with sufficient reach (e.g., TI LMH1219 / LMH1229 / LMH1239, Semtech GS12190). Verify package/suffix/availability.
Pass criteria: return loss ≥ X_RL_DB, TDR reflection ≤ X_TDR_RHO, and mask margin ≥ X_MASK at the target cable class.
2) CDR locks but intermittent glitches/dropouts — supply-noise injection or EQ mis-convergence?
Likely cause: rail ripple coupling into CDR/PLL jitter, or adaptive EQ converging to a marginal state that drifts with temperature/load.
Quick check: correlate errors with rail ripple and load events; log EQ state + lock events before/after a dropout; temporarily disable adaptation and force a stable preset for A/B comparison.
Fix: tighten PLL/SerDes decoupling and isolation (short loops, keep switch-node return away); if needed, move sensitive rails to a low-noise LDO (e.g., TPS7A4700 or ADM7150). For EQ stability, bound adaptation (limit presets) or switch to a reclocking device with readable status (e.g., LMH1219 / GS12190). Verify BOM and noise band fit.
Pass criteria: rail noise ≤ X_RIPPLE_MVRMS (sensitive band), BER ≤ X_BER over X_SEC, and relock time ≤ X_LOCK_MS.
3) Swapping BNC/adapters breaks stability — how to locate a “hidden reflection point” fast?
Likely cause: adapter/connector launch discontinuity causing a localized reflection that collapses the eye at 12G.
Quick check: TDR with and without the adapter, then subtract traces to isolate the incremental reflection; confirm with a return-loss sweep and note the strongest peak frequency.
Fix: eliminate adapters; use 12G-optimized 75Ω parts end-to-end (example: Amphenol RF 031-70536-12G), and pair with a known 12G-capable cable (example: Belden 1694A; compact runs: Belden 1855A). Verify mechanical fit and vendor equivalents.
Pass criteria: adapter incremental TDR ripple ≤ X_TDR_RHO and return loss ≥ X_RL_DB; eye-mask margin ≥ X_MASK.
4) Adaptive EQ becomes worse on some cables — how to tell it converged to a wrong solution?
Likely cause: adaptation locks into a local optimum (wrong CTLE/DFE combination) or keeps hunting due to borderline SNR/ISI.
Quick check: log final EQ state across X_RESET_N repeated relocks; if states vary widely for the same cable, adaptation is not deterministic. Compare against a forced “golden preset” known to pass.
Fix: bound adaptation (limit preset search range), or switch to “coarse sweep → fine tune → hold” policy; if the device supports it, expose EQ index/status to firmware logs. If margin is fundamentally insufficient, upgrade EQ reach (e.g., TI LMH1229/LMH1239, Semtech GS12190). Verify reach vs cable class.
Pass criteria: after X_RESET_N relocks, EQ state variance within a defined band (≤ X states) and mask margin ≥ X_MASK with BER ≤ X_BER.
5) Behavior changes after reset (sometimes pass, sometimes fail) — which 3 fields to check first?
Likely cause: non-deterministic initialization (strap/register mismatch), adaptive EQ not reset cleanly, or counters/windows not aligned.
Quick check: (1) CDR/PLL lock mode + relock count, (2) final EQ preset/index + “adapt locked” flag, (3) error counter window definition (clear point + X_SEC timing).
Fix: enforce a single boot-time register image, clear/seed adaptive logic deterministically, and make counter collection window explicit. Prefer devices with readable states (e.g., TI LMH1219, Semtech GS12190) and store the register snapshot per boot. Verify interface and address map.
Pass criteria: across X_RESET_N resets, mask margin distribution within X and BER ≤ X_BER over X_SEC, with lock time ≤ X_LOCK_MS.
6) Jitter worsens after inserting ANC/audio — check CDC/FIFO first or pathological patterns first?
Likely cause: insertion occurs across a clock-domain boundary (CDC/FIFO behavior) or introduces bursty transitions that increase CDR stress (pattern sensitivity).
Quick check: compare jitter/mask with insertion disabled vs enabled; log FIFO level/overflow flags and insertion timing relative to the reclock point (before/after retimer).
Fix: move insertion to a deterministic clock domain (prefer after a stable reclock), set FIFO depth/thresholds with headroom, and avoid insertion modes that create large burst discontinuities. If needed, insert via a device with robust reclocking and monitorable status (e.g., LMH1226/LMH1228). Verify system architecture.
Pass criteria: insertion ON/OFF delta: mask margin drop ≤ X, jitter increase ≤ X, and BER ≤ X_BER over X_SEC.
7) Hot-plug increases dropouts — which ESD/ground-potential path is most common?
Likely cause: ESD or ground-potential discharge returns through signal ground instead of chassis, upsetting the receiver/PLL or creating a new reflection point via protection parasitics.
Quick check: inspect clamp placement and return routing; correlate hot-plug events with lock-loss counters and rail dips; repeat X_RESET_N hot-plug cycles and log recovery time.
Fix: clamp to chassis at the connector with shortest return; keep protection capacitance ultra-low and layout compact. Example TVS arrays: Semtech RClamp0524P, Littelfuse SP3003-02XTG. Verify capacitance class, footprint, and channel assignment.
Pass criteria: hot-plug drop rate ≤ X over X_RESET_N cycles; recovery time ≤ X_LOCK_MS; no mask regression beyond X.
8) EMI fails but the link is stable — start with Tx edge/boost, pre-emphasis, or return-path strategy?
Likely cause: common-mode radiation from shield/return currents or overly aggressive edge/boost increasing high-frequency emissions.
Quick check: A/B test: keep link settings constant and change only chassis/shield bonding strategy; then compare with a minimal-edge preset (reduced slew/boost) while monitoring mask margin.
Fix: first optimize return/shield-to-chassis paths (least SI impact); only then reduce edge rate/boost or pre-emphasis. If a driver with adjustable output is used (e.g., TI LMH1228), define a “compliance preset” locked in production. Verify preset mapping and compliance procedure.
Pass criteria: EMI margin ≥ X_EMI_DB while mask margin ≥ X_MASK and BER ≤ X_BER over X_SEC.
9) Errors appear only at high temperature — EQ margin shortfall or PLL spur/ref drift?
Likely cause: channel loss increases and pushes EQ to the edge, or temperature shifts reference/PLL behavior causing spurs/jitter increase.
Quick check: at X_TEMP_C, log EQ index/taps and lock stability; compare rail noise and any periodic error bursts (spur-like behavior). Repeat with a shorter cable to separate channel vs PLL.
Fix: if EQ is saturated, reduce reflections and upgrade reach (e.g., LMH1229/LMH1239 or GS12190); if PLL spur/noise is dominant, tighten rail noise (LDO/decoupling) and validate refclk routing/return continuity. Verify temperature stability of the full clock chain.
Pass criteria: at X_TEMP_C, mask margin ≥ X_MASK, BER ≤ X_BER over X_SEC, lock remains stable (relock count ≤ X).
10) Same board, different fixtures give different results — what record field is usually missing?
Likely cause: fixture cable/adapter loss and reflection are not binned or tracked; measurement windows/counter resets differ between stations.
Quick check: require each station to log: cable ID + bin, adapter count, last calibration date, and the exact counter window (X_SEC) + clear timing. Run a known-good unit across stations to detect station bias.
Fix: create fixture cable bins (e.g., Belden 1694A/1855A classes) using a measurable metric (RL/TDR/loss) and lock the station procedure. Remove or standardize adapters using 12G-rated connectors (e.g., 031-70536-12G). Verify local equivalents.
Pass criteria: station-to-station delta in mask/BER ≤ X, and correlation pass on a golden unit across all stations.
11) Enabling return/monitoring reduces main-link margin — how to identify the coupling mechanism quickly?
Likely cause: interference via shared return/shield currents, power-rail modulation, or bursty activity creating pattern-dependent CDR stress.
Quick check: A/B toggle return-channel and log (a) spur-like periodic errors (power/shield coupling), (b) EQ state shifts (ISI change), and (c) rail ripple change.
Fix: isolate returns (chassis bonding strategy), isolate power domains (bead + local decoupling), and enforce scheduling/bounding of return activity. If needed, add robust reclocking at the boundary (e.g., LMH1226/GS12190) and keep adaptation stable. Verify architecture constraints.
Pass criteria: return ON/OFF causes Δmask ≤ X and ΔBER ≤ X (same window X_SEC); no new relock events beyond X.
12) Yield improves after cable binning — how to choose bin metrics and thresholds?
Likely cause: cable assemblies vary in loss and return loss; the weakest tail dominates production failures unless binned.
Quick check: pick one primary metric that correlates with failures (e.g., RL floor or TDR ripple) and validate correlation on a small sample; keep the test setup and termination identical across stations.
Fix: define bins by measurable limits (X_BIN) such as RL ≥ X_RL_DB and TDR ≤ X_TDR_RHO, and map each bin to an allowed EQ preset range (bounded adaptation). Standardize to known-good cable families (e.g., Belden 1694A / 1855A) to reduce variance. Verify local sourcing.
Pass criteria: for each bin, mask margin ≥ X_MASK and BER ≤ X_BER over X_SEC, with consistent lock time ≤ X_LOCK_MS.
