System Role & Isolation Use Cases for Isolated Current Sense

Isolated current sense uses a shunt resistor on the high-voltage or noisy side to measure current while keeping the low-voltage control domain galvanically separated. The goal is to transfer accurate current information across an isolation barrier without exposing the MCU or control logic to hazardous voltages or harsh dv/dt.

In this page we focus on shunt-based isolated current sensing built around isolated amplifiers or sigma-delta modulators. These devices convert the small shunt voltage into an analog or digital representation that safely crosses the isolation barrier and feeds downstream ADCs, FPGAs or MCUs for control, protection and monitoring.

Typical isolation use cases include:

• PFC / AC-DC primary current loop — sensing boost inductor or bus current on the hot side to stabilise power factor and protect the front-end.
• EV traction inverter phase or DC bus current — measuring high dv/dt motor phase currents or the traction bus in 400–800 V drive systems.
• Battery stack high-side current sense — monitoring pack current on the high side while keeping BMS controllers referenced to a safer low-voltage domain.
• Industrial drives and servo systems — isolated measurement of phase and bus currents in noisy inverter cabinets for closed-loop control and protection.

What this page covers — and what it does not:

We concentrate on shunt-based isolated current sense using isolated amplifiers and sigma-delta modulators. Magnetic or contactless current sensors such as Hall, fluxgate, CT or Rogowski coils, as well as non-isolated low-side and high-side shunt amplifiers, are handled in separate dedicated pages.

General isolation amplifiers, digital isolators and standalone isolated ADCs are only discussed here in the context of their role inside a shunt-based current sense chain. Their broader system-level use belongs to other isolation and ADC topics within the Current Sensing & Power / Energy Measurement domain.

Isolated Current Sense Topologies with Shunt, Amplifier and ΣΔ

Most isolated current sense implementations start with a shunt resistor in the power path, but they differ in how the shunt voltage is converted, isolated and presented to the control domain. The main choices revolve around where the isolation barrier sits, whether the signal crosses as an analog voltage or digital bitstream, and how much bandwidth, latency and implementation effort the system can tolerate.

This section groups shunt-based isolated current sense into three practical topologies: a shunt followed by an isolated amplifier, a shunt feeding a sigma-delta modulator with digital isolation, and integrated isolated current sense ICs that combine several functions in a single package.

Key Parameters and Error Budget for Isolated Current Sense

The accuracy of an isolated current sense channel is set by the entire chain from shunt resistor to digital output, not by a single amplifier or sigma-delta modulator specification. Shunt tolerance and self-heating, front-end gain and offset, isolation channel behaviour, filtering, quantisation and the host-side ADC all contribute to the final error budget.

This section outlines the core datasheet parameters to watch and shows how to break down a realistic error budget. The aim is to give you a checklist you can translate directly into a spreadsheet and into system-level accuracy requirements for your isolated current sense channels.

Shunt & Current Path

The shunt and its current path define the fundamental signal level and a large fraction of the long-term drift. You should characterise full-scale and peak current (IFS, Ipeak), nominal and peak power (Pnom, Ppeak), resistance and tolerance (Rshunt) and temperature coefficient (tempco) as early as possible.

A typical design window is a full-scale shunt drop of roughly 50–200 mV. Lower values reduce power loss and self-heating but push the front-end into a noise- and offset-dominated regime. Higher values improve signal-to-noise ratio but raise power dissipation, temperature rise and the risk of overstress during faults. Peak current and short-circuit conditions must be checked against both continuous and pulse power ratings.

Mechanical style and footprint also matter: SMD, four-terminal shunts, and bar-type resistors offer different trade-offs between thermal performance, Kelvin routing options and assembly cost. Even a 1 % shunt tolerance plus several percent of self-heating drift can consume a large portion of a 0.5 % system accuracy target if it is not actively budgeted and, where possible, calibrated.

Amplifier or ΣΔ Front-End Specifications

The isolated front-end — whether it is an amplifier or a sigma-delta modulator — converts the shunt voltage into a more robust signal. Key parameters include gain and gain error, offset and drift, integral non-linearity (INL), noise density / RMS noise, input common-mode range and operating temperature range.

Gain and gain error determine how much of the ADC input range is used at full current and directly map into scale error. Offset and its drift set how cleanly you can resolve low currents and detect near-zero or leakage conditions without large residual readings. Noise density and integrated RMS noise must be small compared to the shunt drop at the minimum current you care about, otherwise the effective resolution collapses in light-load regions.

Bandwidth and step response specifications tie directly into control-loop dynamics and protection response time. Small-signal bandwidth determines how quickly the channel can track current ripple and control perturbations, while large-signal settling time determines how quickly a fault or step load appears at the ADC. The input common-mode range must comfortably cover the shunt voltage location within the high-voltage domain over tolerances and fault conditions.

Isolation Channel Specifications

The isolation channel adds its own constraints on safety and signal quality. You should review working isolation voltage, surge rating and insulation class (functional, basic, reinforced) against the system long-term DC bus voltage and the relevant standards for your market. These figures determine whether the sense chain can safely sit between the high-voltage domain and low-voltage control electronics.

CMTI (common-mode transient immunity) is a critical dynamic parameter in inverter and PFC applications. High dv/dt edges on the power stage can corrupt the measured signal if the isolation channel or internal encoding is not robust. It is important to distinguish typical CMTI numbers from guaranteed minimum ratings, and to ensure your dv/dt envelope has comfortable margin below the worst-case specification.

Channel propagation delay, skew and jitter become important when multiple current channels must be sampled coherently, such as three-phase motor control or multiphase converters. Mismatched delays between phases distort computed quantities like torque and power. For sigma-delta based links, these timing effects must be viewed together with modulator clocking and digital filter latency.

Example Error Budget for an 800 V, ±100 A Rail

As a concrete starting point, consider an 800 V DC bus with a full-scale current of ±100 A and a target measurement accuracy of 0.5 % at room temperature. A sensible budget might allocate roughly half of the error to the shunt and half to the isolated measurement chain, leaving some room for layout, CMTI and host-side effects.

One example split is to assign around 0.25–0.30 % to the shunt tolerance and self-heating drift, assuming a tight-resistance, low-tempco part and controlled thermal environment. The isolated amplifier or sigma-delta front-end might then be allowed around 0.15–0.20 % combined gain error, offset and drift. The remaining 0.10–0.15 % can be reserved for filter shape, quantisation and host ADC resolution limits.

In practice, you should translate this structure into a spreadsheet or simple script with rows for each error contributor and columns for nominal, worst-case and temperature-extended conditions. That framework makes it much easier to see which block is dominating the budget and where calibration, trimming or tighter components provide the best return on cost and complexity.

Design Flow: From High-Side Shunt to Host Controller

Designing an isolated current sense channel is a system exercise, not just a matter of picking one IC. The flow runs from placing and sizing the shunt in the power stage, through choosing a topology and front-end, to planning supplies, isolation, sigma-delta data paths and ultimately validating performance on the bench. The steps below can be copied into a design report or specification as a structured design checklist.

1. Analyse system voltages, topology and grounding. Start by summarising bus voltages, AC/DC or inverter topology and the chosen grounding scheme. Decide whether the current sense channel must provide functional isolation, basic or reinforced safety isolation, and whether the shunt will sit on the bus, phase leg or return path. This step defines the required working isolation voltage, dv/dt envelope and which side of the isolation barrier owns the current measurement circuitry.
2. Select the shunt resistor and current path. Choose a shunt value that yields a practical full-scale drop (often 50–200 mV) at the required IFS and confirm that Ipeak and fault currents do not exceed nominal and pulse power ratings. Consider package style, Kelvin connection options, thermal resistance and how self-heating will impact drift. Decide whether you sense on the DC bus, motor phase, or a filtered branch and capture this in the power stage floorplan.
3. Choose an isolated current sense topology. Based on control-loop bandwidth, protection response time, resolution and software constraints, select between a shunt plus isolated amplifier, a shunt plus sigma-delta modulator with digital isolation, or an integrated isolated current sense IC. Amplifier-based options are attractive for high-bandwidth control with simple analog interfaces, sigma-delta suits high-resolution and metering-class applications, and integrated ICs minimise design effort and board area. Capture the primary choice and any viable backup paths for later risk assessment.
4. Select the amplifier or sigma-delta front-end. For the chosen topology, filter candidate parts by bandwidth, step response and noise against your control and protection requirements. Check gain error, offset, drift and INL against the error budget from the previous section, and verify that the input common-mode range safely covers the shunt location and fault scenarios. At the same time, confirm isolation ratings, CMTI, package style and temperature range align with system-level safety and layout constraints.
5. Plan supplies and isolation placement. Decide how the front-end will be powered on the high-voltage side: with an isolated DC/DC, a bootstrapped rail or a local supply referenced to the shunt node. Choose where the isolation barrier will physically sit on the PCB and how traces will cross it. Define whether the signal crosses as an analog voltage, a sigma-delta bitstream or a framed digital interface such as SPI or LVDS, and ensure the chosen pinout and connector strategy can support multiple channels without routing bottlenecks.
6. Define the sigma-delta data path (if used). For sigma-delta based designs, set the modulator frequency, oversampling ratio and sinc filter order to balance noise, bandwidth and latency for the intended role. Decide whether the digital filter will run in MCU software, dedicated peripherals or an FPGA, and define how multiple phases will share clocks and frame alignment. Capture worst-case latency and update rate so that control engineers can verify loop stability and protection timing with realistic numbers rather than ideal assumptions.
7. Validate performance and add margin with lab measurements. Once hardware is available, measure static accuracy, noise, drift and dynamic response over load, temperature and dv/dt conditions that reflect real operation. Exercise overcurrent and short-circuit events, power-up and power-down sequences and any abnormal operating modes. Compare the measured results against the calculated error budget and timing requirements, then add design margin for production variation, ageing and environmental spread by tightening component choices or adjusting the topology where needed.

Isolation Ratings, Standards and Creepage in Isolated Current Sense

Isolation markings on isolated current sense devices describe both electrical strength and the intended safety role. Functional isolation separates reference domains and reduces noise coupling but does not by itself protect users from electrical shock. Basic isolation provides a single barrier for shock protection under normal operation, while reinforced isolation is a single barrier designed to offer protection equivalent to double insulation. Double insulation uses two independent barriers and is typically reserved for very strict safety regimes and user-accessible equipment.

Datasheets often reference standards such as IEC 61010-1 for measurement and control equipment, IEC 62368-1 for audio/video and ICT, UL 1577 for component isolation testing and various CSA or VDE approvals. These entries indicate which safety frameworks the device can fit into, but they are not a substitute for a full system-level safety assessment. From a selection perspective you should confirm that the device's working voltage, pollution degree, overvoltage category and insulation class align with your DC bus voltage, environment and regulatory targets.

Final responsibility for compliance typically lies with the OEM safety and compliance team. Their job is to interpret how the isolated current sense device fits into the end-product insulation scheme, creepage and clearance model and long-term reliability requirements. Your job as a hardware designer is to make sure the part is technically capable of meeting those requirements and that the datasheet provides the necessary documentation trail.

Creepage and clearance distances largely determine which package families are suitable for a given bus voltage and insulation class. Narrow-body SOIC packages usually offer only a few millimetres of creepage and are often limited to functional or basic isolation at moderate working voltages. Wide-body SOICs and specialised isolation packages extend creepage to 7–10 mm or more, enabling reinforced isolation ratings on 600–1200 V rails when combined with appropriate PCB design and environmental assumptions.

For higher-voltage systems and harsh environments, module-style or transfer-moulded packages with extended creepage paths may be required to meet both surge and lifetime working voltage constraints. These choices interact directly with the mechanical layout of your inverter or power stage, because connector spacing, clearance slots and pollution degree all influence the effective creepage that can be claimed at the assembly level.

To avoid ambiguity during sourcing, the isolation requirements for the current sense channel should be expressed explicitly in the BOM or electrical specification. Rather than simply writing “isolated current sense IC”, specify the insulation class (functional, basic, reinforced), continuous working voltage, surge rating and minimum creepage, as well as any preference for wide-body SOIC or module-style packages.

A typical BOM line might read: “Isolated current sense, reinforced insulation, working voltage ≥ 800 V DC, surge rating per IEC 61010-1, creepage ≥ 8 mm, wide-body SOIC preferred.” Detailed treatment of insulation coordination, altitude derating and lifetime modelling belongs to a dedicated isolation and safety topic, which this page can cross-link for deeper study.

ΣΔ Modulator to Host Filter Chain: Noise, Bandwidth and Latency

A sigma-delta based isolated current sense channel converts the shunt voltage into a high-frequency bitstream on the high-voltage side, transports that stream across an isolation barrier and reconstructs a current value with a digital filter on the control side. The three dominant design dimensions are in-band noise, usable bandwidth and end-to-end latency, all of which are set by the modulator clock, oversampling ratio and filter structure.

This section outlines how the sigma-delta modulator, sinc filter and clocking interact, and how to choose settings that balance control-loop responsiveness against metering precision. The goal is not to teach sigma-delta theory but to give a practical mental model you can use when selecting isolated modulators and configuring host-side filters.

Modulator Basics: Encoding the Shunt Voltage

In a sigma-delta based isolated current sense channel, the high-side modulator continuously samples the shunt voltage and generates a single-bit or low-resolution bitstream at a high clock frequency. Typical modulator clocks sit in the 10–20 MHz range, with the instantaneous density of ones and zeros representing the underlying analog signal after noise shaping. The raw bitstream by itself is not yet a usable current measurement; it is the input to a decimating filter on the control side.

• High-side ΣΔ turns the shunt voltage into a high-rate bitstream plus clock.
• Clock quality and jitter at this stage directly influence noise and distortion.
• The bitstream is designed for robust transport over digital isolation rather than direct interpretation.

Sinc Filter and Oversampling Ratio

On the control side, a sinc or similar decimation filter integrates the bitstream over a window and outputs samples at a much lower rate. The oversampling ratio (OSR) and filter order determine both in-band noise and passband bandwidth: increasing OSR and filter order reduces noise but narrows the bandwidth and lengthens group delay. Sinc1 filters provide minimal noise improvement and very low delay, while sinc3 filters are popular for high-accuracy metering at the cost of higher latency.

• Sinc1: lowest delay, modest noise improvement, suited to simple control roles.
• Sinc2: balances noise and delay for many closed-loop current sense applications.
• Sinc3 and above: strong noise suppression for metering and precision monitoring.
• Higher OSR always trades wider averaging windows for better SNR but slower response.

Control vs. Metering Use Cases

Current sense channels used inside fast control loops, such as FOC motor control or inner current loops in digital power supplies, can typically tolerate only tens of microseconds of additional latency. In these applications, OSR and filter order are usually kept low enough to preserve bandwidth while achieving just enough noise reduction to close the loop robustly. A small amount of extra noise is often acceptable if the response time is tight.

Metering and long-term monitoring systems prioritise accuracy, stability and line-frequency rejection over reaction time. They can often accept millisecond-level latency, enabling higher OSR and higher-order filters that significantly reduce in-band noise and harmonic artefacts. Designing a sigma-delta chain therefore starts with deciding whether the application behaves more like a control loop or a metering function and choosing filter settings accordingly.

Clocking and Synchronisation Across Multiple Channels

Sigma-delta links are highly sensitive to clock quality. Modulator clock jitter and skew between channels can erode effective resolution and distort comparisons between phases. Wherever possible, multiple isolated current sense channels should share a common, well-controlled clock source or use phase-aligned derivations to keep their bitstreams and decimated outputs time-coherent.

• Use common clocks or synchronised dividers for multi-phase current sense channels.
• Manage jitter to preserve ENOB, particularly in wide-bandwidth control applications.
• Choose whether filters run in MCU software, dedicated peripherals or FPGA fabric.
• Align sampling frames so that per-phase currents are valid at the same instant in time.
• Define worst-case latency and update rate once filter, OSR and clocking are fixed.

Layout, CMTI and EMC for Isolated Current Sense

An isolated current sense channel lives on the same PCB as high dv/dt power stages and fast control logic. Good layout separates the noisy high-current switch loops from a quiet measurement island, keeps loop areas small and routes Kelvin sense traces so that the shunt voltage is picked up cleanly. Poor placement and grounding can defeat even the best isolated amplifier or sigma-delta device.

This section focuses on three practical aspects: where to place the shunt and how to route its sense connections, how to partition grounds and the isolation barrier, and how to evaluate and improve CMTI behaviour on real hardware. Detailed rules for ultra-low-drift Kelvin layout and quiet islands are covered in dedicated zero-drift layout topics.

Shunt Placement and Routing

Shunt placement is a compromise between minimising the high-current loop area and giving the measurement circuit a reasonably quiet environment. Locating the shunt directly in the half-bridge return or phase leg produces the smallest current loop, but also exposes the sense traces to the strongest dv/dt. Placing the shunt nearer the DC link or bus connection can ease routing and reduce switching noise at the cost of a larger current loop.

• Choose shunt locations that minimise the high-current loop between switches, diodes and capacitors, but avoid placing sensitive sense traces directly under or beside the fastest switching nodes.
• Use true Kelvin connections: route a dedicated pair of sense traces from the inner shunt pads, not from the wide copper carrying the main current. Keep these traces tightly coupled, short and away from the power switch nodes.
• Keep the high-current path and the measurement path conceptually separate. The power loop carries amps and nanohenries; the sense loop carries milliamps and microvolts. They should only meet at the shunt pads.
• For zero-drift and microvolt-level sensing, apply stricter Kelvin and quiet-island rules and refer to the dedicated zero-drift current sense layout guidance for more detailed patterns.

Ground Partitioning and Isolation Barrier Placement

An isolated current sense channel naturally divides the PCB into at least two ground domains: a high-side or primary ground that carries power-stage currents, and a low-side or secondary ground that serves the ADC and MCU. The isolation barrier ties these two domains together logically without allowing return currents to flow directly between them on the board copper.

• Define clear primary and secondary ground regions. High-current returns should close locally within the primary domain, while ADC and MCU returns should close within a continuous, low-impedance secondary ground plane.
• Keep the area around the isolation barrier free of unrelated sensitive traces. The device pins see large common-mode transients, and any extra signal routed near the barrier can pick up dv/dt-induced noise.
• Ensure that every signal crossing the barrier has a controlled return path in its own domain. Do not inadvertently create loops where a secondary-side signal references primary ground or vice versa through measurement fixtures or test points.
• If the control side distinguishes analog and digital grounds, place the current sense front-end and ADC input routing in the analog region and merge AGND and DGND at a defined single point near the converter.

CMTI in Practice: Measuring dv/dt and Debugging Symptoms

Common-mode transient immunity (CMTI) limits are typically specified in the tens to hundreds of kilovolts per microsecond. Real inverters and PFC stages can approach these limits under hard-switching conditions. It is therefore important to validate CMTI behaviour on the actual hardware using realistic loads and line conditions rather than relying solely on datasheet numbers.

• Estimate dv/dt at the switching nodes using a high-bandwidth probe or differential probe with very short ground leads. The goal is to establish the envelope of the fastest edges, not to capture every detail of the waveform.
• Watch for current sense outputs that exhibit spikes or steps coincident with switching edges, intermittent saturation behaviour, or random ADC code jumps that correlate with load or line changes rather than real current.
• Improve robustness by adjusting layout around the barrier, shortening and shielding sense paths, and increasing spacing from the highest dv/dt conductors. Adding a modest RC low-pass at the output of an isolated amplifier can reduce spikes, provided the added delay and phase shift are acceptable for the control loop and protection timing.
• Use ground planes, guard traces and layer stack planning to keep sensitive current sense routes away from switch nodes, gate drives and long cable runs that can radiate common-mode disturbances into the measurement island.

Fault Detection and Self-Test Hooks for Isolated Current Sense

A failed current sense channel is itself a safety-relevant fault: it can mislead protection logic, control loops and diagnostic functions. It is therefore essential to define fault types, plausibility checks and self-test hooks for the isolated current sense chain, rather than assuming it always works correctly. This section highlights practical ways to detect failures and to periodically verify channel health.

Fault Types Along the Measurement Chain

Faults can occur at the shunt, in the analog or sigma-delta front-end, across the isolation link or in the digital path to the host processor. Some faults are hard, such as open circuits and shorts; others are soft, such as loss of synchronisation or corrupted data. A robust diagnostic concept should cover both categories.

• Open shunt or shorted shunt: an open shunt can lead to dangerously underestimated current, while a shorted shunt removes the sense element and can produce near-zero voltage at the front-end even under high current conditions.
• Amplifier or sigma-delta saturation and overflow: prolonged output near the supply rails or bitstreams that degenerate to all ones or zeros indicate that the front-end has exceeded its input range or lost bias.
• CRC failures, frame errors and loss of synchronisation: for digitally transported measurements, repeated checksum errors, framing issues or stagnant data streams are clear indicators of link-level problems.
• Supply and reference problems: loss of the high-side supply, reference faults or undervoltage conditions can produce frozen readings or values that are inconsistent with any plausible current level.

Plausibility Checks and Cross-Checks

Even when no explicit fault flag is raised, the current sense output can be checked for plausibility against other measured quantities. These cross-checks compare phase currents with bus power, torque, speed or operating quadrant to detect subtle failures that would otherwise go unnoticed.

• Compare the sum of phase currents and the measured bus power. If the inverter appears to deliver significant power while one phase current remains near zero or saturates, the affected current channel should be flagged as suspect.
• Cross-check current against voltage, speed and torque. For example, high current readings with low torque and minimal heating are inconsistent and may indicate a measurement issue rather than a real load condition.
• Check current direction against the expected power-flow quadrant. In regenerative or charging modes, the sign of the measured current should match the direction of power flow. Persistent disagreements are a strong plausibility violation.
• Combine multiple rules into a graded diagnostic scheme, where mild inconsistencies raise warnings and repeated or severe violations are treated as faults that limit torque or disable certain operating modes.

Self-Test Hooks and Health Monitoring

Self-test mechanisms provide a way to exercise the measurement chain with known stimuli and to verify its response at power-up or periodically during operation. Designing these hooks in early makes it easier to validate the system in production and to track degradation over the product lifetime.

• Use built-in test modes where available. Some isolated current sense devices or hosts can output fixed steps, ramp patterns or known bit sequences that the MCU can recognise to confirm link integrity and decoding.
• Where practical, provide a controlled injection path for a small test current or known load. Applying a repeatable stimulus during a safe operating window allows the ECU to check that the measured value falls within a defined tolerance band.
• Combine analog checks, such as verifying that outputs are not stuck near the rails and that supplies and references are within range, with digital checks on frame rate, CRC error counts and update counters.
• Integrate self-test and plausibility results into the overall diagnostic framework so that the system can apply derating, torque limits or controlled shutdown when the isolated current sense channel can no longer be trusted.

Vendor Mapping for Isolated Current Sense

This table is a navigation aid rather than a full parametric comparison. It maps the main shunt-based isolated current sense approaches — isolated amplifiers, isolated delta-sigma modulators and more integrated solutions — onto the portfolios of seven major vendors. Use it to find roughly equivalent families when you start from one supplier, then follow brand-specific pages for deep datasheet reading and second-source strategy.

Each row highlights representative families, typical interfaces and a one-line selection hint. Noise, accuracy, temperature behaviour and package details are intentionally kept out of this overview to avoid overlap with dedicated vendor and product-level pages.

BOM and Procurement Notes for Isolated Current Sense

This section shows how to write an isolated current sense channel clearly into your BOM: which topology you use, what shunt is planned, what isolation level and bandwidth you need, and which interfaces are acceptable. With these fields in place, suppliers can propose parts that actually fit your current, safety and control requirements.

FAQs on Isolated Current Sense (Amplifier and ΣΔ)

These twelve questions cover the most common design decisions around isolated current sense: topology choice, shunt sizing, isolation, layout, digital timing, diagnostics and sourcing. Each answer is short enough to scan quickly but concrete enough to copy into your own design notes or review checklist.