123 Main Street, New York, NY 10001

Submit Your BOM

FDA / SE↔Differential Converter: VOCM Control & ADC Drive

FDA / SE↔Differential Converter: VOCM Control & ADC Drive

← Back to:Active Filters & Signal Conditioning

An FDA SE↔Differential converter is a controlled differential driver: it sets Vdiff and VOCM while staying stable and settled into the real load (R||C + ADC kickback). Most field failures come from missing headroom, poor symmetry, and an untuned Riso/Cshunt interface—budget these and the chain becomes predictable.

H2-1. What an FDA SE↔Differential Converter Really Does

An FDA-based SE↔DIFF stage is a controlled common-mode + differential drive system that must meet amplitude, VOCM, and settling into a dynamic load at the same time—especially when the load is an ADC input.

A) The correct mental model (3 variables that own most outcomes)

  • Vdiff (differential amplitude): defines headroom, distortion, and how much the driver must swing.
  • VOCM (output common-mode): aligns the driver outputs to the ADC/link input window and sets symmetry conditions.
  • Load dynamics (R||C + switching behavior): decides stability, step response, and settling error at the sampling instant.

B) Typical use cases (why the FDA approach is preferred)

ADC driver front-end
Requires tight VOCM alignment, low distortion under load, and settling that holds at the sampling edge.
Differential link / isolator interface
Needs a defined common-mode window, symmetric impedance, and predictable swing to maintain margin across wiring and temperature.
Differential mod/demod stages
Benefits from symmetry and controlled CM behavior to reduce even-order artifacts and prevent CM→DIFF conversion.

C) The 3 outputs that must be met simultaneously (with field signatures)

1) Differential amplitude (Vdiff)
Failure signature: rail clipping or THD rise at large signals.
Quick check: confirm VOUTP/VOUTN stay within output swing limits with guardband.
2) Output common-mode (VOCM)
Failure signature: even-order spurs, code-dependent artifacts, or unexpected headroom loss.
Quick check: measure VOUT_CM and compare it to the ADC/link CM target during operation.
3) Stability & settling into a dynamic load
Failure signature: stable on a resistor, but rings or degrades SFDR when connected to the ADC.
Quick check: compare step response and FFT with/without the ADC attached; sampling-rate sensitivity hints load dynamics.

D) Two common misconceptions (and why they break designs)

  • “It’s just an op-amp plus an inverter.” Incorrect: the stage includes a common-mode control loop and the outputs must remain matched and stable under load.
  • “Differential automatically improves noise.” Not guaranteed: any asymmetry (network mismatch, layout, loading) can convert common-mode disturbance into differential error.

Scope lock (to prevent content overlap)

Not covered here: filter order/response shaping, fc:fs anti-alias planning.
See instead: Fully-Differential Filters; Anti-Alias / Reconstruction Interface.
FDA SE to Differential Converter System Model Block diagram: single-ended input into an FDA core producing differential outputs with a VOCM common-mode control loop, driving an ADC dynamic load modeled as R||C with sampling kickback. SE IN FDA SE↔DIFF ADC DIFF IN VOCM Load R||C kickback System variables: Vdiff • VOCM • Dynamic load

H2-2. Architecture Map: 4 Ways to Do SE↔Diff (and Why FDA Wins in ADC Drivers)

SE↔DIFF can be implemented in multiple ways, but ADC-facing designs usually demand VOCM control, symmetry under load, and settling robustness. A consistent comparison axis prevents mis-selection.

A) Comparison axes (the only ones that matter for first-pass selection)

  • VOCM control: can the output common-mode be defined and held across dynamics?
  • DC capability: does the method support near-DC content and offset management?
  • Isolation need: galvanic isolation or high-CMR environments may force transformer/balun.
  • ADC drive fitness: stability and settling into switching + capacitive inputs (not just resistors).
  • Linearity & symmetry: how easily mismatch creates even-order distortion and CM→DIFF conversion.

B) The four approaches (each with best-fit + risks)

1) Transformer / Balun
Best for: isolation, high-frequency coupling, hostile CM environments.
Tradeoffs: poor/undefined DC behavior, amplitude/phase variation vs frequency, size and repeatability constraints.
Risk flag: near-DC or strict low-frequency linearity requirements.
2) Dual op-amp (two-path SE→P/N)
Best for: flexible general-purpose conversion when constraints are mild.
Tradeoffs: matching complexity, CM behavior not inherently controlled, spurs from asymmetry are common.
Risk flag: tight SFDR targets or heavy ADC input loading.
3) FDA (Fully-Differential Amplifier)
Best for: ADC drivers and differential links that need explicit VOCM control and symmetric drive.
Tradeoffs: sensitive to load C and sampling kickback; requires Riso/Cshunt-style interface tuning.
Risk flag: assuming “resistor-load stability” guarantees ADC-load stability.
4) Fully-differential filter/driver chain
Best for: response shaping + differential drive as a unified block.
Tradeoffs: higher design coupling (stability, Q/tolerance, group delay), more parameters to validate.
Risk flag: when the primary goal is filter order/group delay—this belongs to the dedicated filter pages.

C) Quick decision rules (fast triage without over-explaining)

  • Isolation or high RF coupling dominates? Start with transformer/balun.
  • ADC-facing, strict SFDR/settling, defined VOCM needed? Start with an FDA.
  • Response shaping (order/group delay) is the main deliverable? Use the fully-differential filter pages as the owner.
Scope lock:
This page owns FDA-based SE↔DIFF conversion (VOCM control + drive/settling behavior). Filter order, magnitude/phase shaping, and fc:fs planning are owned by sibling filter/interface pages.
SE to Differential Architecture Map (4 Approaches) Four-panel comparison: transformer/balun, dual op-amp, FDA, and fully-differential filter chain. Each panel indicates VOCM control, DC capability, isolation, and ADC drive fitness. 4 ways to do SE↔DIFF (selection axes: VOCM • DC • Isolation • ADC drive) Transformer / Balun SE DIFF Isolation DC ✕ VOCM △ Dual Op-Amp SE DIFF Match △ VOCM △ ADC △ Fully-Diff Filter Chain SE FD Filt DIFF Response Complex △ VOCM ✓ FDA (ADC Driver) SE FDA ADC VOCM ✓ ADC ✓ DC ✓

H2-3. VOCM and Level Shifting: The Common-Mode Loop You Must Design (Not Assume)

VOCM is a system reference, not an arbitrary DC level. Its source impedance and noise enter the common-mode loop and can show up as output error or even-order spurs when symmetry is imperfect.

A) VOCM source priority (choose the most “reference-like” source)

1) ADC VOCM pin (preferred)
Best alignment to the ADC input window. Reduces CM mismatch risk across operating modes.
2) System reference / internal CM node
Useful when multiple stages share a CM target, or the ADC has no VOCM output.
3) Buffered VOCM
Required for fan-out, long routing, or when a low-impedance CM node is needed to avoid impedance injection.
4) Divider-derived VOCM (last resort)
Only acceptable when bias current, leakage, and drift are within the error budget and the node is made “reference-like”.

B) How VOCM should enter the FDA (direct vs RC vs buffer)

Direct drive
Cleanest dynamics when VOCM is low-impedance and quiet. Often the best match for ADC-provided VOCM.
RC-filtered VOCM
Reduces high-frequency CM noise injection. Watch slow recovery after mode changes and startup, and avoid creating a weak CM node.
Buffered VOCM
Use when VOCM must drive multiple channels, traverse noisy areas, or when source impedance causes measurable CM movement.

C) Common-mode dynamics: the injection paths that create real errors

  • Noise injection: VOCM noise is “tracked” by the CM loop and appears as output common-mode movement.
  • Impedance injection: VOCM source impedance turns CM-loop input current and coupled currents into voltage error at the VOCM node.
  • CM→DIFF conversion: any asymmetry (network mismatch, unequal loading, layout imbalance) converts CM movement into differential error (often visible as even-order spurs).
  • Dynamic coupling: ADC sampling currents can disturb the CM node through parasitics and return paths if VOCM is not locally controlled.

D) Single-supply level shifting: a headroom-budget method that prevents surprises

  1. Lock VOCM to the receiver/ADC input window target (preferred: ADC VOCM pin).
  2. Translate Vdiff into each output swing around VOCM (both outputs must stay inside the swing limits with guardband).
  3. Guardband for load and temperature: output swing and linearity typically degrade at heavier loads and across temperature.
  4. Fix order: adjust VOCM first, then gain, then loading/interface, then supply rails—avoid changing multiple axes blindly.
Practical warning:
Even when Vdiff looks safe, a wrong VOCM can push one output close to a rail and create distortion or clipping under load.

E) Quick checks (VOCM-only) + pass criteria templates

  • Check 1: measure VOUT_CM at steady state and during activity (mode change / sampling).
  • Check 2: probe the VOCM node ripple; correlate ripple with even-order spurs or sampling-rate-dependent artifacts.
  • Check 3: compare “ADC connected” vs “ADC disconnected” CM movement; large deltas indicate impedance or coupling issues.
  • Pass criteria template: VOUT_CM stays inside the receiver window with margin; CM settles within the required time after changes; spur behavior improves with stronger VOCM control and symmetry.
Scope lock:
This section focuses on VOCM selection, injection paths, and headroom budgeting. Deep reference-noise theory is excluded; response shaping and anti-alias planning are owned by sibling pages.
VOCM Source, Conditioning, and Common-Mode Injection Paths Diagram showing VOCM sources feeding a selector and conditioning options (direct, RC, buffer) into the FDA VOCM pin and CM loop, with labeled noise/impedance injection paths and VOUT_CM measurement point. VOCM path: source → conditioning → VOCM pin → CM loop → outputs VOCM Sources ADC VOCM REF / CM BUFFERED DIVIDER SEL Conditioning DIRECT RC BUFFER FDA CM loop VOCM VOUTP VOUTN VOUT_CM noise injection impedance

H2-4. Gain Setting Networks: Make It Accurate, Matchable, and Not a Noise/Distortion Trap

Gain networks in SE↔DIFF drivers are not “just resistor values”. Ratio matching, symmetry, and loading decide CMRR, even-order distortion, and settling robustness.

A) Network roles (what each resistor “owns”)

RIN / RG (input & gain set)
Defines input impedance and gain ratio. Sets noise and bias-current sensitivity.
RF (feedback)
Controls closed-loop gain and output current demand; influences linearity under load and stability sensitivity.
RT (termination / optional)
Helps match differential links and manage reflections; treat as part of the load and symmetry problem.

B) Why ratio matching dominates (the causal chain to even-order spurs)

Ratio mismatch → unequal gain paths → symmetry breaks → CMRR drops + CM→DIFF conversion rises → even-order distortion/spurs increase
Typical symmetry breakers include: resistor tolerance/TC mismatch, unequal parasitic capacitance, unequal loading (probe/ESD/trace), and inconsistent return paths. The network should be treated as a paired structure, not two independent sides.

C) Resistor value triangle: noise vs bias error vs drive burden

Thermal noise
Larger values raise network noise contribution, especially when the source impedance is high.
Bias & leakage sensitivity
Larger values amplify DC errors from input bias current and leakage paths; symmetry makes this worse if the paths differ.
Drive current & linearity
Smaller values increase feedback/output currents; distortion and settling pressure rise under heavy loads.
Selection order:
Choose topology and gain ratio first → validate noise budget → validate drive burden and headroom → then tune for stability/settling with the ADC interface.

D) How to control mismatch (layout and BOM tactics that actually work)

  • Mirror symmetry: place and route the two halves as a paired structure with equal environment and return paths.
  • Use resistor arrays: matched networks reduce ratio drift and temperature gradients across the pair.
  • Keep thermal symmetry: avoid placing only one side near heat sources or digital hotspots.
  • Optional Kelvin sense: use when DC accuracy is limited by routing resistance or when high currents flow in the feedback path.

E) Quick checks + pass criteria templates (network-focused)

  • Check 1: verify gain with a small-signal sweep; confirm both outputs have matched single-ended amplitude.
  • Check 2: inspect even-order spur sensitivity to symmetry (probe loading and small layout changes can reveal asymmetry).
  • Check 3: compare behavior under balanced vs intentionally imbalanced loading; strong sensitivity indicates weak symmetry margin.
  • Pass criteria template: output amplitude match is within the allowed tolerance; even-order spurs reduce when symmetry is improved; results are robust to normal probing and cabling.
Scope lock:
This section owns gain network roles, ratio matching, and symmetry tactics. Response shaping and anti-alias planning remain on sibling pages.
SE-to-Differential Gain Network with Symmetry and Ratio Matching Mirror-symmetric resistor network around an FDA showing RG and RF pairs highlighted for ratio matching, optional Kelvin sense, and a symmetry axis to emphasize matched layout and loading. Gain network: ratio match + symmetry to protect CMRR and SFDR SE IN FDA SE↔DIFF symmetry RG+ RG− ratio match RF+ RF− VOUTP VOUTN ADC RT opt Kelvin (opt)

H2-5. Output Swing & Headroom Budget: A Simple Spreadsheet-Style Method

Most “clips on the board” failures are not mysteries: they are missing fields in the headroom budget. This section provides a spreadsheet-style method that checks each single-ended node against supply rails, under real load, with guardband for temperature and tolerance.

A) Symbols (keep the math unambiguous)

Vdiff_pp
Differential peak-to-peak output target across VOUTP–VOUTN.
VOCM
Output common-mode target around which both outputs swing (system reference, not an arbitrary DC level).
VOUTP / VOUTN
Single-ended waveforms that must independently stay inside output swing limits with margin.
Key rule:
A safe Vdiff can still clip if VOCM shifts either output too close to a rail. Always budget both single-ended nodes.

B) Headroom budget (spreadsheet fields to fill)

Inputs
  • V+ / V− (rails)
  • VOCM_target (from receiver/ADC window)
  • Vdiff_pp_target (required differential amplitude)
  • Rload_eq and Cload_eq (include termination, ADC input, parasitics)
Limits
  • Vout_max ≈ V+ − headroom_high
  • Vout_min ≈ V− + headroom_low
  • Iout capability (linear region, distortion target)
  • Guardband (temperature + tolerance margin)
Checks
  • Compute VOUTP_max/min and VOUTN_max/min from VOCM and Vdiff
  • Confirm both outputs remain inside Vout_min..Vout_max with guardband
  • Compute peak output current demand from amplitude and Rload_eq
  • Re-check at worst-case temperature and load

C) Load current is part of headroom (not a separate topic)

Output swing limits tighten as output current increases. A design that “fits” by voltage-only math can fail when real loads (termination, protection, ADC interface) pull higher current or create dynamic demand. Treat the headroom budget as a joint voltage + current check, then apply guardband for temperature and tolerance.

D) Common pitfalls (symptom → reason → corrective direction)

Top clipping
VOCM too high or output current demand pulls the high swing margin smaller → lower VOCM, reduce load, or add guardband.
Bottom clipping
VOCM too low or low-side headroom is overestimated at temperature → raise VOCM or change gain/loading so both nodes stay safe.
One side clips first
Asymmetry (network mismatch, unequal loading, layout imbalance) → fix symmetry before changing rails or gain.
Fails only when ADC is connected
Dynamic input demand increases effective load and reduces margin → treat ADC interface as part of the budget and the next section.

E) Quick checks + pass criteria templates (headroom-only)

  • Check: view VOUTP and VOUTN single-ended for any flattening near rails at worst-case amplitude and load.
  • Check: compute VOUT_CM and confirm it remains near VOCM_target under activity.
  • Check: compare “light load” vs “real load” (termination/ADC connected) to identify current-limited behavior.
  • Pass template: both single-ended nodes maintain the planned margin to rails; no clipping at worst-case conditions; distortion trends align with amplitude changes.
Output Swing and Headroom Budget around VOCM Gauge-style diagram showing supply rails V+ and V−, a VOCM line, and mirror waveforms for VOUTP and VOUTN. Arrows indicate headroom to rails and a guardband marker. Rails + VOCM + single-ended swing → headroom margins Gauge V+ V− VOCM GB VOUTP / VOUTN V+ VOCM V− VOUTP VOUTN headroom hi headroom lo Vdiff_pp

H2-6. Driving an ADC Input: Kickback, Riso/Cshunt, and Settling Time That Datasheets Don’t Hand You

An ADC input is not a static capacitor. Sampling switches create dynamic current pulses that disturb the driver. Treat the FDA + ADC input as one system, then use an interface “toolkit” to control stability and settling.

A) The minimum model: why “just a capacitor” is wrong

  • Sampling switch + sampling capacitor: the load changes with sampling action, not with DC datasheet capacitance.
  • Kickback pulses: charge injection and switch action create short disturbances that can ring the driver and convert to distortion.
  • Correlation: symptoms often move with sampling rate and input frequency, revealing a sampling-related root cause.

B) The interface toolkit: Riso + Cshunt + optional input RC

Riso (isolation)
Improves phase margin by isolating the ADC’s dynamic load from the amplifier output. Trade-off: longer settling if too large.
Cshunt (charge reservoir)
Supplies instantaneous charge locally at the ADC pins and absorbs kickback energy. Helps reduce spikes seen by the driver.
Input RC (optional)
Extra suppression for high-frequency spikes/EMI, but consumes settling margin. Use only when the error budget allows it.

C) Settling from an output-error budget (a step-by-step method)

  1. Define allowed residual error at the sampling instant (the budget is owned by system SNR/SFDR/accuracy targets).
  2. Define the available time window (sampling schedule, mux switching, and aperture requirements).
  3. Stabilize first with a reasonable Riso and a local Cshunt at the ADC pins; keep the interface symmetric.
  4. Iterate using time-domain response and FFT trends until the residual error fits inside the window.
Principle:
Stability is a prerequisite. Settling performance is tuned after stability is secured, not before.

D) A practical tuning order (prevents random trial-and-error)

Step 1 — add Riso
Increase from small values until ringing and marginal stability reduce while settling remains acceptable.
Step 2 — add Cshunt at ADC pins
Increase until kickback spikes and sampling-correlated artifacts diminish; keep routing short and symmetric.
Step 3 — consider input RC (only if needed)
Add only when EMI/spikes remain and the error budget still closes with the reduced settling margin.
Step 4 — validate with “ADC connected” comparisons
Always compare with and without the ADC load; the delta identifies sampling-driven failure modes.

E) Symptoms → likely root cause → corrective direction

SNR drops after connecting ADC
Sampling-correlated spikes and incomplete settling add noise-like error → increase local Cshunt and tune Riso for stability.
SFDR drops / spurs appear
Kickback-induced nonlinearity and CM→DIFF conversion under asymmetry → enforce symmetry and reduce driver disturbance with Riso/Cshunt.
Code-pattern dependence
Dynamic sampling action interacts with driver recovery → verify sampling-rate dependence and reduce kickback energy at the pins.
Rings only with ADC attached
Effective phase margin collapses under dynamic load → add/increase Riso and keep Cshunt local to the ADC pins.
Scope lock:
This section owns ADC input dynamics, kickback, and the interface toolkit. Filter order and anti-alias response design are excluded and belong to the AAF / differential filter pages.
FDA to ADC Interface: Riso, Cshunt, and Kickback Pulses Block diagram showing FDA differential outputs through Riso to ADC pins with a differential Cshunt across inputs. ADC input includes a sampling switch and sampling capacitor. A small pulse icon indicates kickback current. FDA outputs → Riso → ADC pins + Cshunt → sampling switch + Cs FDA driver VOUTP VOUTN Riso Riso Cshunt ADC INP INN SW Cs kickback AAF → other page

H2-7. Stability in the Real World: Capacitive Loads, Filter Caps, and the “Only Oscillates on My Board” Problem

Board-level oscillation is usually not “mystery instability” — it is hidden capacitance and poor damping showing up in the step response. This section provides a practical stability workflow: identify real Cload sources, stabilize in the right order, then validate with actionable step-response criteria.

A) Where capacitive load really comes from (it always adds up)

ADC input
Dynamic sampling action can look like a time-varying capacitive load and can trigger ringing.
ESD / clamp devices
Junction capacitance quietly increases Cload; stability can change after “adding protection.”
Probes / fixtures
Probe and cable capacitance can be the dominant load and can create “only fails when measured.”
Traces / connectors
Parasitics rise fast with routing length and connector structures, especially in differential paths.
Filter / “noise cap”
Output-side caps can reduce noise but also reduce phase margin; stability must close first.

B) The stability order that works (stabilize before optimizing)

  1. Isolate first (Riso): reduce the effective capacitive load seen by the driver and improve phase margin.
  2. Shape locally (Cshunt at the receiver): provide a charge reservoir and absorb fast disturbances near the ADC pins.
  3. Only then add extra caps: any “filter cap” at the output must be justified by the settling/error budget.
Rule:
Noise or filtering improvements are invalid if stability and settling fail at real load conditions.

C) Engineering phase-margin clues from step response (actionable criteria)

Overdamped
  • Minimal overshoot
  • Little to no ringing
  • Often slower settling
Underdamped
  • Moderate overshoot
  • 1–2 decaying rings
  • Settling must close the error window
Oscillating / marginal
  • Large overshoot
  • Ringing decays slowly or not at all
  • Settling window collapses

D) Why “adding a capacitor makes it worse” (the practical explanation)

Output capacitance adds a new pole and shifts phase at the frequency where loop gain is still significant. If the driver’s output impedance and the load network place poles/zeros in the wrong region, the result is reduced phase margin: more overshoot, more ringing, and sometimes self-oscillation. A stability-safe design treats every added capacitor as a loop-shaping change, verified against step response and settling constraints.

E) Symptom → likely root cause → corrective direction

Oscillates only with ADC connected
Dynamic input load reduces effective phase margin → increase Riso first, then add local Cshunt at the ADC pins.
Oscillates only when probed
Probe capacitance becomes the dominant load → switch measurement method or add isolation at the correct node.
A “small cap” increases ringing
Pole/zero placement shifts into a dangerous region → redefine the stable component range and validate by step response trends.
Ringing correlates with temperature
Output impedance and loop gain shift with temperature → add guardband and verify worst-case load and rail conditions.

F) Stability validation checklist (minimal, stability-only)

  • Compare loads: no-load vs real-load (ADC/termination/protection) and record the step response delta.
  • Trend test: increase Riso and observe ringing decrease (expected if phase margin improves).
  • Local reservoir: adjust Cshunt at receiver pins and observe spike/ringing reduction without destabilizing.
  • Pass template: no sustained oscillation; ringing decays quickly; settling closes the system error window at worst-case conditions.
Real-World Stability: Equivalent Output Load and Step-Response Shapes Diagram showing an output equivalent circuit with driver output impedance, isolation resistor, load R and C, and common capacitance sources. Three step-response mini-cards compare overdamped, underdamped, and oscillating behavior. Output equivalent + step response → fast stability diagnosis Output Equivalent Circuit FDA Rout OUT Riso Rload Cload Cshunt Cload sources ADC ESD Probe Trace Filter cap Step Response Shapes Overdamped Underdamped Oscillate

H2-8. Noise & Dynamic Range Budget: How FDA + Network + ADC Combine Into SNR/ENOB

Noise budgeting becomes usable only when every contributor is moved to the same reference point (ADC differential input) and combined by a consistent process. This section provides a spreadsheet-style merge of FDA noise, resistor noise, VOCM injection, and ADC quantization/reference noise into a single SNR/ENOB outcome — without turning into a theory chapter.

A) The budget target: one reference point, one output metric

  • Reference point: equivalent noise at the ADC differential input.
  • Combination rule: convert each source to the same units, then combine in RMS.
  • Output metric: signal amplitude vs total noise → SNR → ENOB.

B) Noise sources to include (list-only, budget ownership)

FDA
Input voltage noise (en) and input current noise (in) shaped by the source impedance and gain network.
Resistor network
Thermal noise from each resistor, converted through the same transfer function to the ADC input.
VOCM injection
VOCM node noise and impedance can enter the common-mode loop and appear as output error.
ADC
Quantization noise plus reference noise (and their in-band contributions) expressed at the input as an equivalent noise term.

C) Spreadsheet-style merge process (RMS combine, consistent bandwidth)

  1. Normalize: express each noise source at the ADC differential input using the correct gain/transfer factor.
  2. Bandwidth: use the same in-band definition for all sources (the system noise bandwidth).
  3. Convert: spectral densities → in-band Vrms (or equivalent) with a consistent method.
  4. Combine: total noise = RMS sum of all in-band Vrms contributors.
  5. Report: SNR from signal amplitude vs total noise, then map to ENOB.
Common failure mode
Adding “noise in dB” directly is invalid. Convert to linear units at the same reference point, then RMS combine.

D) Source-impedance sensitivity (high-Z inputs need a strategy)

High source impedance increases sensitivity to input-current noise and resistor thermal noise. The gain network’s absolute resistance scale matters, not only the ratio: larger resistors raise thermal noise and can amplify noise terms through impedance interactions. A robust plan uses a controlled resistance scale (still symmetric), or adds a buffer when the source is inherently high-Z.

E) Differential does not automatically “halve noise” (CM → DIFF conversion conditions)

When CM stays CM
Symmetry and adequate CMRR keep common-mode disturbances from appearing in the differential signal path.
When CM becomes DIFF error
Any asymmetry (network mismatch, unequal loading, layout imbalance, VOCM impedance differences) converts CM noise into differential error.

F) Budget closure checks (minimal, noise-budget-only)

  • Trend validation: change resistor scale or source impedance and confirm noise moves in the predicted direction.
  • FFT sanity: verify whether the noise floor and spurs match “dominant terms” in the budget.
  • CM stress test: perturb VOCM or introduce controlled asymmetry to detect CM → DIFF sensitivity.
  • Pass template: total in-band noise closes SNR/ENOB targets or clearly identifies the dominant contributor and the fix direction.
Noise Budget Tree: FDA + Network + VOCM + ADC → SNR / ENOB Tree diagram with noise source blocks for FDA en/in, resistor thermal noise, VOCM injection, ADC reference and quantization. Arrows merge into an RMS SUM node, then flow to ADC codes, SNR, and ENOB blocks. Noise sources → RMS SUM → ADC codes → SNR → ENOB Noise Sources FDA en FDA in R thermal VOCM noise ADC ref / quant RMS SUM in-band Gain BW RMS Outcome ADC codes SNR ENOB Normalize to one reference point → consistent bandwidth → RMS combine

H2-9. Linearity & Distortion: Why CMR, Swing, and Mismatch Create SFDR Spurs

When SFDR or THD looks worse on the board than in the datasheet, the cause is rarely “random.” The dominant chain is usually swing/headroom, output current stress, common-mode movement, and symmetry break that converts common-mode content into differential spurs. This section maps the sources and provides a practical diagnosis path.

A) Distortion source map (cause → path → SFDR impact)

Swing / headroom
Approaching output limits increases output-stage nonlinearity → harmonic growth → SFDR drops before “hard clipping” appears.
Output current stress
Heavy R-load or large effective capacitance forces higher dynamic current → output devices enter a more nonlinear region → spurs rise.
Common-mode movement
Input/outputs shift around VOCM → internal operating points change → distortion can vary strongly with common-mode.
Mismatch / asymmetry
Ratio/parasitic imbalance breaks differential cancellation → CM content becomes DIFF spur → even-order products lift SFDR floor.
Nonlinear loads
Sampling input behavior, clamp junctions, and connectors can reflect nonlinearity into the driver → spur pattern changes with load.

B) Even-order spurs are a symmetry alarm (CM → DIFF leakage)

In an ideal differential chain, even-order products cancel. In practice, any left/right imbalance turns common-mode content into differential error, lifting even-order spurs. Treat “high even-order” as a top-level indicator for symmetry breaks rather than a single component’s “bad linearity.”

Common symmetry breakers (top list)
  • Unequal trace length / unequal environment
  • Component mismatch (ratio + parasitics + temp drift)
  • Different return paths (plane discontinuity, via count)
  • Different loads (ESD, probe, connector, extra cap)
  • Asymmetric decoupling / supply impedance

C) Why datasheets look cleaner: light-load conditions hide stress

Datasheet distortion numbers are tied to specific load, capacitance, and layout assumptions. Real systems often add ADC sampling dynamics, protection capacitance, connectors, and higher swing/current demand. The output stage and common-mode loop then operate under different stress, and SFDR can degrade even when the waveform still “looks fine” in time domain.

D) Symptom → likely cause → corrective direction

High even-order spurs
Symmetry break / CM→DIFF conversion → check left/right load, parasitics, return paths, and ratio-matched parts.
Degrades past a certain amplitude
Headroom or output-stage nonlinearity onset → revisit swing and current budget, include temperature and guardband.
Worse only with cable/connector
Nonlinear load/parasitics change the operating point → simplify the load and reintroduce one element at a time.
Spur pattern changes with resistor swap
Mismatch and parasitics changed → use resistor arrays and mirror placement to control ratios and temp drift.
High frequency looks much worse
Current stress and parasitics dominate → reduce effective capacitance, restore symmetry, then validate settling.
Changes when probed
Measurement introduces capacitance and asymmetry → use symmetric test points and avoid single-ended probing of a differential node.

E) Measurement traps that create “fake spurs”

  • Asymmetric probing: loading only one side breaks cancellation and lifts even-order products.
  • Return-path changes: probe ground and fixture routing can inject a new return path and alter distortion.
  • Inconsistent FFT settings: comparing spurs requires identical acquisition bandwidth and processing settings.

F) Verification loop (prove symmetry vs intrinsic limitation)

  • Swap test: swap left/right loads or fixtures; if even-order spurs move, symmetry is the main lever.
  • Load isolation: simplify to a known benign load, then add ADC/ESD/connector one-by-one to locate the trigger.
  • Sweep test: sweep amplitude and frequency to find the degradation “knee,” then map it to swing/current stress.
  • Pass template: a repeatable modification reduces even-order spurs or pushes the knee outward under worst-case conditions.
Differential Symmetry Breakers: Why Even-Order Spurs Appear Diagram shows differential outputs VOUTP and VOUTN with five symmetry-breaking items near each side: trace environment, component mismatch, return path, load mismatch, and asymmetric decoupling. Arrows indicate CM to DIFF leakage that raises even-order spurs. Symmetry breaks → CM leakage → even-order spurs (SFDR) FDA OUT VOUTP VOUTN Breakers Trace env Mismatch Return path Load diff Decoupling Breakers Trace env Mismatch Return path Load diff Decoupling CM → DIFF leakage Even-order spur

H2-10. Layout & Grounding for Differential Integrity: Symmetry, Return Paths, and Probe-Proofing

Differential integrity is mostly a layout discipline: symmetry across components and routing, continuous return paths, and controlled access to sensitive nodes so measurement does not change behavior. This section converts layout guidance into a checklist that can be reviewed before bringing up hardware.

A) Differential symmetry has 3 layers (all are checkable)

Placement symmetry
Mirror critical parts (gain network, Riso, Cshunt, decoupling) so parasitics and temperature gradients match.
Route symmetry
Equal length is only the baseline; match via count, reference planes, spacing to aggressors, and impedance environment.
Return-path symmetry
Keep return paths continuous and matched. Plane splits and detours break cancellation and amplify distortion and coupling.

B) Return paths: plane continuity is part of the signal path

Differential routing still depends on the local reference. A plane split forces return current to detour, enlarging loops and creating asymmetry. Treat “crossing a slot” as a high-risk event: keep a continuous reference plane under the pair and avoid discontinuities near the driver, Riso, and the receiver input network.

C) VOCM & reference decoupling: keep control nodes quiet and local

  • VOCM routing: short, shielded by quiet reference, far from digital edges and large-swing outputs.
  • RC/buffer placement: place near the VOCM pin to avoid long impedance-sensitive runs.
  • Decoupling symmetry: match supply/ground impedance left-to-right to reduce CM→DIFF conversion.

D) Probe-proofing: mark nodes that should not be “directly touched”

High-impedance nodes
Probe capacitance shifts bias and converts CM into DIFF error. Provide an isolation option for measurement access.
Output nodes
Probes become extra Cload. Use symmetric test points and avoid probing only one side of a differential node.
VOCM / reference nodes
Measurement can inject noise and impedance variation. Keep test access controlled and local.
Design-for-measurement options
  • Symmetric test points (P/N) with identical geometry
  • Optional series resistor footprint near sensitive nodes
  • Optional buffer footprint for high-impedance or VOCM nodes

E) Digital aggressors: isolation rules (layout actions only)

  • Avoid long parallel runs between digital edges and differential outputs.
  • When crossing is required, prefer near-orthogonal crossing.
  • Keep digital return currents from flowing through the differential return region.
  • Maintain small decoupling loops and match placement left-to-right.

F) Review checklist (fast, checkable, differential-focused)

Symmetry
  • Riso and Cshunt footprints mirror placed
  • ESD/termination is left-right identical
  • Test points are symmetric (P/N)
Routing & return
  • Same reference plane and via count
  • No plane split/slot under the pair
  • Return paths are continuous and matched
VOCM & measurement
  • VOCM routing is short and isolated
  • RC/buffer options are local to the pin
  • Probe access does not add one-sided loading
Good vs Bad Layout: Symmetry, Return Paths, VOCM, and Probe-Proofing Abstract layout comparison. The GOOD side shows symmetric placement and routing with continuous return plane, short VOCM routing, and isolated digital lines. The BAD side shows plane split slot, asymmetry, long VOCM trace near digital, and probing that adds one-sided capacitance. Abstract layout review: symmetry + return paths + VOCM + probe-proof GOOD BAD RETURN Riso Riso Cshunt Cshunt SYM VOCM DIGI SLOT Riso Riso Cshunt ESD DIGI VOCM Probe

Verification & Engineering Checklist: Bring-Up, Bench Tests, and Pass/Fail Criteria

This section turns the FDA SE↔Differential converter into a repeatable validation flow: a minimal test set, condition-aligned measurements, and a pass/fail template that can be copied into bring-up notes or production test plans.

A) Bring-up (power-on & static): verify the system can “stand”

VOCM correctness
  • Check: VOCM node voltage and source impedance behavior (load it lightly and observe droop).
  • Why: VOCM noise/impedance injects directly through the common-mode loop into the outputs.
  • Fail hint: output CM error tracks VOCM ripple, or CM shifts when probing VOCM.
Output common-mode & balance
  • Check: (VOUTP + VOUTN)/2 vs VOCM, plus output symmetry under a small sine.
  • Why: CM mismatch often becomes even-order distortion and SFDR spur growth.
  • Fail hint: one side clips earlier, or even-order spurs rise when swapping probes between sides.
Quiescent current & rail headroom
  • Check: Iq at steady state, and DC output distance to rails (both outputs).
  • Why: unexpected Iq often indicates oscillation, heavy capacitive load, or biasing errors.
  • Fail hint: Iq jumps when connecting the ADC/EVM, or output DC point drifts toward a rail.

B) Dynamic bench (minimal set): stability & distortion with aligned conditions

Step response (phase margin proxy)
  • Condition: define load model (R||C), probe type, and output amplitude.
  • Pass: overshoot < X%, ringing cycles ≤ N, settle-to-error < T.
  • Fail signature: “only oscillates on my board” appears when ADC is attached or when probing.
Full-scale THD / single-tone SFDR
  • Condition: specify Vdiff_pp, VOCM, frequency, and load (include Cshunt if used).
  • Pass: THD/SFDR ≥ target with the required swing and drive current.
  • Fail signature: even-order harmonics grow when symmetry breaks (layout, mismatch, load imbalance).
Frequency sweep (find spur “knees”)
  • Condition: sweep Fin across the intended band while keeping amplitude constant.
  • Pass: SFDR stays above target across band under defined load.
  • Fail signature: spurs jump at certain Fin → usually a coupling/mismatch/settling boundary.

C) With-ADC integration: a small matrix to expose kickback & settling limits

Use a tiny test matrix (e.g., 2 sampling rates × 3 input tones) to force worst-case sampling transients and confirm the interface network (Riso/Cshunt) meets the error budget.

Kickback-driven failure cues
  • Code-dependent spurs increase (spur level changes strongly with sampling rate or tone placement).
  • SNR/SFDR becomes overly sensitive to small Riso or Cshunt changes (interface-dominated behavior).
  • Output shows sampling-synchronous ripple or spikes that scale with Fs.

D) Pass/Fail template (copyable)

Template fields
  • Metric: SNR / SFDR / THD / Overshoot / Settling
  • Condition: VDD, VOCM, Vdiff_pp, Load (R||C), Fs, Fin, Temperature
  • Method: instrument + bandwidth + sample length
  • Pass: threshold + “symptom disappears” statement
  • Fail signature: what failure looks like
  • Next action: point back to the right section (VOCM, headroom, ADC kickback, stability, layout)
Example wording pattern
SFDR @ Fin = …
Condition: VDD = …, VOCM = …, Vdiff_pp = …, Load = R||C, Fs = …, T = …
Pass: SFDR ≥ … and spurs do not change after swapping probes between VOUTP/VOUTN.
Fail: even-order spurs rise > … dB when one side is probed → likely symmetry/load imbalance.

Reference examples (MPNs; starting points only)

Part numbers below speed up datasheet/EVM lookup and lab replication. Values and topology must be tuned to the target ADC, sampling behavior, and error budget.

  • FDA examples: TI THS4551; TI THS4561; ADI ADA4940-1; ADI ADA4945-1
  • ADC examples: TI ADS8900B (ordering example: ADS8900BRGER); ADI AD7982 (ordering example: AD7982BRMZ)
  • ADC evaluation helpers: TI PSIEVM (Precision Signal Injector EVM for ADC testing); ADI ADA4945-1CP-EBZ; ADI AMC-ADA4945-1EBZ (mezzanine)
  • Matched gain network (example resistor array): Panasonic EXB-38V103JV (10 kΩ ×4)
  • Riso (example thin-film resistor): Vishay TNPW040210R0FHTD (10 Ω, 0402)
  • Cshunt (example C0G/NPO): Murata GRM1555C1H100JA01J (10 pF, 0402)
  • Decoupling (example X7R): Murata GRM155R71H104KE14D (0.1 µF, 50 V, 0402)
  • Reference example: TI REF6050 (commonly used as a low-noise reference in precision DAQ chains)
FDA verification test fixture and checklist diagram A block diagram from signal source through FDA and ADC/EVM to FFT analyzer, with a checklist of bring-up and bench tests. Minimal bench flow: Source → FDA → ADC/EVM → FFT + Pass/Fail template SOURCE ATTEN / RC optional FDA BOARD VOCM + diff drive VOUTP VOUTN ADC / EVM Riso + Cshunt FFT / ANALYZER Checklist (minimal) VOCM (level + impedance) Iq + rail headroom Step response (overshoot/ringing/settle) THD @ full swing SFDR sweep (find spur knees) With-ADC matrix (Fs × Fin) Pass/Fail must include: Metric + Condition + Symptom disappears.
Test fixture block diagram and a minimal checklist for bring-up + dynamic validation.

Applications (Placed Near the End): Typical Chains and What Each Block Owns

Use these chains to map the FDA’s role quickly. Each chain states ownership boundaries: this page covers only the SE↔Differential conversion, VOCM control, and differential drive segment.

Chain 1) Precision SAR DAQ ADC driver (most common)

  • FDA owns: Vdiff amplitude, VOCM alignment, settling under Riso/Cshunt + sampling kickback.
  • ADC owns: sampling behavior (kickback), reference/quantization limits, digital readout integrity.
  • Interface owns: Riso/Cshunt trade-off between stability and settling error.
Example BOM (MPNs)
  • FDA: TI THS4551
  • ADC: TI ADS8900B (ordering example: ADS8900BRGER)
  • Riso: Vishay TNPW040210R0FHTD (10 Ω, 0402)
  • Cshunt: Murata GRM1555C1H100JA01J (10 pF, C0G, 0402)
  • Matched network (example): Panasonic EXB-38V103JV (10 kΩ ×4)

Chain 2) Wide-swing differential input (maximize dynamic range)

  • FDA owns: headroom budget, output current drive, distortion under large Vdiff swing.
  • System owns: guardband across temperature and tolerance (avoid rail-limited SFDR collapse).
Example BOM (MPNs)
  • FDA: TI THS4561
  • ADC: TI ADS8900B (ordering example: ADS8900BRGER)
  • Reference: TI REF6050
  • Decoupling (example): Murata GRM155R71H104KE14D (0.1 µF, 50 V, 0402)

Chain 3) Low-power differential drive for SAR / Σ-Δ class ADCs

  • FDA owns: VOCM level shifting, balanced outputs, low distortion with modest bandwidth.
  • Layout owns: symmetry (mismatch shows up as even-order distortion and SFDR spurs).
Example BOM (MPNs)
  • FDA: ADI ADA4940-1
  • ADC: ADI AD7982 (ordering example: AD7982BRMZ)
  • Matched network (example): Panasonic EXB-38V103JV (10 kΩ ×4)
  • Riso: Vishay TNPW040210R0FHTD (10 Ω, 0402)
  • Cshunt: Murata GRM1555C1H100JA01J (10 pF, C0G, 0402)
Three typical application chains using an FDA SE-to-differential converter Three stacked block-diagram chains. The FDA block is highlighted in blue in each chain. Application chains (FDA block highlighted): own the conversion + VOCM + differential drive Chain 1: SE sensor → FDA → ADC (Riso/Cshunt) SENSOR RC FDA VOCM set Riso Cshunt ADC Chain 2: SE → FDA → diff cable/isolator → receiver/ADC SOURCE FDA drive diff link CABLE / ISO RECEIVER / ADC Chain 3: Sensor → PGA → FDA → ADC / diff interface SENSOR PGA range FDA SE↔DIFF ADC DIFF LINK
Three common chains. The highlighted FDA block defines Vdiff + VOCM and must remain stable under the real ADC/link load.

Request a Quote

Accepted Formats

pdf, csv, xls, xlsx, zip

Attachment

Drag & drop files here or use the button below.

FAQs

Troubleshooting only (no new theory). Each answer uses the same 4-line, measurable format: Likely cause / Quick check / Fix / Pass criteria.

Why is VOCM correct at DC but my FFT shows big even-order spurs?
Likely cause: Common-mode → differential conversion from asymmetry (ratio mismatch, unequal load, unequal return path), lifting even-order terms.
Quick check: Swap probes between VOUTP/VOUTN; swap left/right load parts; compare even-order spur change and CM ripple ((VOUTP+VOUTN)/2).
Fix: Enforce symmetry (matched resistor array e.g., Panasonic EXB-38V103JV; equal loading; mirrored routing/return); reduce VOCM impedance (buffer or RC filter close to VOCM pin).
Pass criteria: Even-order spurs change ≤ 2 dB after probe/load swap; CM error ≤ 5 mV (or within system budget) under the defined Vdiff_pp, Fin, Fs, and load.
Why does it look stable into a resistor load but ring badly with the ADC connected?
Likely cause: ADC sampling network adds dynamic kickback + effective capacitance, collapsing phase margin compared with a pure resistor load.
Quick check: Compare step response with ADC disconnected vs connected; change Fs (ringing that tracks Fs strongly points to sampling interaction).
Fix: Add/tune interface: start Riso = 5–20 Ω (e.g., Vishay TNPW040210R0FHTD 10 Ω) then add small Cshunt = 5–33 pF C0G (e.g., Murata GRM1555C1H100JA01J 10 pF); keep the loop compact and symmetric.
Pass criteria: Overshoot ≤ 10%, ringing cycles ≤ 2, and settle-to-error ≤ 0.25–0.5 LSB (or ≤ X%FS) within the required time window for the target Fs/Fin/load.
Why does adding a small Cshunt improve SFDR but worsen settling time?
Likely cause: Cshunt filters high-frequency kickback/edge energy (spur drops) but adds a pole with Riso/output impedance (settling tail grows).
Quick check: Sweep Cshunt (e.g., 5/10/22/33 pF) and record (a) worst spur, (b) settling-to-error at the sampling instant, and (c) step ringing.
Fix: Reduce Cshunt to the minimum that suppresses the spur; co-tune with Riso; if needed split filtering (smaller Cshunt + mild input RC) instead of one large shunt cap.
Pass criteria: SFDR improves ≥ 10 dB (or meets target) while settling-to-error remains ≤ 0.25–0.5 LSB (or ≤ X%FS) for the defined Fs/Fin/load.
Why does changing gain change the allowed input/common-mode range?
Likely cause: Gain changes the required output swing/current and the CM mapping, shrinking headroom and shifting the safe input/CM region.
Quick check: Compute per-side peaks: VOUTP/VOUTN = VOCM ± Vdiff/2; measure minimum distance to rails at max signal and compare across gain settings.
Fix: Re-center VOCM, reduce target Vdiff_pp or gain, increase supply headroom, and keep ratio matching tight (use arrays to control mismatch-driven CM→diff errors).
Pass criteria: Minimum rail margin ≥ the chosen guardband (e.g., ≥ 200–300 mV or per datasheet), and THD/SFDR remain stable (Δ ≤ 3 dB) across intended gains/temps.
Why does my output clip near a rail even though the amplitude seems within range?
Likely cause: The “range” check used Vdiff only and ignored per-side swing, VOCM offset, load current, and temperature/part guardbands.
Quick check: Scope VOUTP and VOUTN separately; record peak-to-rail margins and output current (approx Iout ≈ Vout/Rload for resistive loads).
Fix: Shift VOCM toward mid-supply, reduce swing, lighten the load (or add Riso), and include temperature + tolerance guardbands in the headroom budget.
Pass criteria: No flat-topping; harmonic growth with a small amplitude increase is ≤ 3 dB; minimum peak-to-rail margin ≥ the selected guardband across the target temperature range.
Why does my measured noise increase when I reduce resistor values?
Likely cause: Thermal noise fell, but total integrated noise rose due to wider effective bandwidth, higher drive current/noise dominance, or VOCM/reference injection sensitivity changes.
Quick check: Compare noise using the same measurement bandwidth; check if the noise shape indicates bandwidth expansion (more HF noise) or CM injection (tracks VOCM noise).
Fix: Hold the intended RC corner constant when changing resistor values; keep the network in the FDA’s “comfortable” load region; reduce VOCM impedance/noise if CM injection is suspected.
Pass criteria: Integrated RMS noise (in the specified bandwidth) ≤ budget, and noise changes match predictable scaling with bandwidth (not large jumps from probing or VOCM handling).
Why do I see code-dependent “glitches” that disappear when I probe differently?
Likely cause: Measurement loading (probe C + ground loop) or ADC sampling kickback coupling creates sampling-synchronous artifacts that look “code dependent.”
Quick check: Use short ground spring or a differential probe; vary Fs (kickback artifacts often track Fs); disconnect ADC and compare whether the glitch remains.
Fix: Make nodes probe-proof: add small series resistors at test points (e.g., 20–49 Ω per side), provide symmetric probing pads, and keep return paths tight/continuous.
Pass criteria: Glitch peak amplitude varies ≤ ±10% across approved probing methods, and FFT metrics (SNR/SFDR) change ≤ 1–2 dB under the same conditions.
How do I choose Riso without sacrificing bandwidth or distortion?
Likely cause: Riso is a three-way trade: too small → ringing/instability; too large → settling tail and potential large-signal distortion under heavy drive.
Quick check: Sweep Riso (e.g., 5/10/15/20 Ω) and log step ringing, settling-to-error, and SFDR/THD; pick the first value that stops ringing without long tails.
Fix: Start near 10 Ω thin-film (e.g., TNPW040210R0FHTD) then tune Cshunt (5–33 pF C0G); keep traces short and symmetrical to reduce required Riso.
Pass criteria: Ringing ≤ threshold (e.g., ≤ 2 cycles), settle-to-error ≤ 0.25–0.5 LSB (or ≤ X%FS), and SFDR/THD meet target while bandwidth remains ≥ requirement.
Why does the circuit pass at room temp but fail at hot/cold?
Likely cause: Temperature shifts headroom, bias/drive, resistor ratios, and VOCM source behavior; a small asymmetry becomes large spur/clip at extremes.
Quick check: At hot/cold repeat: minimum rail margin, Iq, CM error, even-order spur level; identify which metric “breaks first.”
Fix: Add guardband (e.g., ≥ 20–30% margin on headroom/settling), use matched low-tempco ratio parts (arrays), stabilize VOCM (buffer/RC), and keep C0G for small caps that set dynamics.
Pass criteria: Key metrics remain in-family across temperature: CM shift ≤ 5 mV, SFDR/THD drift ≤ 3 dB (or within budget), and no rail clipping at max signal.
Why does VOCM noise show up as differential noise?
Likely cause: VOCM noise is common-mode, but any imbalance (ratio, routing, loading, return) converts it into differential noise seen by the ADC.
Quick check: Measure CM noise ((VOUTP+VOUTN)/2) vs diff noise (VOUTP−VOUTN); inject a small known tone on VOCM and see if it appears in the differential spectrum.
Fix: Improve symmetry (matched arrays, mirrored placement/return paths), reduce VOCM impedance (buffer) and filter VOCM locally (small RC close to the VOCM pin).
Pass criteria: Differential noise increase from VOCM handling is ≤ 10% RMS (in the specified bandwidth), and injected VOCM tone-to-diff transfer meets the system limit (e.g., ≤ −60 dB).
What’s the quickest bench test to distinguish instability vs ADC kickback?
Likely cause: Both look like ringing/spikes, but instability is load/probing dominated; kickback is sampling (Fs) dominated.
Quick check: (1) Remove ADC and replace with R||C dummy load → if ringing remains, suspect stability. (2) Reconnect ADC and vary Fs → if artifacts track Fs strongly, suspect kickback.
Fix: Instability → tune Riso/Cshunt and tighten layout symmetry/return paths; kickback → co-tune interface network and confirm with a small Fs×Fin matrix.
Pass criteria: Classification is consistent across repeats (same trigger, same signature), and the chosen fix removes the symptom under the defined Fs/Fin/load conditions.
When should I buffer VOCM instead of feeding it directly?
Likely cause: VOCM source impedance is too high, shared across channels, too noisy, or too sensitive to probing/trace coupling—so CM loop becomes error-injection.
Quick check: Lightly load VOCM (small resistor step) and observe droop; probe VOCM and watch output CM shift; compare even-order spur level with/without VOCM RC isolation.
Fix: Buffer VOCM with a unity-gain-stable, low-noise op-amp placed close to the VOCM pin; keep VOCM routing short, isolated from digital, and decouple locally (do not share long runs).
Pass criteria: VOCM changes ≤ 1 mV with allowed loading/probing, output CM shift ≤ 2–5 mV, and even-order spur level is stable (Δ ≤ 2 dB) across approved test setups.
icnavigator

ICNavigator helps engineers find verified ICs, alternatives, and fast quotes.

Explore
Categories
  • Power Management
  • MCU
  • Automotive ICs
  • Sensors
  • Interface & Transceivers
  • Analog Front-End
Get in Touch
  • Email: hello@icnavigator.com
  • WeChat/WhatsApp: +86-xxxx

© 2025 ICNavigator. All rights reserved.