fc is largely set by the RC time-constant scale. Choose capacitor families (C0G/NP0) and a practical R magnitude first.

Q is mainly controlled by feedback ratios. Adjusting ratios is typically easier than forcing extreme absolute values.

Set by the stage’s effective RC scale. In measurement, it anchors the magnitude/phase transition region.

Controls corner peaking and step-response ringing. Higher Q increases tolerance and phase-delay sensitivity.

The intended passband gain magnitude used in budgets. Keep sign/phase separate from gain magnitude.

• GBW and phase margin at/above the corner (Q magnifies phase delay errors).
• Slew rate and output settling at the target swing and frequency.

• Input noise (en/in) vs the resistor magnitude window.
• Input bias current and drift vs expected offsets when biased at Vref.

• THD at the target frequency, swing, and load (not a convenient datasheet condition).
• Output drive and headroom on the chosen supply and Vref.

• AC magnitude/phase (read ω0/Q behavior).
• Noise (in-band integrated noise tied to the budget).
• Transient (step overshoot/settling reveals Q errors).
• Monte-Carlo (fc/Q distribution for production viability).

• Magnitude/phase vs frequency (corner shape + phase slope).
• Step response (overshoot + settling time).
• THD/IMD at target frequency and swing under real load.
• Noise measurement with defined bandwidth integration.

• Corner: fc within ±X% and peaking within ±Y dB.
• Time domain: overshoot < Z% and settling < T ms.
• Distortion: THD < A dB at ftest and Vout swing.
• Noise: in-band RMS < N (defined BW and weighting).

fc mostly follows RC scale, while Q mostly follows ratios. Ratio drift shows up as corner peaking changes and longer settling.

In high-Q designs, small capacitance at the inverting node and asymmetry in routing can shift Q and peak gain even when nominal values are correct.

Different materials, packages, and placement create mismatch in drift. The result is Q and peaking dispersion across units and temperature.

• Use C0G/NP0 where corner stability is required.
• Prefer consistent dielectric and package for matched pairs.
• Keep inverting-node capacitance low and predictable.

• Use resistor networks for ratio-critical parts when possible.
• Use thin-film/precision resistors for key ratio legs.
• Spend tolerance budget on ratio-critical components, not on every part.

• Place ratio parts close together to share the same thermal environment.
• Route the inverting-node network compactly; avoid long stubs and layer changes.
• Keep sensitive nodes away from switching edges and guard with a quiet reference plane.

Track shift direction and 3σ range; confirm the corner remains inside the allocated budget window.

Inspect whether Q is skewed and whether tails create excessive peaking or slow settling in a small fraction of units.

Track peak gain and the phase-transition region. These reveal ratio sensitivity and parasitic-driven instability risk.

When the system allows, reduce Q or split gain so the distribution stays inside peaking and settling budgets under tolerance and temperature.

Use matched networks and thermal co-location to shrink random ratio spread. This usually beats pushing every part to the tightest tolerance.

Provide a trim point (digital pot / resistor strap / stored coefficients) so production can re-center peaking and corner location without over-costing passive components.

Current noise and bias/leakage conversion become more visible; drift and low-frequency terms can dominate.

Output drive and distortion often become the limiter; noise may drop but linearity can degrade under load.

Near headroom boundaries, compression and odd-order rise can appear first around the corner and under capacitive loads.

Nonlinear output stages interacting with capacitive paths can produce corner-linked distortion and unexpected peaking.

THD must be verified at the target frequency, swing, and load. “Great typical THD” under light load is not transferable.

Every resistor produces noise; the MFB topology weights each resistor differently through the noise-gain path.

en injects at the input pair and is shaped by the stage noise gain and the frequency response around the corner region.

in converts through the inverting-node effective impedance. Larger resistor magnitudes make in and bias/leakage more visible.

In single-supply biasing, Vref integrity behaves like a signal input. Poor reference filtering can dominate low-frequency output noise.

• in and bias/leakage conversion rise at the inverting node.
• Reference/bias noise coupling becomes easier to notice.
• Low-frequency noise terms become harder to average away.

• Resistor thermal noise can drop, but output-drive stress can increase.
• Linearity and stability under load may become the limiter.
• en can become the main term when in conversion is reduced.

A single frequency point can look great while total integrated noise increases due to wider bandwidth or corner peaking.

Integrate the measured spectrum across the target bandwidth. Use consistent RBW, windowing, and averaging settings.

Lower impedance reduces in conversion and resistor noise weighting, but verify output drive, distortion, and load stability.

Smaller R often favors low en; larger R makes in and bias terms more important. Verify noise under the real corner conditions.

Excess gain or high Q increases corner weighting and can raise in-band noise even when spot noise looks unchanged.

Filter, decouple, and route Vref/Vbias to avoid injecting low-frequency noise into the MFB output.

As the output approaches headroom limits, compression and odd-order products rise rapidly, often first near the corner region.

Low resistive loads increase output current demand; THD can worsen sharply with amplitude even if small-signal AC looks perfect.

ADC inputs, long cables, and input capacitances reduce phase margin. The result can be corner-linked peaking and distortion bumps.

Measure across frequency and amplitude, focusing on the corner and the peaking region where risk concentrates.

Use two tones that stress the corner region; inspect intermod products for load-driven nonlinearity.

Repeat with the actual load (ADC input, cable, or specified R||C). Small-signal lab conditions are not transferable.

The fastest lever: reduce peak-region swing demand and keep the stage inside its linear envelope.

Isolation often stabilizes the load interface and reduces distortion bumps triggered by phase-margin loss.

Screen parts using the intended swing, frequency, and load; avoid relying on “typical THD” under light-load conditions.

Set amplitude limits and validation around the peaking region to prevent late-stage THD surprises.

• Peaking height/position changes with source or series resistance.
• Step overshoot changes even when the PCB stays the same.
• Corner-region phase behavior shifts unexpectedly.

• Model source-Z as a window (min/max) in simulation.
• Validate peaking and step response across that window.
• Use a controlled series element only when needed, and verify its side effects on noise/distortion elsewhere.

• Downstream behaves like R||C (ADC, cable, clamp network).
• Response changes with probe type or cable length.
• Ringing frequency is stable and repeats across boards.

• Add Riso near the output pin and sweep its value as an A/B diagnostic.
• Use a buffer stage when load variation is unavoidable.
• Re-check peaking and step response in the real load corner case.

Sensitive-node capacitance adds an extra pole/zero interaction near the corner and can increase peaking.

Output capacitance reduces phase margin and can create sustained ringing or intermittent oscillation.

Ltrace with capacitive nodes forms a resonant bump that shows up as a narrowband peak and repeatable ringing frequency.

Shared return paths convert output currents into a reference shift, effectively injecting phase error into the loop.

Large change in ringing/peaking points to load-C coupling and phase-margin loss at the output interface.

Peaking height/position changes point to source-Z coupling into the inverting-node effective impedance.

A visible response change indicates measurement injection or ground impedance coupling through the return path.

Peak height, ringing frequency, and settling time constant under each A/B condition.

• Keep the inverting node short with minimal copper area and minimal vias.
• Minimize feedback loop area; place R/C elements tightly around the op-amp pins.
• Use guard/keepout around high-impedance nodes to reduce Cin and leakage pickup.

• Maintain continuous return paths; avoid crossing splits for the output current return.
• Separate high-current loops from sensitive references; prevent Zgnd injection into the loop.
• Place decoupling close; keep current loops compact and predictable.

• Match trace environments for repeatability across channels.
• Place critical parts with consistent orientation and proximity to reduce drift mismatch.
• Control routing inductance for output and feedback paths.

Detects peaking shifts and phase anomalies caused by source/load interaction and parasitics.

Reveals ringing frequency, overshoot, and settling behavior tied to phase-margin loss and resonances.

Validates integrated noise across the intended bandwidth and catches Vref injection and impedance-window sensitivity.

Captures load-driven distortion bumps near the corner/peaking region that do not appear in small-signal AC checks.

• Peaking < X ; overshoot < Y% ; settle < T
• In-band noise < N ; THD < D across band (including peak region)

• Vin, Vout, Vref (bias), and a clean reference ground point.
• Optional: Riso option pads to select isolation window in production.

• Bypass the downstream load for isolation diagnosis.
• Loopback fixtures to reproduce AC/step behavior consistently.

• Digipot or resistor options for gain/threshold tuning.
• EEPROM parameter slot to track calibration revision and guardband windows.

• Peaking > X → bin “peaking”
• Ringing / oscillation beyond T → bin “stability”
• THD bump > Y in peak region → bin “linearity”
• In-band noise > N → bin “noise”

• Low-noise / low-THD (dual): TI OPA1612AIDR, TI OPA1602AIDR, TI OPA1678IDR
• FET/JFET input (good when resistor values are higher): TI OPA1652IDR (dual), TI OPA1656IDR (single), TI OPA1642AIDR (dual)
• High-speed / wideband option: ADI ADA4898-2YRDZ-R7 (dual; check supplies & headroom policy)
• Precision (DC/low-frequency measurement): TI OPA189IDR (single; validate distortion if used in audio band)
• Reference-grade “general precision”: ADI ADA4077-2ARZ-R7 (dual; confirm bandwidth/Q feasibility)

• Vishay Dale 0805 0.1%: TNPW080510K0BEEA (example value 10 kΩ; match values per design)
• SUSUMU 0805 0.1%: RG2012P-103-B-T5 (10 kΩ; stable ratio networks for Q control)

• Murata C0G 0603 1 nF 50 V 1%: GRM1885C1H102FA01D
• Murata C0G 0603 10 nF 50 V 5%: GRM1885C1H103JA01D
• TDK C0G 0603 10 nF 50 V 5%: CGA3E2C0G1H103J080AA