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Sallen-Key Low-Pass / High-Pass Filters (LP/HP)

Sallen-Key Low-Pass / High-Pass Filters (LP/HP)

← Back to:Active Filters & Signal Conditioning

Sallen-Key LP/HP is the simplest 2nd-order active filter for anti-alias and denoise front-ends, but its real success depends on op-amp stability (GBW/phase margin) and tight R/C ratios that keep Q under control.

This page shows how to choose the right variant, synthesize practical R/C values, verify stability with real loads (especially ADC kickback), and lock performance with tolerance, layout, and measurable pass/fail criteria.

H2-1. Definition & Positioning (What Sallen-Key is, where it fits)

A) One-line definition + where it sits in the chain

Sallen-Key LP/HP is a 2nd-order VCVS (voltage-controlled voltage source) active filter that uses an op-amp buffer plus an RC feedback network to realize low-pass or high-pass shaping with a low part count.

Typical fit: Anti-alias front
Place a 2nd-order LP/HP in front of an ADC to trim out-of-band content and reduce alias risk. Key checks: ADC sampling kickback, settling budget, and op-amp stability under the effective load.
Typical fit: Denoise / bandwidth shaping
Reduce in-band noise by narrowing analog bandwidth before digitization. Key checks: Q-peaking headroom, integrated noise vs. source impedance, and distortion under the target swing.
Typical fit: Low/medium-Q shaping
Use when a clean 2nd-order corner with modest peaking is sufficient. If a sharp transition, strict group delay, or deep notch is required, move to higher-order or multi-loop topologies (handled on sibling pages).
The “simple but costly” tradeoff
  • Q is tolerance-sensitive: small R/C ratio or parasitic changes can shift peaking and phase.
  • Op-amp GBW & phase margin matter: insufficient loop gain/phase creates extra peaking, ringing, or instability.
  • Load interaction matters: capacitive loads and ADC kickback can break “bench-perfect” behavior.

B) Three common failure modes (what they look like in hardware)

1) “GBW is not enough”
Symptoms: unexpected passband peaking, step overshoot/ringing, phase response that differs from ideal. Quick check: the behavior improves materially with a higher-GBW/stronger-PM op-amp, or with reduced Q/closed-loop gain.
2) “Q drifts across units/temperature”
Symptoms: fc and peaking vary between boards or after reflow; temperature shifts move the peaking more than expected. Quick check: Monte-Carlo and measured sweep disagree mainly around the peak (not a flat gain error).
3) “Looks fine no-load, fails with ADC attached”
Symptoms: oscillation, worse SFDR, slower settling, or transient spikes correlated with sampling. Quick check: adding a small isolation resistor (Riso) or buffering reduces ringing and stabilizes the response.
Figure 1 — Signal-chain placement and the three interface points
Sallen-Key LP/HP placement in an ADC front-end Block diagram showing source, Sallen-Key LP/HP filter, and ADC/driver with callouts for source impedance, op-amp GBW/phase margin, and ADC kickback load interaction. Source Source-Z Sallen-Key LP/HP Op-Amp + RC ADC / Driver Kickback Interface 1: Source impedance Shifts fc/Q and noise budget. Interface 2: Op-amp GBW & PM Sets stability, peaking, settling. Interface 3: Load / ADC kickback Can trigger ringing or oscillation.
Use this placement view to keep scope tight: the design outcome is dominated by source-Z, op-amp loop behavior, and ADC/load interaction.

H2-2. When to Choose Sallen-Key (Decision boundaries)

A) Use-cases where Sallen-Key is a strong fit

Anti-alias pre-filter (2nd order is sufficient)
Choose Sallen-Key when a clean 2nd-order corner provides enough attenuation margin before sampling. Minimum checks: ADC kickback stability and time-domain settling within the acquisition window.
Denoise / bandwidth trimming ahead of ADC
Use it to reduce integrated noise by shaping bandwidth in analog. Minimum checks: Q-peaking headroom, op-amp noise vs. source impedance, and distortion under the expected swing.
Simple HP for DC removal (with well-defined biasing)
Apply HP shaping to remove slow drift while preserving the passband. Minimum checks: bias paths, leakage/bias current induced offsets, and recovery after large common-mode or step events.
Low/medium-Q shaping (manufacturable targets)
Use when tolerance-driven Q variation is acceptable or can be constrained with matching parts. Minimum checks: Monte-Carlo spread around the peak and temperature drift relative to system margin.

B) Red flags (stop conditions)

  • High Q, deep notch, or tight unit-to-unit consistency is required → Sallen-Key sensitivity becomes a yield risk.
  • 4th/6th order roll-off or strict magnitude/phase targets are required → a higher-order realization is needed.
  • Heavy capacitive load or aggressive ADC kickback is unavoidable without buffering → instability/settling failures become likely.
  • Single-supply near-rail swing with low distortion is mandatory → output headroom/drive limitations dominate THD/SFDR.
Practical interpretation
If the risk comes from Q control or order/phase needs, switch topology; if the risk comes from load interaction, fix the interface (buffer/isolation) before blaming the filter math.

C) Link-outs (go deeper without expanding this page)

Figure 2 — Decision tree: choose Sallen-Key vs. alternatives
Decision tree for selecting Sallen-Key LP/HP Flowchart that routes design goals by required order, Q requirement, and load interaction to Sallen-Key, MFB, cascaded biquads, or state-variable/notch solutions. What is the goal? Anti-alias (AA) Denoise / shaping HP for DC removal Is 2nd order enough? Sallen-Key candidate Use biquads Need high Q? Sallen-Key Prefer MFB Heavy load / ADC kickback → fix interface first
The selection outcome is driven by three questions: order, Q/consistency, and load interaction. Keep the rest of the page focused on making those risks measurable.

H2-3. Topology Variants (LP/HP, unity/non-unity gain, biasing)

Goal of this section

Lock down the valid LP/HP variants, how gain K changes risk (Q sensitivity and stability margin), and the single-supply biasing rules that prevent baseline drift and “stuck at rail” behavior. Higher-order synthesis and non-Sallen-Key topologies are intentionally excluded here.

A) LP variants (same 2nd-order core, different usage constraints)

Unity-gain LP (K = 1)
  • Best fit: simple anti-alias / denoise corners with low part count.
  • What fc/Q “mean”: fc set mainly by RC magnitudes; Q strongly affected by RC ratios and parasitics near the op-amp pins.
  • Primary risk: op-amp loop margin and output drive under the real load (including ADC kickback).
Gain-of-K LP (K > 1)
  • Best fit: when the filter also needs to set chain gain (range matching into the ADC).
  • How K changes risk: higher K typically increases noise-gain and can reduce stability margin; Q and peaking become more sensitive to op-amp non-idealities.
  • Minimum checks: step overshoot/ringing, load stability with worst-case capacitance, and distortion under target swing.
LP with explicit interface elements (Riso / small damping)
  • Best fit: when the load is not “benign” (ADC input network, cables, or capacitive loads).
  • Why it exists: isolates the op-amp from charge injection and reduces ringing without changing the intended 2nd-order poles.
  • Pass check: sampling-correlated output spikes shrink and settling meets the acquisition window.

B) HP variants (DC paths and recovery dominate real behavior)

DC path rule (non-negotiable)
Every op-amp input must have a defined DC return path. Missing bias paths can look “fine” in ideal simulations but drift to a rail in hardware.
AC-coupled HP with bias network
  • Key trade: bias resistor values set leakage/bias-current error, noise, and recovery time after steps.
  • Common symptom: slow baseline return after a large step or common-mode event.
  • Fast check: change bias network magnitude (1 decade) and observe baseline and low-frequency gain shift.
HP in single-supply systems
  • Bias point selection: choose mid-supply or a defined VOCM so the signal swing stays inside input/output headroom.
  • Leakage sensitivity: board contamination and high-value resistors can dominate low-frequency error.
  • Pass check: no rail sticking, predictable recovery time, and stable low-frequency magnitude across temperature/humidity.

C) Single-supply biasing: three hard rules

  1. Define DC return paths for both op-amp inputs (bias resistors, reference node, or intentional paths).
  2. Use a low-impedance bias reference (virtual ground/VOCM) so the common-mode does not move with signal or load.
  3. Verify headroom under worst-case peaking (Q and gain can increase peak amplitude and trigger clipping early).
Practical outcome
Most “mysterious” Sallen-Key failures are not topology mistakes—they are missing DC paths, insufficient loop margin under real loads, or headroom loss from peaking.
Figure 3 — Three canonical block variants (LP, HP, Gain K)
Sallen-Key LP/HP variants and bias path Three-column block diagram showing LP, HP with bias path, and gain-of-K variants using op-amp and RC blocks, highlighting DC loop and interface points. LP (K = 1) HP + Bias LP (Gain K) Vin R/C Op-Amp Vout 2nd-order core Vin C/R Op-Amp Vout Bias path Vin R/C Op-Amp Gain K Vout Keep DC loops and load interaction explicit
The LP and HP blocks share a 2nd-order core; the real differences come from DC paths, gain K, and load stability.

H2-4. Design Targets & Specs Mapping (fc/Q vs system goals)

Why mapping matters

Filter parameters (fc, Q, gain, headroom) must be chosen from system acceptance criteria (alias risk, settling window, phase/latency, in-band noise, and baseline behavior). A 2nd-order Sallen-Key can meet many front-end needs, but it cannot replace higher-order magnitude/phase targets.

A) Anti-alias front-end: map alias/settling/phase to fc and Q

Alias margin
fc sets how much out-of-band content leaks into the sampler. With only 2nd-order roll-off, alias margin is often dominated by the first out-of-band region rather than “far away” frequencies.
Settling window
Q affects step overshoot and ring-down. Even if the frequency response “looks right”, excessive ringing can violate the ADC acquisition window and degrade effective resolution.
Phase / latency
Lower fc or higher Q can increase group-delay variation around the corner. If latency/phase linearity is a hard requirement, a different filter family may be needed (handled on the cascaded-biquads / all-pass pages).

B) Denoise front-end: map source-Z + bandwidth to in-band noise and headroom

In-band noise
Bandwidth reduction lowers integrated noise, but the real benefit depends on source impedance and op-amp noise. High source-Z can shift the dominant term, limiting the achievable improvement.
Headroom under peaking
Q-peaking increases peak amplitude near the corner. If headroom is tight (single-supply, near-rail), clipping can occur even when the “nominal” gain is within range.
Step response
Time-domain behavior is the fastest sanity check: overshoot and ring-down reveal whether Q and op-amp loop margin align with the measurement window and the ADC’s acquisition dynamics.

C) Quick worksheet (inputs that prevent “fc/Q by guess”)

  • Sampling rate (fs) and usable signal bandwidth (BW).
  • Settling window (acquisition time) and allowed overshoot/ring-down behavior.
  • Latency / phase tolerance around the corner (if applicable).
  • Noise target (in-band RMS) and distortion target (THD/SFDR under target swing).
  • Load model: ADC input network or capacitive load (kickback severity, effective capacitance, any Riso/buffer).
Pass criteria style (keep measurable)
Define acceptance in system terms (e.g., “settles within the acquisition window”, “no sampling-correlated ringing”, “in-band noise meets the target”). Numerical thresholds are filled by the system noise/distortion budget later.
Figure 4 — Map system goals to filter specs (fc, Q, gain, headroom, load)
System goals to Sallen-Key filter specs mapping A mapping diagram connecting anti-alias, denoise, and HP drift goals to filter specs including fc, Q, gain, headroom, and load interaction. Anti-alias goals alias margin settling window Denoise goals in-band noise step response HP drift goals drift removal Filter specs fc Q gain headroom load interaction goals → specs
This mapping keeps the page scope tight: choose fc and Q from system acceptance (alias, settling, noise), then validate headroom and load interaction before finalizing component values.

H2-5. Synthesis: Picking R/C (Practical design flow, no over-math)

What this section delivers

A reusable component-picking workflow for 2nd-order Sallen-Key LP/HP: start from C family, choose ratio-friendly R values, then validate with the shortest loop (AC → step → Monte Carlo). Higher-order synthesis and non-Sallen-Key topologies are intentionally out of scope.

A) Design flow (steps 1–6, minimal friction)

  1. Lock inputs: target fc, Q, optional gain K, supply/headroom, and a load model (ADC input network or capacitive load).
  2. Choose capacitor family first: prioritize stable dielectric (NP0/C0G when practical) and a value range that keeps parasitics small while not overloading the op-amp.
  3. Compute ratio-friendly resistors: pick resistor ratios that can be matched reliably in real parts; avoid “exotic” ratios that push Q sensitivity into manufacturing noise.
  4. Select absolute R magnitude: balance thermal noise + bias/leakage error (too large R) against drive/linearity/stability stress (too small R).
  5. Run the shortest verification loop: AC for fc/Q/peaking, step for ringing/settling, Monte Carlo for fc/Q spread and worst-case corners.
  6. Iterate with the right knobs: adjust ratios and interface elements (e.g., isolation/damping) before changing topology; escalate to other filter families only if a 2nd-order corner cannot meet acceptance.
Why “C first” works
Fixing the capacitor family and range early reduces drift and parasitic dominance. Resistor ratios can then be chosen for matching and repeatability, which directly stabilizes Q behavior across builds.

B) Component range rules (avoid the “silent failures”)

  • R too large → more thermal noise, more bias/leakage-induced error, and longer recovery (HP bias paths and baseline behavior become fragile).
  • R too small → heavier output drive, higher distortion risk, and reduced stability margin—especially when the load includes capacitance or ADC kickback.
  • C too small → parasitics become a large fraction of the intended value; fc/Q drift and channel-to-channel spread increase.
  • C too large → op-amp drive and phase margin become harder to maintain; ringing and settling failures become more likely.
  • Match what drives Q → prioritize ratio match (same series, same package, tight tolerance) over chasing nominal values.
  • Always keep DC paths explicit → HP variants and single-supply biasing must have a defined return; otherwise the build can drift or rail-stick despite “correct” nominal fc/Q.
A practical priority order
Prioritize: DC legality → ratio-friendly Q → load stability → headroom under peaking → only then fine-tune nominal fc.

C) Simulation checklist (AC / step / Monte Carlo)

AC (frequency-domain)
  • Confirm fc and peaking behavior (Q) against acceptance limits.
  • Check phase trend around the corner for obvious anomalies (a fast indicator of weak loop margin).
  • Include the expected load model (capacitive load or ADC input network) before signing off.
Step (time-domain)
  • Observe overshoot and ring-down; verify settling within the measurement or acquisition window.
  • Repeat with worst-case load (capacitance, cable, ADC kickback equivalent).
  • Flag sampling-correlated spikes/ringing as a stability/interface issue, not a “minor artifact”.
Monte Carlo (manufacturability)
  • Plot fc/Q distribution and confirm worst-case corners remain inside system margin.
  • Identify the dominant tolerance contributor (ownership of error budget) and improve matching accordingly.
  • Use the result to decide whether trimming or calibration hooks are needed (handled later in the page).
Figure 5 — Practical R/C picking flow (inputs → choices → verification loop)
Sallen-Key RC synthesis flowchart Flowchart from system inputs to capacitor family selection, resistor ratio choice, verification steps, and outputs with a feedback loop for iteration. Inputs fc / Q / gain K supply / headroom load model Choose C family Compute R ratios Pick R magnitude Verify AC Verify Step Verify Monte Carlo Outputs R/C set risk notes pass checks Fail → adjust ratios / interface Keep the loop short: AC → Step → Monte Carlo
The flow prioritizes repeatable ratios and real load models so Q behavior and settling are stable across builds.

H2-6. Op-Amp Requirements (GBW, phase margin, slew, output drive)

Why “GBW is enough” is not enough

Sallen-Key performance depends on the op-amp’s loop margin under the real noise-gain shape and the real load. High Q, gain K, and capacitive/ADC loads can reduce phase margin and break settling even when the nominal GBW looks large.

A) Must-check specs (what actually gates success)

  • GBW / loop gain: sets the available correction near fc; insufficient loop gain increases peaking and degrades settling.
  • Phase margin under load: the dominant gate for ringing/oscillation; capacitive loads and ADC input networks often add harmful phase lag.
  • Slew rate (SR): large-signal steps can fail to settle even when small-signal AC looks correct; SR limits distort waveforms and extend settling time.
  • Output swing & headroom: Q peaking and gain K increase peak amplitude; clipping can occur well before “nominal” level if headroom is tight.
  • Output drive (current + capacitive stability): insufficient drive causes amplitude droop and THD collapse; marginal cap-drive causes sampling-correlated ringing.
  • Input CM range & bias behavior: single-supply bias points must be legal across temperature; missing or weak DC paths lead to drift and rail sticking.
  • Noise & distortion (en/in, THD/SFDR): real performance depends on source impedance, swing, and load; datasheet “typical” conditions may not match the application.

B) Quick checks (bench and simulation, fast signal)

Oscilloscope checks
  • Small-signal step: overshoot/ringing indicates weak phase margin and/or harmful load interaction.
  • Repeat with worst-case load: added capacitance and ADC input behavior often expose marginal stability.
  • Large-signal step/sine: watch for slew limiting, clipped peaks, or amplitude droop under drive stress.
Simulation checks
  • AC with load models: confirm peaking and identify phase weakness around the corner.
  • Transient settling: validate time-domain window; include the same load conditions used on the bench.
  • Cap-load sweep: scan output capacitance to find stability edges early (especially with ADC networks).

C) Common traps (what causes avoidable respins)

  • RRIO ≠ strong driver: rail-to-rail does not guarantee low distortion or stable cap drive.
  • GBW “looks big” ≠ stable: phase margin can collapse with high Q, gain K, or capacitive/ADC loads.
  • Stable at no-load ≠ stable in-system: the real load is often the dominant pole/phase source.
  • Datasheet THD is conditional: frequency, swing, and load often differ from the application.
  • Input CM “okay” ≠ output headroom okay: single-supply bias plus peaking can clip early.
  • Low overshoot ≠ fast settling: acceptance is typically a time-window criterion, not a visual waveform preference.
  • Smaller R is not always safer: drive stress rises and stability may worsen under capacitive loads.
  • Bigger C is not always safer: heavier capacitive loading can reduce phase margin and increase ringing.
A clean mental model
Op-amp selection is a gate system: loop margin (GBW/PM) protects stability and settling; SR/swing/drive protect large-signal behavior; noise/THD protect the final measurement quality.
Figure 6 — Op-amp gates: targets → specs → failure symptoms
Op-amp selection gates for Sallen-Key filters Three-column diagram mapping system targets to op-amp specification gates and to observable failure symptoms such as ringing, oscillation, THD collapse, clipping, and settling failure. Targets fc / Q gain K load (ADC / C) headroom noise / THD Op-amp gates GBW / loop gain phase margin slew rate swing / Iout cap drive noise / THD Failure symptoms ringing oscillation settling fail THD collapse amplitude droop clipping High Q + gain K + real loads tighten the stability gate
Use the gates to explain failures quickly: stability issues map to PM/cap drive, time-window failures map to SR/loop gain, and quality limits map to noise/THD under real swing and load.

H2-7. Q Sensitivity & Tolerances (Why it drifts, how to tame it)

The defining trait of Sallen-Key: Q is ratio-sensitive

In Sallen-Key, the 2nd-order damping is shaped by R/C ratios and feedback. Small ratio shifts change damping more than many designers expect, so Q (peaking and ring-down) can drift even when nominal fc looks “correct”. The goal is to make Q behavior repeatable across temperature, builds, and loads.

A) Sensitivity map (what moves fc vs what moves Q)

Practical rule-of-thumb
  • fc tends to follow absolute values (the effective R and C magnitudes). Parasitic capacitance and capacitor drift often show up as fc shift.
  • Q tends to follow ratios (R/C matching and ratio tracking). Small ratio errors can cause large changes in peaking and ring-down time.
  • Loads make Q “conditional”: capacitive/ADC loads can change the effective damping and expose marginal stability.
Fast prioritization
If peaking/ringing changes between units: suspect ratio match, parasitics, and load. If only the corner moves: suspect effective capacitance drift.

B) BOM guidelines (make ratios stable and repeatable)

Capacitors
  • Use stable dielectric when Q must be consistent (NP0/C0G is a common baseline).
  • Keep the two capacitors “as a pair”: same series, same package, similar thermal environment.
  • Watch parasitic dominance: too-small C magnifies PCB pad/trace capacitance impact and increases unit-to-unit spread.
Resistors
  • Prefer matched networks for ratio-critical parts (tracking beats absolute accuracy for Q).
  • Keep ratio parts thermally coupled: adjacent placement improves tracking through temperature swings.
  • Avoid extreme R magnitudes: large R increases noise and leakage/bias sensitivity; small R increases drive stress and distortion risk.
PCB parasitics are “hidden components”
Pads, traces, and input/output capacitances can shift effective C and ratios. Keep sensitive nodes short, keep paired parts symmetric, and avoid routing that makes one side “see more capacitance” than the other.

C) Calibration hooks (interfaces only, no system algorithms)

  • Trim pads for small C steps: reserve footprints for optional parallel caps to nudge fc or peaking when parasitics dominate.
  • Ratio swap options: reserve alternate resistor footprints (two/three discrete ratio choices) to tame Q spread without redesigning the topology.
  • Bypass and loopback jumpers: allow fast isolation between filter drift and downstream coupling (especially with ADC/driver networks).
  • Measurement test points: provide stable probing for key nodes to avoid “probe capacitance as a hidden component”.
Acceptance mindset
The objective is not “perfect nominal values”. The objective is predictable peaking and settling across temperature and builds under the real load.
Figure 7 — Tolerances → parameter drift → symptoms → mitigation
Sallen-Key tolerance causality chain Causality chain mapping tolerance, temperature and parasitics to fc and Q shifts, then to observable symptoms, plus mitigation actions such as stable capacitors, matched networks, layout symmetry, and trim hooks. Sources tolerance / temp parasitics load coupling humidity / leakage Parameter shift fc shift Q shift Symptoms peaking ringing alias leak unit spread Mitigation NP0/C0G + match thermal co-location parasitic control trim / jumpers Q is damping: ratio drift changes peaking and ring-down
Treat parasitics and load coupling as first-class terms; otherwise Q will look “random” across builds.

H2-8. Noise, Dynamic Range & Distortion Budget (Make it measurable)

Budget first: noise and THD are system properties

A Sallen-Key stage can reduce in-band noise by shaping bandwidth, but it can also create peaking that burns headroom and raises distortion. This section provides a budget template, measurement hooks, and pass-criteria placeholders so results stay consistent across benches and builds.

A) Budget template (by block: source → op-amp → R/C → load/ADC)

Noise contributors (in-band)
  • Source impedance: thermal noise and any upstream noise density shaped by the filter transfer.
  • R network: resistor thermal noise rises with R; large R also amplifies bias/leakage sensitivity (appears as low-frequency “noise”).
  • Op-amp en/in: the dominant term depends on source-Z and where the noise is injected within the topology.
  • Load/ADC: sampling-related artifacts can fold into the measurement band if ringing is present.
Distortion contributors (THD/SFDR risk)
  • Headroom and peaking: Q peaking increases peak swing near the corner and can force early clipping.
  • Output current & cap drive: heavier loads raise nonlinearity and can trigger oscillation-like ringing.
  • Slew rate: large-signal steps and high-frequency large swing can fail to settle and spike THD.
  • Common-mode bias (single-supply): illegal CM points or asymmetric swing often cause “mysterious” distortion.
Dynamic range gate (always include this field)
Track a headroom margin under peaking and worst-case load; average amplitude checks miss peak-driven clipping.

B) Measurement hooks (repeatable noise and THD checks)

Noise measurement
  • Set a defined input condition: short, known source impedance, or the real sensor impedance.
  • Fix bandwidth and acquisition length; use the same filtering and windowing across comparisons.
  • Confirm stability first: ringing and sampling-correlated spikes can masquerade as “noise”.
THD/SFDR measurement
  • Sweep amplitude and frequency under the real load and bias point; record the “last clean level”.
  • Watch for peak-driven clipping near the corner when Q is high or headroom is tight.
  • Repeat with and without the expected load network to expose drive-limited distortion.
A useful separation test
If noise floor changes drastically when connecting the load/ADC network, treat it as a stability/interface problem first, not a pure noise problem.

C) Pass criteria (placeholders; X is set by the system budget)

  • In-band RMS noise < X (Vrms or LSB-rms under the defined bandwidth).
  • Peaking margin < X (dB), or peak headroom > X (% of available swing).
  • THD < X (dBc) and/or SFDR > X (dBc) at the defined load and amplitude.
  • Settling window: |error| < X by time T (time aligned to the acquisition window).
Keep it consistent
Define the bandwidth, load, and amplitude conditions in the budget. Without consistent conditions, measurements will not match simulations or production builds.
Figure 8 — Budget stacks (noise vs distortion) + headroom gate
Noise and distortion budget stacks for Sallen-Key front-ends Two stack diagrams: noise contributors rolled into in-band total and distortion contributors rolled into SFDR/THD risk. A headroom gate highlights Q peaking and swing margin as a common failure trigger. Noise stack source thermal R thermal op-amp en/in layout pickup ADC / downstream in-band total Distortion stack swing / headroom slew rate output current cap load / ADC CM bias effects SFDR / THD risk Headroom gate: Q peaking can trigger early clipping No numbers here: use measurements to fill the budget
Keep budgets tied to fixed conditions (bandwidth, load, amplitude). Otherwise measured noise and distortion will be inconsistent across benches and builds.

H2-9. Interfacing: Source-Z, Load, and ADC Anti-Alias Front-End

Why the bench looks perfect, then collapses with a real ADC

A Sallen-Key stage is often simulated with ideal sources and static loads. On hardware, the source impedance can shift fc/Q and raise noise, while an ADC input behaves like a dynamic capacitive load that injects kickback currents. Interfacing must be treated as part of the filter design: stability and settling are load-dependent.

A) Source interaction (low-Z / mid-Z / high-Z sensor)

Low-Z source (buffered driver)
Symptom: looks clean no-load, then rings or distorts when the ADC/load is connected.
Quick check: disconnect the ADC and replace it with a purely resistive load; compare step response.
Fix: add Riso at the output node first; keep it small and validate settling under the real sampling window.
Pass criteria: ringing amplitude < X and |settling error| < X by time T (X set by system budget).
Mid-Z source (series R/RC or upstream stage impedance)
Symptom: fc shifts, unexpected peaking appears, or in-band noise increases.
Quick check: emulate the source impedance with a precision resistor and re-run an AC sweep for fc/Q.
Fix: rebalance the R/C ranges (avoid extreme values) or buffer the input if the source must remain high impedance.
Pass criteria: fc/Q remain within the allowed spread across the defined source-Z range.
High-Z sensor (leakage- and parasitic-sensitive)
Symptom: slow drift, touch/probe sensitivity, strong humidity/temperature dependence.
Quick check: compare results with short cables and low-capacitance probing; observe whether fc/Q changes with probing.
Fix: treat leakage and parasitics as first-class terms: shorten sensitive nodes, improve cleanliness, and isolate with a buffer when required.
Pass criteria: drift and probe sensitivity remain below X under the defined environment conditions.

B) ADC load interaction (kickback, sampling, stability, settling)

An ADC input is not a static resistor. During sampling, the input switch charges the sampling capacitor, producing a current pulse that flows through the output impedance and any series elements. This kickback can excite ringing, shrink phase margin, and extend settling beyond the acquisition window.
Interface-first diagnosis
  • Probe both nodes: the filter output node and the ADC pin after Riso.
  • Compare “ADC connected” vs “ADC replaced by a resistor”; large differences indicate a kickback/interface problem.
  • Validate settling to the actual sampling window, not to a generic “looks stable” time scale.
Common traps
  • “GBW is high” does not guarantee stability under kickback and capacitive loading.
  • “No-load THD is good” does not guarantee THD/SFDR under real output current and peaking.
  • Adding an output RC can help spikes but can also create new poles and worsen phase margin if not validated.

C) Debug flow (shortest loop from symptom → root cause → fix)

  1. Baseline: test the filter with a resistive load (no ADC) using AC sweep + step response.
  2. Interface toggle: connect the ADC input network; record ringing, spikes, and settling to the sampling window.
  3. Riso sweep: increase Riso in small steps to find a stable region that still meets settling requirements.
  4. Spike control (if needed): add a small output RC/snubber only when high-frequency ringing dominates.
  5. Re-validate: repeat AC + step + FFT under identical conditions.
  6. Lock pass criteria: settle error < X by time T, and THD/SFDR meet X under real amplitude and load.
Interface problems should be proven by a load toggle test
If the result changes drastically when the ADC network is connected, treat it as an interface/stability issue before tuning noise or component tolerances.
Figure 9 — ADC front-end interface with kickback path
Sallen-Key interfacing to an ADC input network Block diagram from source through source impedance into a Sallen-Key filter, then through Riso into an ADC sampling capacitor and switch. A kickback arrow shows charge injection returning toward the filter output node. Mitigation blocks include Riso, small RC, and buffer. Stability + settling are load-dependent (ADC input is dynamic) Source Source-Z Sallen-Key LP / HP output node Riso ADC input Cin + switch kickback Common mitigations Riso tuning small RC / snubber buffer isolation Validate with load toggle: resistor load ↔ ADC network (same measurement conditions)
Riso is usually the first lever. Tune it against both stability and settling within the real acquisition window.

H2-10. Engineering Checklist (Design + Layout + Verification)

A reusable review stack: design → layout → test

The checklist below turns Sallen-Key success into a repeatable process. Each item is written to be verifiable with measurements and tied to a pass criterion placeholder (X set by the system budget).

A) Design review checklist (prioritized)

  • P0: fc/Q meet the system target, including peaking and headroom margin under worst-case conditions.
  • P0: stability and settling are validated with the real load (ADC network and expected capacitance).
  • P0: settling within the acquisition window: |error| < X by time T (X set by budget).
  • P1: tolerance/temperature spread is bounded (Monte Carlo and worst-case corner checks align with hardware reality).
  • P1: noise and distortion budgets are both satisfied (no “noise-only” tuning that breaks THD/SFDR).
  • P2: serviceability hooks exist: jumpers, trim pads, and stable test points for fast isolation and rework.
Review record fields (recommended)
Target: ___   Measured: ___   Condition: ___   Pass: Y/N

B) Layout review checklist (by node and loop)

  • Input nodes: keep short and clean; avoid asymmetric parasitics and coupling from high dv/dt traces.
  • Feedback and capacitor loops: minimize loop area; keep return paths continuous; avoid plane splits across sensitive returns.
  • Output to Riso/ADC: route with clear return; prevent parallel coupling back into the input/feedback region.
  • Thermal pairing: place ratio-critical R/C parts together in the same thermal zone; avoid heat gradients.
  • Leakage control (high-Z cases): reduce contamination risk and manage surface leakage; treat humidity as a design variable.
Layout determines “hidden C” and “hidden coupling”
If two boards with the same BOM behave differently, suspect parasitics, thermal gradients, and coupling paths before changing topology.

C) Test plan checklist (what to measure + pass placeholders)

  • AC sweep: fc/Q/peaking within X across the defined source-Z and load range.
  • Step response: overshoot < X and |settling error| < X by time T (aligned to acquisition window).
  • Load perturbation: toggle resistor load ↔ ADC network; verify stable window across Riso tuning.
  • FFT check: THD/SFDR meet X at the defined amplitude, bias point, and load.
  • Temp/lot checks: compare spread across temperature and units; confirm it matches simulation expectations.
  • Probe sensitivity: verify the result does not shift beyond X with realistic probing and cabling conditions.
Keep measurement conditions identical
Bandwidth, load, amplitude, and bias point must be documented. Without fixed conditions, “failures” will appear inconsistent across benches.
Figure 10 — Checklist visualization (Design / Layout / Test)
Engineering checklist for Sallen-Key filters Three-column checklist visualization. Columns are Design, Layout, and Test with short bullet labels and check icons. Footer notes that pass criteria X comes from the system budget. Review stack: Design → Layout → Test (each item must be measurable) Design Layout Test fc / Q headroom GBW / PM settling tolerance noise / THD hooks short nodes symmetry return path loop area thermal pair guard/isolate Riso close AC sweep step load toggle FFT temp lot spread MC compare Pass criteria uses X from the system budget (document conditions)
Keep each checklist item tied to a measurement condition (bandwidth, load, amplitude, and bias point).

H2-11. Applications (Anti-alias, denoise, sensors, audio/measurement)

Copyable application recipes (only what Sallen-Key owns)

This section provides reusable chain templates for where a 2nd-order Sallen-Key LP/HP is the right tool: gentle anti-alias roll-off, bandwidth shaping for denoise, and low-to-mid Q shaping for audio/measurement. When targets require steeper roll-off or strict group delay, link out to cascaded biquads or phase equalizers.

A) Anti-alias front-end recipes (3 templates)

AA-1: Robust 2nd-order LP (stability + settling first)
Use case: first-stage roll-off before an ADC; moderate attenuation needs; low-to-mid Q only.
Goal: reduce alias energy while keeping settling within the acquisition window under real ADC kickback.
Core choices: place fc conservatively vs signal BW; avoid aggressive peaking; treat headroom as part of the filter spec.
Interface notes: include Riso and validate both nodes (filter output and ADC pin) under sampling.
Verification: AC sweep + step-to-window + load toggle (resistor load ↔ ADC network).
Pass criteria: alias leak < X and |settling error| < X by time T (X,T from system budget).
Example op-amp BOM (starting points; verify under your load)
• TI OPA320 (RRIO precision) — OPA320
• TI OPA350 (RRIO high-speed) — OPA350
• ADI ADA4807-2 (RRIO high-speed) — ADA4807-2
AA-2: 2nd-order LP as “first roll-off”, reserve higher-order later
Use case: a clean, low-risk first pole-pair; steeper attenuation is handled by cascaded biquads downstream.
Goal: shape BW without destabilizing the ADC drive; keep group delay moderate (not “strict”).
Core choices: set the 2nd-order stage for predictable behavior across tolerance and load.
Interface notes: if the downstream stage is a driver/FDA, validate inter-stage loading.
Verification: measure fc/Q drift over temperature and unit spread; confirm it does not break alias margin.
Pass criteria: fc/Q spread stays within allowed guardband; no peaking-induced clipping.
Link-out triggers (do not expand here)
Need steeper roll-off → Cascaded Biquads Need strict group delay → All-Pass / Phase EQ
AA-3: HP + LP “band window” (drift removal + alias shaping)
Use case: remove DC / slow drift first, then limit BW for noise and alias.
Goal: prevent low-frequency drift from consuming headroom while keeping the passband clean.
Core choices: HP corner must preserve the lowest useful signal content; LP corner must match the sampling plan.
Interface notes: HP stages can be leakage- and bias-current sensitive; validate in the real environment.
Verification: drift step test + step response + FFT at target amplitude.
Pass criteria: drift-induced offset is bounded; no early clipping from peaking/headroom loss.

B) Denoise recipes (3 templates)

DN-1: Sensor bandwidth shaping (LP to reduce in-band RMS noise)
Use case: low-to-mid bandwidth sensors where noise is dominated by wideband content.
Goal: measurable reduction in in-band RMS noise without introducing peaking or long recovery.
Core choices: avoid high Q; keep component ratios stable; treat source impedance as part of the filter.
Interface notes: high-Z sensors require leakage/parasitics control; probe and humidity can change results.
Verification: RMS noise in-band + drift check + Monte Carlo alignment with unit spread.
Pass criteria: noise reduction meets target and fc/Q drift stays within guardband.
Example op-amp BOM (precision / drift control)
• ADI ADA4522-2 (zero-drift) — ADA4522-2
• TI OPA2188 (zero-drift) — OPA2188
• ADI ADA4077-2 (precision) — ADA4077-2
DN-2: Prevent saturation (HP for drift + LP for BW; headroom-aware)
Use case: slow drift or offset steps exist; downstream ADC/PGA clips early without conditioning.
Goal: remove low-frequency “energy” that consumes dynamic range, then limit BW for noise.
Core choices: HP corner is set by the lowest useful signal content; LP corner is set by noise/alias budget.
Interface notes: HP nodes are sensitive to bias current and leakage; avoid extreme resistor values.
Verification: drift step + large-signal recovery + FFT under real amplitude.
Pass criteria: no long recovery after CM/drift steps; no early clipping from peaking/headroom loss.
DN-3: Audio / measurement shaping (low-to-mid Q, distortion-controlled)
Use case: bandwidth shaping for audio/measurement where distortion and transient fidelity both matter.
Goal: predictable response without peaking-induced clipping; keep THD/SFDR controlled under real swing.
Core choices: use conservative Q unless the full tolerance stack is proven; treat output drive as a first-class spec.
Interface notes: strict group delay targets require link-out to all-pass/biquads (no expansion here).
Verification: THD vs amplitude sweep + step response + load sensitivity.
Pass criteria: THD/SFDR meet target at required swing and load; no ringing under final interconnect.
Example op-amp BOM (audio / low distortion)
• TI OPA1656 (audio) — OPA1656
• TI OPA1612 (audio) — OPA1612
• ADI ADA4898-2 (low noise/distortion) — ADA4898-2

C) Failure modes per application (2 common failures each)

ADC anti-alias
Failure 1: Rings / fails settling only when ADC is connected
Likely cause: ADC kickback and capacitive loading reduce phase margin at the filter output node.
Quick check: load toggle (resistor load ↔ ADC network) and probe both nodes (output vs ADC pin).
Fix: tune Riso first; add a small RC/snubber only if ringing is high-frequency dominated; buffer if needed.
Pass criteria: |settling error| < X by time T within the acquisition window (X,T from budget).
Failure 2: Unexpected peaking or fc/Q shift (alias leak rises)
Likely cause: source impedance/parasitics change effective ratios; tolerance stack moves Q.
Quick check: emulate source-Z with precision resistors; AC sweep fc/Q vs source-Z corners.
Fix: rebalance R/C ranges; reduce sensitivity by choosing friendlier ratios; tighten C0G/NP0 and matching.
Pass criteria: fc/Q spread stays within guardband; alias margin stays above X.
Sensor denoise
Failure 1: Drift / touch sensitivity / humidity dependence
Likely cause: leakage and parasitics dominate at high-Z nodes; probing adds capacitance.
Quick check: compare with short wiring and low-C probing; observe fc/Q shifts when probing.
Fix: avoid extreme resistor values; shorten sensitive nodes; isolate with a buffer when required.
Pass criteria: drift and sensitivity stay below X across defined environment.
Failure 2: Early clipping / THD rises after “denoise tuning”
Likely cause: Q peaking increases peak swing; headroom budget was not enforced.
Quick check: sweep amplitude and observe clipping onset vs peaking; FFT vs amplitude.
Fix: reduce peaking; increase headroom; or move shaping elsewhere (do not force high Q here).
Pass criteria: no clipping at target input + margin; THD/SFDR stays within X.
Audio / measurement
Failure 1: Transient fidelity or group delay target not met
Likely cause: strict group delay goals exceed what a simple 2nd-order stage can guarantee.
Quick check: compare step/impulse response against target (overshoot, ringing, decay).
Fix: link out to all-pass / cascaded biquads for phase and higher-order control.
Pass criteria: time-domain error metrics meet X under the defined bandwidth and load.
Failure 2: THD looks fine no-load, fails in system
Likely cause: output current and capacitive loading increase distortion; RRIO behavior degrades near rails.
Quick check: measure THD/SFDR at the required swing with the final interconnect/load.
Fix: choose an op-amp specified for distortion under load; add buffer isolation if needed.
Pass criteria: THD/SFDR meet X at swing/frequency/load corners.
Figure 11 — Application chain assembly (3 reusable chains)
Sallen-Key application chains: sensor, audio, and DAQ Three chain templates: Sensor to Sallen-Key LP to Riso to ADC with kickback arrow; Audio to Sallen-Key HP to ADC; DAQ to Sallen-Key LP to PGA/ADC. Risk tags shown under each chain. Link-out tags show when to use cascaded biquads or all-pass. Recipes are chain-level templates (validate with real source + load) Chain 1 Sensor → SK LP → Riso → ADC Sensor Sallen-Key LP Riso ADC kickback Source-Z drift fc/Q shift Settling window Chain 2 Audio → SK HP → ADC Audio Sallen-Key HP ADC DC removal THD under load Chain 3 DAQ → SK LP → PGA/ADC DAQ Sallen-Key LP PGA / ADC Gain range + BW Settling vs range Need order → Biquads Need phase → All-pass
Each chain must be validated with the real source impedance and the real ADC (kickback + sampling window).

H2-12. IC Selection Logic (Op-amp choice fields + inquiry checklist)

Convert datasheet items into measurable risk control

Sallen-Key success is not “pick a big GBW.” Selection must prove stability and settling under the real load (ADC kickback), then confirm headroom and distortion under the required swing. Use the table and inquiry checklist below to force evidence under your conditions.

A) Selection table (Spec field → Why → Failure signature → Quick check → Mitigation)

GBW / open-loop behavior Risk: peaking / instability
Why: Sallen-Key noise gain and feedback shape interact; GBW must support phase margin under real loading.
Failure signature: unexpected peaking, ringing, or “works no-load but fails in system.”
Quick check: AC sweep + step response with ADC network connected; compare to resistor-load baseline.
Mitigation: adjust Riso and ratio choices; if PM cannot be secured, buffer or change topology.
Capacitive-load drive / stability notes Risk: kickback oscillation
Why: ADC inputs are dynamic capacitive loads; kickback stresses the output node and PM.
Failure signature: short bursts of ringing at sampling edges; long settling beyond acquisition window.
Quick check: scope trigger on sampling clock; observe output node and ADC pin; run load toggle test.
Mitigation: Riso tuning first; then small RC/snubber if needed; buffer when margins remain insufficient.
Output swing / output current Risk: early clipping
Why: peaking and load current raise peak swing; RRIO stages often degrade near rails.
Failure signature: THD jumps at high swing, recovery slows near rails, or amplitude collapses under load.
Quick check: THD vs amplitude with final load; compare rail headroom corners.
Mitigation: increase headroom, reduce peaking, choose an amplifier specified for distortion under load.
Slew rate (large-signal) Risk: step distortion
Why: step/impulse response and high-frequency large signals can become slew-limited.
Failure signature: slow edges, asymmetric waveform, or distortion that grows with amplitude.
Quick check: time-domain large-signal step and FFT vs amplitude at target frequency band.
Mitigation: reduce required swing, increase headroom, or select a higher SR amplifier.
Input noise (en/in) + 1/f Risk: missed SNR
Why: Sallen-Key shapes bandwidth; the remaining in-band noise must hit system SNR/ENOB targets.
Failure signature: noise floor higher than expected; unit-to-unit spread if bias/leakage dominates.
Quick check: measure in-band RMS noise with a fixed bandwidth; compare against budget template (H2-8).
Mitigation: rebalance R/C, reduce source impedance impact, choose lower-noise parts where needed.
THD/SFDR vs swing + frequency + load Risk: distortion spikes
Why: distortion must be proven under the real amplitude and load, not just “no-load typical.”
Failure signature: spurs appear only at certain loads or when the chain is fully assembled.
Quick check: sweep THD/SFDR with final load model; compare against system spur limits.
Mitigation: select a part specified for low distortion under load; adjust headroom and peaking.
Input bias / input CM range Risk: drift / recovery
Why: HP and biasing networks can become bias/leakage dominated; CM limits can cause long recovery near rails.
Failure signature: slow drift, bias-dependent offset, or long recovery after common-mode steps.
Quick check: bias point sweep + soak test; confirm behavior with real PCB leakage and temperature.
Mitigation: rebalance resistor ranges; choose lower Ib parts; enforce CM margins under worst-case.
“RRIO” caveats (near-rail behavior) Risk: hidden distortion
Why: rail-to-rail does not guarantee linearity or fast recovery close to rails with real loads.
Failure signature: waveform “looks okay” but THD/SFDR is poor; recovery is slow after saturation.
Quick check: test near-rail operation at required load; include the worst-case output current corner.
Mitigation: keep headroom; select parts with distortion specs near rails; or change supply strategy.

B) Vendor questions (copy/paste inquiry checklist)

Request evidence under the actual conditions. Do not accept “typical no-load curves” for a Sallen-Key driving an ADC.
Inquiry template (fill blanks)
Application: Sallen-Key LP/HP Supply: ____ V (single/dual), bias/Vcm: ____ Target fc: ____ , target Q: ____ , gain K: ____ Signal: amplitude ____ , frequency range ____ Load model: – Rload: ____ ohm – Cload: ____ pF (plus ADC input network) – ADC sampling: Cin ____ , switch/kickback present (yes/no) Settling requirement: – acquisition window T: ____ us – required error: < X (define LSB or %FS) Please provide: 1) Stability / phase margin evidence under the above Cload/ADC model 2) Step settling to < X within T under the above load 3) THD/SFDR at the above swing + frequency under the above load 4) Output swing/current capability at the above load and near-rail behavior notes

C) Decision flow (Spec → Risk → Action)

  1. Prove stability under real load: ADC network connected, worst-case Cload corner included.
  2. Prove settling to the window: |error| < X by time T inside the acquisition window.
  3. Prove headroom + distortion: THD/SFDR at the required swing and frequency under final loading.
  4. If any step fails: take the minimal fix first (Riso / ratio / headroom), then buffer, then change topology.
Fail stability → Riso / buffer Fail settling → R/C range + load control Fail THD → headroom + better part Need high Q/steep → change topology

D) Reference part numbers (official links; starting points only)

These part numbers speed up datasheet lookup and lab evaluation. Selection must be proven by the load + window requirements above.

RRIO single-supply / general AAF
• TI OPA320   • TI OPA350   • TI TLV9062
Precision / drift control (sensors, low-frequency)
• ADI ADA4522-2   • TI OPA2188   • ADI ADA4077-2   • TI OPA2140
Audio / low distortion
• TI OPA1656   • TI OPA1612   • ADI ADA4898-2
Fast AAF / ADC-facing (prove load stability)
• ADI ADA4807-2
When the ADC is differential (link-out path)
• ADI ADA4940-1 (fully differential driver; use when the chain is differential)
Figure 12 — Selection flow (Spec → Risk → Decision)
Op-amp selection flow for Sallen-Key filters Three-column flowchart. Left column lists datasheet specs, middle column lists risks/failure signatures, right column lists decisions/actions. Bottom bar emphasizes vendor inquiry under real load and settling window. Prove stability + settling under real ADC load before tuning noise/THD Spec Risk Action GBW / PM Cload drive Swing / Iout SR Noise THD / SFDR Ringing Settling fail Clipping THD rise Noise miss Tune Riso Add buffer Fix headroom Change part Change topology Ask vendor under your load model + settling window (no “typical no-load” answers) Cload / ADC kickback / swing / frequency / T-window / error target
The winning candidate is the one that stays stable and settles inside the real acquisition window with the real ADC network.

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FAQs: Sallen-Key LP/HP (GBW, Q tolerance, interfacing, single-supply bias)

Each answer uses a fixed, measurable 4-line format to keep troubleshooting fast and avoid sideways expansion.

Why does the cutoff shift after PCB assembly even with 1% parts?
Likely cause: Parasitic C/R and capacitor voltage/temp coefficients shift the effective ratios; “1%” does not guarantee matched ratios at the operating bias.
Quick check: Measure fc on-board, then add a small known parallel capacitor (e.g., +0.5–2 pF equivalent) at the sensitive node to see if the fc shift tracks parasitics; compare two boards for repeatability.
Fix: Use NP0/C0G for frequency-setting capacitors, shorten/guard sensitive nodes, and reserve a tiny trim footprint (parallel-C or swap option) for post-assembly correction.
Pass criteria: |fc_meas − fc_target|/fc_target ≤ X% across N boards at the intended DC bias, and fc drift over temperature ≤ X% (T1→T2).
Why does the filter ring/overshoot much more than simulation?
Likely cause: Real loop phase margin is lower than the model (GBW/phase, output stage, parasitics), and the load/probing adds extra poles that increase peaking.
Quick check: Repeat a step test with (a) no external load, (b) intended load, and (c) added Riso; use a short ground spring to eliminate probe-lead inductance artifacts.
Fix: Reduce sensitivity (lower Q target / more robust ratios), add Riso or a buffer stage, and keep the capacitor loop tight with minimal node area.
Pass criteria: Overshoot ≤ X% and settle to within ±X% of final value in ≤ T, with no sustained oscillation under worst-case load/probe conditions.
How do I tell “GBW not enough” vs “load capacitance instability”?
Likely cause: Insufficient GBW/PM shows broad peaking and slow, underdamped response even with light load; capacitive-load instability appears strongly dependent on output C and wiring.
Quick check: Keep the filter the same and sweep output loading: add/remove a known capacitor (e.g., 50–500 pF) and insert/remove Riso; observe whether ringing frequency and amplitude track the added C.
Fix: If GBW/PM-limited: lower fc/Q or use a faster op-amp; if Cload-limited: add Riso, reduce direct Cload, or add a dedicated output buffer/driver.
Pass criteria: Stable step response (no sustained oscillation) across the defined load window, and peaking/ringing variation ≤ X% when toggling the specified Cload/Riso extremes.
Why does Q vary a lot across temperature?
Likely cause: Q is ratio-sensitive; capacitor tempco/mismatch, resistor network tracking, and op-amp GBW/phase drift with temperature change loop damping.
Quick check: Measure both fc and peaking/overshoot at two temperatures; if fc stays similar but peaking changes, damping/PM is drifting (ratios/op-amp), not just absolute values.
Fix: Use matched networks (resistor arrays), NP0/C0G caps, co-locate critical parts for thermal tracking, and avoid operating near stability limits (headroom/PM).
Pass criteria: Q (or peaking in dB) drift ≤ X% (or ≤ X dB) over T range, and step overshoot remains ≤ X% at T-min/T-max.
Why does the LP look fine no-load but fails with the ADC connected?
Likely cause: The ADC input is a switched-capacitor load; sampling kickback and dynamic input current reduce phase margin and break settling even if AC magnitude looks acceptable.
Quick check: Compare waveforms at (a) filter output pin and (b) ADC input pin; toggle ADC sampling (or swap to an equivalent RC load) to confirm kickback-driven instability/settling error.
Fix: Add Riso (start from a small value and iterate), optionally add a small shunt C at the ADC side to localize charge, or insert a buffer/driver stage when settling requirements are tight.
Pass criteria: At the ADC pin, settle to within the system error window (e.g., ≤ X mV or ≤ 0.5 LSB) within the acquisition time T_acq under worst-case sampling rate and input amplitude.
Can I lower Q by “just changing gain K”? What do I lose?
Likely cause: Changing K modifies loop noise-gain and damping, but it also changes headroom, distortion, and sensitivity to op-amp non-idealities; it can trade peaking for amplitude/linearity loss.
Quick check: For the same fc, compare step overshoot and THD/SFDR at the intended swing for two K values; watch for earlier clipping or rising distortion at high output levels.
Fix: Prefer ratio/tolerance control to set Q; use K changes only when the system gain plan can absorb reduced headroom or added distortion, and re-verify stability with real load.
Pass criteria: Peaking/overshoot meets target while passband gain error ≤ X dB and distortion remains better than the system requirement (e.g., THD ≤ X dBFS at swing A).
Why does output clip earlier near the rails in single-supply?
Likely cause: “RRIO” behavior is load- and distortion-dependent; near-rail swing reduces linearity, and Q peaking increases peak amplitude beyond the expected RMS level.
Quick check: Reduce input amplitude by a known margin and check whether distortion/clipping disappears; repeat with different loads to see if the available swing collapses under output current demand.
Fix: Add headroom (raise supply or shift common-mode), lower peaking (reduce Q), reduce load demand (buffer or higher R), and select an op-amp characterized for low distortion near rails under the real load.
Pass criteria: No clipping at the maximum specified signal and load, and distortion stays within budget (e.g., SFDR/THD better than X dBc) over the full output swing range.
HP version: why does the baseline wander / long recovery happen?
Likely cause: Bias/leakage and large time constants shift the HP operating point; overload can drive the op-amp into saturation and cause slow recovery (especially on single-supply).
Quick check: Apply a controlled step or burst and measure return-to-baseline time; repeat while changing bias resistor scale (keeping ratios) to see if recovery is leakage/bias-current dominated.
Fix: Choose a bias network that keeps bias-current errors bounded, avoid saturating the amplifier, and use low-leakage capacitors/clean layout on high-impedance bias nodes.
Pass criteria: Baseline returns within ±X% (or ±X mV) in ≤ T_recover after the worst-case transient, and long-term baseline drift stays below X over the operating window.
Why does increasing resistor values worsen noise and offset?
Likely cause: Higher R increases thermal noise and converts input bias/leakage into offset; high-impedance nodes also become more sensitive to contamination and parasitics.
Quick check: Keep fc/Q the same but scale R down (and C up) by a known factor; compare integrated output noise and DC offset drift under identical conditions.
Fix: Stay within a practical impedance window, use lower Ib/low-noise op-amps when high R is unavoidable, and keep high-impedance bias nodes short/guarded and clean.
Pass criteria: Integrated in-band noise ≤ X_rms and DC error (offset + bias-induced) ≤ X under worst-case temperature and leakage conditions.
How do I quickly verify fc/Q on the bench without a network analyzer?
Likely cause: fc/Q errors usually show up as incorrect -3 dB point, unexpected peaking, or step-response overshoot; these can be captured with simple sweep and time-domain tests.
Quick check: Do a stepped sine sweep (few points per decade around fc) measuring gain ratio, and run a step test to estimate damping from overshoot/settling; repeat 2–3 times for repeatability.
Fix: Calibrate the measurement setup first (probe loading, generator source-Z), then apply trim options (parallel-C or ratio swap) if fc/Q are outside tolerance.
Pass criteria: fc within ±X% of target and Q (or peaking) within ±X% (or ±X dB), with run-to-run variation ≤ X% using the same fixture.
Why does touching the probe change the response?
Likely cause: Probe capacitance and ground lead inductance add parasitic poles/zeros; high-impedance nodes in Sallen-Key are especially sensitive to added C and loop area.
Quick check: Compare (a) standard ground lead vs (b) ground spring, and (c) 10× low-C probe vs a higher-C probe; note changes in fc/peaking to identify the sensitive node.
Fix: Measure at a lower-impedance node when possible, keep probing loop area minimal, and consider a buffered test point if verification must be repeatable.
Pass criteria: Measured fc/Q change ≤ X% between the approved probing method and the production test method, with no false ringing introduced by probing.
When should I abandon Sallen-Key and move to MFB?
Likely cause: The system needs tighter Q control, higher Q, or better robustness under load than Sallen-Key can economically provide (GBW/PM cost, tolerance, or ADC-drive constraints).
Quick check: After applying best practices (NP0/C0G, matched ratios, Riso/buffer, verified op-amp PM under load), check whether fc/Q/settling/THD still miss targets at worst case.
Fix: Move to MFB when Q/peaking and load robustness dominate; keep Sallen-Key for simple LP/HP where low-to-mid Q and cost/complexity are the priority.
Pass criteria: Migration trigger: any two of {fc drift > X%, peaking/overshoot > X, settling > T, distortion worse than X} remain after mitigation; otherwise keep Sallen-Key.
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