The cutoff is not “aligned to one number.” It must satisfy two constraints at once: (1) enough attenuation before fs/2 to reduce PWM ripple and spike energy that can fold into baseband, and (2) minimal phase loss around fc so margin stays safe. If both cannot be met, reduce ripple at the source or increase fs rather than pushing a sharp AAF near fc.

A cleaner plot often means more filtering, and filtering near fc adds delay and phase lag. The loop then reacts to a delayed measurement and can ring or enter limit cycles—even though noise looks lower. The most common trap is stacking an analog low-pass with a digital moving average/IIR, doubling the phase loss. Verify by re-checking phase near fc and step settling after enabling filtering.

Discrete sampling folds energy above fs/2 back into baseband. PWM spikes and ripple can enter the ADC input bandwidth and, after sample/hold, appear as fake low-frequency disturbances that the controller tries to “correct.” This is especially visible when sampling timing drifts relative to PWM edges or when fs is a submultiple of fsw. Confirm by FFT of ADC codes: folding fingerprints track duty/load and fsw.

The goal is stronger stopband attenuation without placing a sharp corner or resonance near fc. Prefer low-Q behavior and avoid narrow peaking. If a 2nd-order response is needed, keep its effective transition away from fc and validate the driver + ADC input stability, because the ADC’s sampling capacitance can create extra poles. Pass/fail should be based on phase near fc and step response, not on “prettier” waveforms.

In most systems, the final RC that defines the ADC input network should be placed as close as practical to the ADC pins, so it absorbs sampling kickback locally and keeps the high-di/dt loop small. However, if the driver is sensitive to capacitive loading, add a small series isolation element at the driver and treat the network as a two-stage stability problem. Verify by checking for ringing/overshoot at the ADC inputs under worst-case sampling conditions.

High-current events can inject spikes that push the AAF/driver into output rails or forward-bias protection paths. The recovery tail behaves like extra delay in the measurement chain, and delay is most damaging around fc. Nonlinear behavior also converts “out-of-band” energy into baseband error. Check the ADC input node for clipping and recovery time, then increase headroom, soften spikes before the amplifier, or re-locate clamp return paths to avoid corrupting the signal node.

A moving average is a delay generator in the control band. At low speed, the loop often operates closer to its phase-margin limits, so added group delay can produce torque ripple and audible whine. If analog AAF already introduces delay, stacking a moving average can push total delay past the safe budget. Before enabling any digital smoothing, re-verify phase near fc and confirm step response does not add ringing or limit cycles.

The usual issue is not “a bit more noise,” but corners shifting: RC tolerance moves the AAF corner, and mismatch unbalances differential paths, converting common-mode disturbance into differential error. Temperature gradients and self-heating can worsen mismatch, and sense-element drift shifts operating points into sensitive regions. Build in quick A/B hooks (bypass or loopback) and compare phase near fc across multiple boards at hot/cold to confirm a tolerance-driven margin collapse.

“Only in certain regions” usually means a coupling path turns on: common-mode swing approaches limits, return currents re-route, or spikes begin to trigger clamp conduction or amplifier slew limits. Start with common-mode range and clamp activity, then inspect ADC-input ringing and return path geometry (Kelvin sense, differential symmetry, and proximity to switching nodes). Validate by correlating the symptom with FFT folding marks and with the presence/absence of clipping.

Sampling timing is part of the measurement chain. If sampling occurs near switch edges, spike energy enters the sample/hold window and increases folding risk; it also changes effective delay and can create duty-dependent artifacts. Define a sampling window that avoids edges and include ADC sample/hold delay + compute/update delay + PWM update delay as one budget. Verify by shifting sampling phase and confirming that baseband FFT artifacts reduce and that phase near fc does not degrade.

Folding signatures typically track switching behavior. If the baseband “disturbance” changes position or strength when fsw, duty, or sampling phase changes, it is likely folded content, not a true plant perturbation. A fast field check is an A/B experiment: tweak AAF corner (or temporarily change fsw) and see whether the baseband lines move or fade predictably. Real low-frequency disturbances stay anchored in frequency and do not follow fsw adjustments.

Yes—two mechanisms matter. Linear parasitics (especially capacitance) reshape the ADC input network and add phase lag, while nonlinear conduction creates clipping and slow recovery tails that behave like extra delay around fc. Decide with measurements: confirm whether the protection is ever near conduction in normal operation, and look for waveform deformation or recovery tails at the ADC input. If issues appear, add isolation, relocate return paths, reduce effective capacitance, or move the clamp away from the precision signal node.