What this page solves: why use an ADC with PGA

Many precision systems combine ultra-small bridge or shunt signals with larger voltage and temperature channels on the same board. If all of these channels share a single ADC, a fixed-gain or gainless front-end often wastes resolution on weak signals or saturates on strong signals. An ADC with a programmable gain amplifier (PGA) is designed specifically to solve this conflict.

Bridges in the tens of microvolts, shunt drops in the millivolt range, and multi-volt sensors can easily span dynamic ranges above 1 000:1. Without programmable gain, low-level channels may occupy only a small fraction of the ADC full-scale range, effectively reducing the usable number of bits. At the same time, using a large fixed gain to recover weak signals risks clipping and distortion for higher-level channels.

Typical pain points without a PGA

• Low-level sensors use only a few LSBs of the converter, so an 18-bit ADC may behave like a 10-bit device in practice.
• One fixed gain cannot satisfy both microvolt-level and multi-volt-level inputs, causing either saturation or poor resolution.
• Multiple sensors with different ranges cannot be mapped cleanly into one ADC full-scale without per-channel gain flexibility.

How a programmable gain front-end solves it

A PGA in front of the ADC allows each channel or measurement range to select a dedicated gain code. Weak bridge or shunt signals can be amplified so that their full-scale spans most of the ADC input range, while higher-level signals use lower gain codes to avoid clipping. Systems can implement per-channel gain settings, multi-range modes (for example 1 A/10 A/100 A), or automatic ranging that adapts gain based on measured amplitude.

This section focuses only on the need for an ADC with PGA and the system-level problem it solves. Detailed MUX behaviour, crosstalk and specific SAR or ΣΔ core architectures are discussed on their dedicated pages.

Architecture basics: how ADC and PGA work together

An ADC with PGA combines a programmable gain front-end with a conversion core such as a SAR or sigma-delta modulator. Depending on the device family, the PGA may drive a SAR sampling network, a ΣΔ modulator input, or sit behind a multi-channel MUX that shares a single gain stage and converter core. Understanding these high-level topologies helps match the device to the target application.

Differential PGA in front of a SAR core

Many industrial ADCs use a fully differential PGA at the input. The PGA provides gain selection and common-mode level shifting, and its output drives the SAR sampling capacitors. Higher gain codes increase the closed-loop gain and the drive requirements into the sampling network, which affects bandwidth and settling. The SAR core itself behaves like a conventional successive-approximation converter behind the PGA.

Programmable gain front-end with ΣΔ modulator

High-resolution weigh-scale and metering ADCs often integrate an instrumentation-style amplifier in front of a sigma-delta modulator. The PGA presents a high-impedance, high-CMRR interface to bridge and low-frequency sensors, then maps the small differential signal into the modulator input range. Oversampling, noise shaping and on-chip digital filtering are handled by the ΣΔ core, while the PGA determines how effectively microvolt-level signals occupy that input range.

MUX plus shared PGA and converter

Some converters place an analog multiplexer in front of a single PGA and ADC core. Multiple channels can be connected to one high-performance front-end with per-channel or shared gain settings. This approach reduces cost and silicon area, but introduces sequential sampling and shared analog resources between channels. Detailed MUX crosstalk and settling behaviour is handled on the dedicated MUXed SAR ADC page.

Typical PGA implementation styles

Internally, gain selection is usually implemented with switched resistor networks, switched-capacitor arrays, or instrumentation-amplifier structures. Gain codes in a control register select discrete gain ratios such as 1x, 2x, 4x, 8x, and 16x. Changing gain modifies both the signal gain and the internal noise and bandwidth characteristics; later sections analyse these trade-offs in detail.

This section concentrates on high-level topology. Pipeline stage details, SAR bit cycling, sigma-delta noise shaping and MUX layout optimisation are discussed under the corresponding architecture and front-end pages.

Gain range & dynamic range planning

A programmable gain front-end is only effective when its gain codes are planned against sensor output ranges and the ADC full-scale range. The goal is to map each input range so that it occupies a meaningful portion of the converter span, without clipping, and with enough overlap between ranges to support calibration and seamless switching.

Key definitions: input range, full-scale and utilisation

A sensor exposes an input range, for example 0 to 20 mV or ±20 mV. The ADC specifies an input full-scale range V_FS, such as ±2.5 V differential (5 V span) or 0 to V_REF. For an N-bit converter, the code width or LSB size is LSB = V_FS / 2^N. If a sensor only uses a small fraction of V_FS, many codes are never exercised and the effective resolution is lower than the nominal bit count.

Full-scale utilisation can be expressed as U = V_signal,max / V_FS. When U is only 10 %, the number of effectively used bits is reduced by roughly three bits. As a result, an 18-bit ADC can behave closer to a 15-bit converter in practice if the signal uses only one-tenth of the full-scale span.

Single-range example: 0–20 mV into a ±2.5 V, 18-bit ADC

Consider a bridge sensor with 0 to 20 mV full-scale and an 18-bit ADC with a ±2.5 V input range (5 V span). With gain = 1, the utilisation is U = 20 mV / 5 V = 0.4 %. Only a small fraction of the available codes represent the bridge signal, and the effective resolution is close to 11–12 bits instead of 18 bits.

Introducing a programmable gain G improves utilisation. A practical design target is to map the maximum sensor output to 80–90 % of V_FS, leaving headroom for offsets and excursions. For the 20 mV bridge and 5 V full-scale, the ideal gain is roughly: G_ideal ≈ 0.8 × 5 V / 20 mV ≈ 200. In practice, only discrete gain codes are offered, such as 1, 2, 4, 8, 16, 32, 64 or 128. A gain of 128 maps 20 mV to about 2.56 V, or around half of the 5 V span, already a large improvement compared to 0.4 %.

The same method applies to other ranges: estimate the maximum sensor amplitude including offset and tolerance, compute a target gain from V_FS, then choose the closest supported gain code that keeps the signal away from clipping while using a significant fraction of the span.

Multi-range planning and overlap for 1 A / 10 A / 100 A

Many current-measurement front-ends must support several ranges such as 1 A, 10 A and 100 A. Shunt values or sensing methods are usually selected so that each range produces a similar maximum shunt voltage, for example 40 mV at full-scale current. A PGA with multiple gain codes can then align all three ranges with the ADC span: a high gain (such as 128) for the 1 A range, a medium gain (for example 16) for the 10 A range, and a gain of 1 for the 100 A range.

Ranges should not meet exactly at the nominal boundary. A deliberate overlap zone allows both ranges to measure the same current, which simplifies calibration and enables smooth transitions. For instance, the 1 A range could be considered valid up to 0.8 A, while the 10 A range remains accurate down to 0.5 A. Both ranges can then be compared and cross-calibrated in the overlap region before the firmware commits to a range change.

Gain matrices for multi-sensor systems

When several sensors share the same ADC, a gain matrix is useful. Rows represent sensors such as Bridge 1, Bridge 2, Shunt, Voltage and RTD; columns correspond to gain codes such as 1x, 2x, 4x, 8x and 16x. Each cell notes the resulting full-scale ADC voltage for that sensor and gain. Combinations that use less than 20 % of the ADC span or approach hard clipping can be excluded, leaving a shortlist of recommended gain settings per sensor and per range.

This section focuses on low-frequency and industrial measurement front-ends. RF-sampling and IF-sampling dynamic range planning is handled by the corresponding ADC architecture pages.

Noise, bandwidth and settling with a PGA front-end

Gain settings in a PGA affect not only the signal amplitude but also noise, bandwidth and settling behaviour. Higher gain codes improve the mapping of small signals into the ADC span, yet also change the closed-loop bandwidth, noise gain and the time required for the output to stabilise after a step or gain change. These effects must be considered alongside the dynamic range plan.

Noise sources and the difference between signal gain and noise gain

The noise at the ADC input comes from several contributors: the input amplifier voltage and current noise, the thermal noise of resistors or switched-capacitor networks, the ADC core quantisation noise and the sensor itself. In many PGA topologies, the closed-loop gain for noise is different from the gain applied to the external signal. For example, an amplifier may see a noise gain of 1 + R_f/R_in even when the signal path gain appears lower.

Output noise tends to increase with gain, because both the input-referred noise and the ADC noise are amplified. However, when noise is referred back to the sensor input, a suitable gain setting can reduce the relative contribution of the ADC core noise. In practice, a moderate-to-high gain often provides a good trade-off: small signals occupy more of the span and the ADC noise becomes less dominant, while the total input-referred noise remains compatible with the application budget.

Gain versus bandwidth and stability

For a finite-GBW amplifier, the closed-loop bandwidth decreases as the closed-loop gain increases. A simplified relation is f_BW ≈ GBW / G_CL, where GBW is the gain-bandwidth product and G_CL is the closed-loop gain. High gain codes therefore limit the usable signal bandwidth and reduce phase margin if the amplifier is not compensated for the configuration.

The application bandwidth and the PGA bandwidth have to match. A common guideline is to design the closed-loop bandwidth to be at least five to ten times the highest useful signal frequency. For SAR ADCs, the front-end must also drive the sampling capacitors and switch network. If the bandwidth is too low at a given gain, sampled amplitudes will be attenuated, edges will be rounded and distortion will increase, particularly near the top of the passband.

Settling after steps and gain changes

When the input signal steps or when the gain code changes, the PGA output exhibits a transient before reaching a new steady value. For SAR converters, the combination of amplifier output resistance, switch resistance and sampling capacitance forms an effective RC network. The output must settle to within a fraction of an LSB, often 0.5 LSB, before the sampling instant to avoid conversion error.

Gain changes introduce additional steps because the closed-loop gain and sometimes the output common-mode change abruptly. Many data sheets specify a settling time after a gain change or after a channel change. For sigma-delta converters, the digital filter adds group delay, so several output codes after a gain update must be discarded before the data reflects the new setting. The number of discard samples depends on the oversampling ratio and filter type.

Data sheet parameters to review

Several data sheet sections are especially important for PGA operation: noise (rms or peak-to-peak, often per gain code and bandwidth), small-signal bandwidth and full-power bandwidth, step response to a given error band, and settling time after gain or channel changes. For sigma-delta ADCs, conversion latency, filter group delay and the number of valid conversions after configuration changes are equally important. These parameters together determine whether a target gain setting is feasible for the required bandwidth and timing.

System-level EMI and external filtering are covered in the dedicated driver and anti-alias filter sections. This part focuses on the local analogue behaviour of the PGA and ADC core around gain, bandwidth and settling.

Input formats & common-mode: interfaces and protection

An ADC with a programmable gain amplifier accepts different input formats and common-mode levels, while its internal amplifier and converter core tolerate only a limited input window. Correctly mapping single-ended, pseudo-differential and fully differential sources into the allowed common-mode range, and applying protection without degrading linearity, is essential for reliable operation.

Single-ended, pseudo-differential and fully differential inputs

Single-ended inputs drive one ADC pin with respect to a reference node such as ground or a local reference point. This configuration suits voltage-output sensors, divider networks and buffered signals. Pseudo-differential inputs still treat one pin as the signal and the other as a quiet reference, but use two pins to gain some immunity against ground noise. Fully differential inputs accept a true differential signal between IN+ and IN− and are preferred for bridge sensors, differential shunts and precision differential drivers where common-mode disturbances must be rejected.

Many ADCs with PGA can operate in more than one mode. Some devices support fully differential inputs only, while others offer configurations where single-ended or pseudo-differential sources are converted to a suitable internal differential representation. Input configuration and allowed ranges are usually documented explicitly and must be checked before a new sensor interface is designed.

Typical sensor interfaces and input mapping

Bridge sensors for pressure and weight produce a differential signal centred around a common-mode near the bridge excitation voltage. These sensors naturally match fully differential ADC inputs, where IN+ and IN− connect to the opposite bridge nodes and the ADC reference may track the excitation for ratiometric measurements. Shunt resistors used for current sensing can be connected in low-side or high-side configurations; low-side shunts often allow single-ended or pseudo-differential coupling, whereas high-side shunts usually require an external amplifier to shift the common-mode into the ADC range.

RTDs and NTC thermistors are measured via excitation and sense networks that may present either a single-ended voltage or a small differential signal. The choice between single-ended, pseudo-differential and fully differential operation depends on the wiring length, expected interference and how closely the sensor common-mode matches the ADC input common-mode window at the intended gain settings.

Common-mode range and gain-dependent limits

ADC data sheets usually specify an input common-mode range VIN_CM as a function of supply rails and reference voltage. Some devices show a graph of VIN_CM versus differential input voltage or gain code; others provide tables listing the minimum and maximum permissible common-mode levels for each gain setting. Operating outside this window forces internal amplifier nodes into saturation even when the differential voltage remains within the nominal full-scale range.

At low gain, the PGA sees smaller internal swings, so the allowed common-mode range is usually wider and may extend closer to the rails. At higher gain, a modest shift in VIN_CM produces larger internal voltage changes, reducing headroom and narrowing the permissible common-mode band. For architectures that centre the input around a fraction of VREF, the valid common-mode region may move with VREF as well, which must be considered when programmable references are used.

Protection networks and linearity with a PGA front-end

Input protection typically combines series resistors, RC filters, TVS diodes and the ADC’s own ESD structures. Series resistors limit surge currents into the device and, together with the sampling network, form an RC time constant that influences bandwidth and settling. Excessive series resistance degrades dynamic performance and may prevent the PGA from charging internal sampling capacitors within the allowed acquisition time, especially at high gain.

External clamping and TVS devices introduce leakage currents and non-linear capacitance. In low-level, high-gain modes, these effects can distort measurements, shift common-mode voltages and reduce CMRR if the protection is not symmetrical between the differential inputs. A balanced protection network placed between the sensor and PGA, with low-leakage components and moderate resistance values, offers effective protection while keeping distortion and noise within budget.

Detailed shunt and bridge front-end design, including excitation and bridge balancing, is covered on the dedicated front-end pages. This section focuses on input formats, common-mode limits and compatible protection strategies for ADCs with PGA.

System gain planning: sensor to PGA to ADC

Many precision systems include more than one gain stage between the sensor and the ADC with PGA. The sensor signal may pass through protection, external amplification and filtering before reaching the on-chip PGA and converter core. Gain must be distributed so that the stages closest to the ADC provide most of the amplification, while earlier stages operate within a comfortable linear range and do not dominate the noise.

Signal chain from sensor to digital codes

A typical chain can be represented as: Sensor → protection and filtering → optional external amplifier → on-chip PGA → ADC core → digital processing. Each block contributes its own gain, bandwidth, noise and saturation limit. System gain planning ensures that the combination maps the smallest and largest expected sensor values into the ADC’s full-scale range without overdriving intermediate stages or wasting resolution.

A practical guideline is to allow the stages nearest to the ADC to carry most of the total gain. Internal PGAs and differential front-ends are usually optimised for noise, linearity and matching to the converter core. External amplifiers are then primarily used to provide level shifting, common-mode translation, isolation or drive capability, with moderate gain rather than very high gain.

Preventing sensor and external amplifier saturation

Each element in the chain has a finite linear range. Sensors exhibit their own linear operating region, such as strain limits for bridges or current and temperature limits for shunts. External amplifiers are constrained by input common-mode ranges, output swing relative to the rails and gain-bandwidth product. Gain planning must keep the maximum expected signal and any common-mode variation within these limits with adequate headroom.

In many designs, front-end amplifiers are configured with modest gains that prevent them from approaching saturation over the worst-case sensor and common-mode range. The on-chip PGA then performs the final mapping of the conditioned signal into the ADC span. This arrangement reduces the risk that the external amplifier clips before the ADC input reaches its full-scale, and simplifies stability and bandwidth design for the external stage.

Coordinating VREF and PGA for range and resolution

In many ADCs, the full-scale range is proportional to the reference voltage. A higher reference increases the maximum measurable voltage but also enlarges the LSB size, while a lower reference reduces the LSB size and tightens the usable range. When the ADC offers a programmable reference, VREF becomes another gain control in addition to the PGA.

A common strategy is to use the reference for coarse range selection and the PGA for fine adjustment. Large-signal ranges can operate with a higher reference and lower PGA gain, while small-signal precision ranges use a lower reference and higher PGA gain. Reference noise and stability must be considered as part of the overall noise budget; using the smallest possible reference without regard to its noise performance may not improve accuracy.

Example gain distributions: external gain vs internal PGA gain

Consider a sensor that produces 0 to 10 mV and an ADC with a ±2.048 V input range. One design may use an external amplifier with gain of 10, producing 0 to 100 mV, followed by a modest PGA gain. Another design may use an external gain near unity to handle common-mode translation and rely on a higher internal PGA gain to reach the same ADC full-scale region. In the second case, the external amplifier operates with more headroom and contributes less noise when referred to the sensor input, while the internal PGA applies most of the amplification under controlled conditions.

Comparing alternative gain splits helps identify which stage should carry more gain to minimise noise, avoid saturation and simplify stability. In many precision applications, assigning only modest gain to the external amplifier and reserving the higher, programmable gain for the on-chip PGA provides the best compromise between dynamic range and robustness.

Power supplies, isolation and multi-card synchronisation are addressed in the design hooks and system integration sections. This part focuses on how gain and reference settings are distributed along the sensor-to-ADC signal path.

Application patterns for ADCs with PGA

An ADC with a programmable gain amplifier can support a wide range of applications by mapping different sensor ranges into the converter full-scale span. Typical patterns include bridge and load-cell measurements, multi-range current sensing and multi-sensor systems where pressure, temperature and position channels share the same ADC. In all cases, the PGA gain codes define how each range is represented and how auto-ranging strategies are implemented in firmware.

Overview: using the PGA to map ranges

Across applications, the role of the PGA is consistent. Gain codes are used to map each sensor range to a suitable portion of the ADC full-scale, to define multiple measurement ranges on the same hardware and to provide the steps needed for auto-range decisions. The device does not impose a specific application; instead, gain and range planning create reusable circuit templates for bridge sensors, current shunts and mixed sensor systems.

Pattern 1: bridge and load-cell measurements with ΣΔ + PGA

Load cells and pressure bridges generate small differential voltages centred around a common-mode close to the bridge excitation. A sigma-delta ADC with an integrated PGA is a common choice because the modulator and digital filter deliver high resolution at low bandwidth. The bridge connects directly to the differential inputs, while the PGA adjusts the effective range. For a multi-range scale, smaller weight ranges use higher gain codes, and larger ranges use lower gain codes so that each range utilises a significant fraction of the converter span without clipping.

For example, a 10 kg range may operate with a gain of 128 or 256 so the full-scale weight maps close to the ADC full-scale, while a 100 kg range uses gain values such as 16 or 32 on the same bridge. Overlap regions where both ranges remain valid allow cross-calibration and smooth range transitions. The sigma-delta digital filter latency defines how many conversion results must be discarded after a gain or range change before new readings are considered valid.

Pattern 2: multi-range shunt current sensing with SAR + PGA

Current measurement often relies on shunt resistors that produce millivolt-level signals proportional to the line current. A SAR ADC with a PGA provides low-latency conversions and flexible range settings for motor control, power supplies and protection. In low-side configurations, the shunt voltage can be sensed directly in single-ended or differential mode, and PGA gain codes map 1 A, 10 A and 100 A ranges onto the ADC span by combining shunt values and gain settings.

High-side shunts usually require an external differential amplifier to translate the high common-mode down to the PCA input range. In this pattern, the external amplifier applies modest gain to maintain headroom, while the internal PGA provides the programmable range selection. Multiple current ranges can be implemented by combining shunt values, external amplifier gains and PGA codes, with overlap regions reserved for cross-checking current scales and verifying calibration.

Pattern 3: multi-sensor systems sharing one ADC with PGA

Many industrial and instrumentation nodes combine several sensors, such as pressure, temperature and position, onto a single ADC. A multiplexer selects the active channel, and the PGA is reconfigured per channel before each conversion or conversion group. Each sensor type is associated with a default gain code and optionally several range-dependent gain codes, forming a gain map indexed by channel number and desired range.

When the multiplexer switches from one sensor to another, the firmware writes the corresponding gain code, waits for analogue settling and discards a number of samples as required by the ADC data sheet. Channels with low-level signals such as bridges or RTDs use high gain codes, while buffered 0–2 V or 0–5 V sensors operate with low gain or unity gain. The gain map and scheduling logic together define how the shared ADC supports heterogeneous sensors without compromising resolution or speed.

Auto-range strategies based on PGA gain codes

Auto-ranging relies on fixed or adaptive thresholds applied to the measured code. When a reading in a high-gain range approaches a predefined upper threshold, the firmware selects a lower gain range, applies the new gain code, waits for settling and then resumes measurement. Hysteresis between the up-range and down-range thresholds prevents chattering when the signal hovers near the decision level. Historical data or filters in the digital domain smooth the transition so that plotted values or control loops do not show abrupt steps when gain changes occur.

Detailed design of weighing, power, motor control and other application systems is handled on the dedicated application pages. This section focuses on reusable patterns showing how PGA gain codes map sensor ranges into the ADC span.

PCB, reference and digital behaviour with PGA gain changes

Variable-gain operation places additional demands on PCB layout, reference routing and digital control compared to fixed gain converters. High gain codes magnify small disturbances at the inputs and reference pins, and repeated gain changes require coordinated firmware actions to maintain accuracy. Layout, reference design and digital sequencing should be planned together with the PGA gain strategy.

Layout considerations for high-gain operation

When high PGA gain codes are used, small voltages at the inputs are amplified to occupy most of the ADC span. Any coupling from digital lines, power stages or other analogue channels into the input traces is also magnified. Differential input traces benefit from close coupling, length matching and a solid reference plane beneath the sensitive region. Return currents should flow in a short, direct path underneath the input pair rather than through large loops.

Guard rings and local shields around high-impedance, high-gain nodes help reduce leakage and capacitive coupling. High-current and high dv/dt traces such as switching nodes, digital clocks and communication lines should be routed away from the front-end region. The channels that use the highest gain codes deserve the most conservative routing and spacing, because their effective noise and interference margin is smallest.

Reference and supply interactions with variable gain

The ADC reference defines the full-scale range and directly influences noise and linearity. High gain operation and large input swings can increase the dynamic loading on internal sampling capacitors driven from VREF or internal bias nodes. Reference buffers must supply these transient currents without excessive droop or ringing. The reference routing should avoid coupling from fast digital edges and power switching nodes to maintain a stable conversion baseline.

Many ADCs specify PSRR and CMRR versus gain. These parameters may degrade at higher gains, making the system more sensitive to supply and reference ripple. Local decoupling capacitors placed close to the reference and supply pins, and a star-like reference connection with a short route to the ADC, help maintain consistent performance across gain codes. Reference selection and PCB implementation together determine how much of the theoretical resolution is usable in high-gain modes.

Digital control and sample discarding after gain changes

Changing the PGA gain code or input channel introduces analogue and, for sigma-delta converters, digital transients. Firmware should update configuration registers, wait for the analogue front-end to settle and discard a number of conversions before using new data. The required discard count depends on the ADC architecture, oversampling ratio and the magnitude of the gain and input step.

In single-channel SAR systems, the settling time is often a small multiple of the conversion period and only a few samples need to be ignored. Sigma-delta ADCs include digital filters whose group delay can span many output samples; data sheets typically recommend how many conversions must be discarded after a gain or filter change. For multi-channel systems, each channel and gain combination can be assigned a dedicated dummy-sample count so that the firmware state machine applies the correct settling delay for each step in the scan.

Gain code and dummy-sample planning

A practical implementation associates each gain code with recommended dummy-sample counts for SAR and sigma-delta modes. Lower gain settings may require only one or two discarded samples, while higher gains or large input steps need more conversions before the output reflects the new operating point. Combining this information with the scan schedule and auto-range algorithm ensures that gain changes do not introduce hidden errors or distortions into measurement or control loops.

General mixed-signal layout practices, detailed reference design and system-level timing are discussed in the broader design hook sections. This part highlights the additional considerations introduced by variable PGA gain and gain switching.

BOM & IC selection checklist for ADCs with PGA

When an ADC includes a programmable gain amplifier, the device behaves as both a converter and a precision front end. The bill-of-materials and sourcing checklist therefore needs additional fields beyond those used for standard ADCs. The following checklist focuses on architecture, PGA parameters, input structure, reference options and grading that are specific to ADCs with PGA and can be copied directly into engineering spreadsheets and RFQs.

Field overview: what matters for ADCs with PGA

For ADCs that integrate a PGA, the selection checklist can be grouped into six field categories:

• Architecture & performance level: ADC architecture (SAR / sigma-delta / hybrid), nominal resolution (bits), sample rate and effective data rate at the target bandwidth.
• PGA behaviour: gain codes, minimum and maximum gain, gain error and drift, noise and ENOB versus gain setting.
• Input structure & common-mode: input type (differential / pseudo-differential / single-ended), common-mode range versus gain and reference, overvoltage limits.
• Channels & per-channel gain: number of channels, multiplexer organisation, per-channel gain capability, conversion sequencing.
• Supply & reference: AVDD/DVDD ranges, power consumption at target settings, reference options (internal / external / programmable).
• Package & grade: package type and size, operating temperature range, industrial or automotive qualification.

Architecture, resolution and sampling fields

Architecture determines whether the device is better suited for low-latency control loops, high-resolution low-bandwidth measurements or mixed requirements. For the BOM and RFQ, the architecture field should capture:

• ADC architecture: SAR / sigma-delta / hybrid.
• Resolution (bits): nominal resolution of the converter core.
• ENOB at target conditions: effective number of bits at the intended bandwidth, gain and data-rate settings.

Sampling fields describe how fast the system can acquire usable data rather than only the maximum theoretical sample rate. For SAR devices, the key numbers are the maximum conversion rate and any limitations imposed by acquisition time at high gains. For sigma-delta ADCs, the checklist should distinguish between modulator clock, oversampling ratio and output data rate, and relate ENOB to the chosen filter configuration. Including the target bandwidth and data rate in RFQs helps suppliers match parts and provide realistic performance estimates.

PGA gain range, error and noise fields

The integrated PGA is often the main reason to select a specific ADC. The checklist therefore needs dedicated fields for gain coding, accuracy and noise:

• PGA gain codes: list of supported gains (for example 1, 2, 4, 8, 16, 32, 64, 128).
• Minimum / maximum gain: lowest and highest usable gain, including any restrictions at the extreme codes.
• Gain error: gain error for each code, in percent or LSB, with test conditions.
• Gain drift: gain temperature coefficient in ppm/°C, especially important for weighing and metering.
• Noise / ENOB versus gain: input-referred noise or ENOB as a function of gain and bandwidth.

Including these fields allows direct comparison of devices when the same sensor and range planning are applied. For precision applications, RFQs can explicitly request tables or plots of input-referred noise and ENOB versus gain for the target bandwidth, so that PGA settings can be chosen with full visibility of the resulting resolution.

Input formats, common-mode window and protection fields

The input structure and common-mode window determine whether a bridge, shunt or buffered voltage can connect directly to the ADC or requires additional conditioning. The checklist should include:

• Input type: differential / pseudo-differential / single-ended.
• Number of true differential channels: and how many can use the PGA.
• Input common-mode range: VIN_CM versus AVDD/VREF and gain, with minimum and maximum limits.
• Absolute maximum ratings: maximum voltages on input pins and any internal protection structures.

For many converters, the allowed common-mode range narrows at higher PGA gains even though the differential full-scale remains constant. RFQs benefit from including the expected sensor common-mode range and intended gain codes so that component vendors can confirm that the operating point stays within the specified window across voltage and temperature.

Channel count, per-channel gain and interface fields

Systems that combine multiple sensor types on one ADC with PGA need clarity on channel organisation and gain control. Useful fields include:

• Channel count: total channels and differential pairs.
• Multiplexer structure: internal MUX topology for single-ended and differential inputs.
• Per-channel gain: whether each channel can have an independent gain code or the PGA setting is global.
• Interface type: SPI / I²C / other serial interfaces and maximum clock rate.
• Conversion latency: SAR conversion time or sigma-delta group delay at the target filter settings.

For multi-sensor designs, RFQs can also state expected scan patterns, such as the number of channels, desired per-channel gain codes and effective sample rate per channel. This allows suppliers to confirm that interface bandwidth and conversion latency are sufficient for the planned auto-range and control algorithms.

Supply, reference and grading fields

Power and reference fields capture how the ADC with PGA fits into the wider analogue front-end and system rails:

• AVDD / DVDD ranges: analogue and digital supply ranges and separation options.
• Power consumption: typical current at the target sample rate and PGA settings, including low-power modes.
• Reference options: internal reference availability, accuracy and drift; external reference input range; any programmable reference levels.
• Package and size: package type, pin count and footprint dimensions.
• Temperature and qualification: operating temperature range and industrial or automotive grades.

When these fields are present in the BOM and RFQ, it becomes straightforward to filter candidate devices by rail compatibility, thermal environment and assembly constraints before comparing detailed noise and PGA behaviour.

Selection priorities: noise, cost and speed

Different applications apply different weighting to the same checklist. For noise- and accuracy-driven systems such as weighing scales or precision metering, the top priorities are ENOB, noise versus gain, gain drift and stability of the reference at the chosen operating point. Cost-sensitive platforms can accept a smaller set of gain codes and modest noise performance in exchange for lower price, small packages and high channel density.

For fast control loops in motor drives and power supplies, low latency and deterministic timing from the ADC with PGA are often more important than maximum resolutions. SAR architectures with modest gain ranges and well-documented settling behaviour can be preferred here, provided that noise performance at the chosen gains meets control-loop requirements. Stating the primary priority—noise, cost or speed—in the RFQ helps suppliers propose appropriate device families and highlight relevant trade-offs.

Example ADCs with PGA from major vendors

The checklist applies across manufacturers. The following examples show typical ADCs with integrated PGA from several major vendors, together with their broad positioning:

These examples illustrate how the same checklist can be applied to different vendor families. The actual choice depends on the required architecture, gain range, noise level, channel count, interface and qualification for each project.

Recommended topics you might also need

• DC / Low-Frequency Precision
• Ultra-High Resolution (24–32 bit ΣΔ)
• Precision Instrumentation
• Shunt/Bridge Front-Ends
• Reference & Buffering

FAQs: ADCs with Programmable Gain Amplifiers (PGA)

This FAQ section aggregates long-tail questions around ADCs with integrated programmable gain amplifiers, including architecture choice, gain planning, noise and linearity, layout and grounding, debug flows, production calibration and long-term drift. Each answer focuses on practical engineering decisions and checks that can be applied directly in real designs.

How to choose between a sigma-delta ADC with PGA and a SAR ADC with PGA?

A sigma-delta ADC with an integrated PGA is better suited to low-bandwidth applications that demand very high resolution and low noise, such as weighing scales, energy metering and precision temperature or pressure sensing. These devices rely on oversampling and digital filtering, so they offer high ENOB within a narrow bandwidth at the expense of conversion latency.

A SAR ADC with PGA is usually preferred in systems that require medium to high sampling rates and low latency, such as motor control, power-supply loops, current protection and fast data acquisition. The conversion delay is close to a single conversion period, which simplifies timing and control-loop design.

The choice can be guided by three main factors: required signal bandwidth and acceptable group delay, effective resolution at that bandwidth, and how often the PGA gain needs to switch. For DC and low-frequency precision, a sigma-delta with PGA is usually more appropriate; for fast response and deterministic timing, a SAR with PGA is typically the better fit.

What are the pros and cons of an ADC with integrated PGA versus an external amplifier plus standard ADC?

An ADC with an integrated PGA typically offers better internal matching of gain, offset and temperature drift, and the high-impedance small-signal path is kept short on the PCB. This improves noise immunity and common-mode rejection. Gain switching is performed through digital registers, with well-controlled repeatability for multi-range and auto-range use cases.

An external amplifier plus standard ADC provides more freedom to choose amplifiers with specific bandwidth, noise or common-mode range characteristics. Complex filtering, isolation and protection networks can be implemented in the analogue front end without being constrained by the internal PGA architecture.

When dynamic range and small-signal precision are the primary challenges, an ADC with integrated PGA is often more efficient. When the front end must handle demanding protection, isolation or wide common-mode conditions, an external amplifier with a suitable fixed-gain ADC may be preferable, with the integrated PGA treated as an optional feature.

How should PGA gain ranges be defined to balance dynamic range and resolution?

A practical rule of thumb is to plan each measurement range so that the maximum expected signal occupies roughly 60–90 % of the ADC full-scale span at the chosen gain. This avoids constant clipping while keeping most of the converter codes in use, rather than leaving signals at only a small fraction of full scale.

Neighbouring gain ranges should have overlapping regions, often 5–10 % of full scale, to allow smooth transitions and cross-calibration. For each sensor or shunt range, the minimum and maximum input voltages can be multiplied by candidate gain codes to see which combinations best fill the ADC range without violating common-mode limits.

The resulting gain table can then be used by firmware to select the appropriate range for each sensor, balancing the need for fine resolution in low ranges with sufficient headroom in higher ranges that must handle large signals.

Does auto-ranging with the PGA risk destabilising control loops, and how should gain switching be handled?

Auto-ranging changes the mapping between the physical quantity and the ADC code, but it does not change the physical process itself. If the control algorithm always operates on calibrated physical units, a gain change should not cause a true step in the controlled variable. The main risks are apparent jumps in measured code and short periods where samples are discarded during gain transitions.

For display or logging channels, auto-ranging is usually acceptable when combined with hysteresis and averaging across the transition. For control-critical channels, many designs either fix the gain or restrict gain changes to defined operating modes, and always perform gain changes together with an update of scaling factors and a short settling period.

In all cases, firmware should implement upper and lower thresholds with hysteresis, discard a defined number of samples after each gain change, and apply filtering to prevent auto-ranging from appearing as a disturbance in plots or control loops.

Why can THD or SFDR become worse at high PGA gains?

Higher PGA gains push the internal amplifier stages closer to their linearity limits for a given input level. Any residual nonlinearity in the front end is magnified, and the output waveform at high gains may exhibit more distortion even if the ADC core has not changed. Data sheets often show THD or SFDR curves that degrade as gain and signal level increase.

External factors such as source impedance, limited drive capability or insufficient headroom in the input signal path can also contribute. High gain settings expose these limitations because the amplified signal occupies more of the ADC full-scale range, and small asymmetries become more visible in the spectrum.

When stringent THD or SFDR is required, it is usually better to operate in moderate gain settings and adjust the sensor range or external scaling accordingly, reserving the highest gains for low-frequency or quasi-DC measurements where harmonic distortion is less critical.

Is higher noise at high PGA gains normal, or does it indicate layout or device problems?

Some increase in output noise with gain is normal, because both signal and noise are amplified. Data sheets usually provide input-referred noise or ENOB versus gain and bandwidth, which can be used as the reference behaviour. If measured noise at high gain matches the expected trend within a reasonable margin, the device and layout are likely operating correctly.

When measured noise at high gains is significantly above the data sheet values, the excess often comes from external coupling or grounding issues. High-gain settings are more sensitive to digital switching noise, reference ripple and leakage currents. Shorting the inputs or connecting them to a quiet mid-scale point and repeating the measurement helps separate intrinsic ADC noise from system-level interference.

If multiple boards show similar excess noise in the same conditions, the root cause is likely structural (layout, grounding or reference design) rather than a single faulty device.

Why do readings differ between PGA gain settings for the same signal, and how can this be calibrated?

Differences between readings at different PGA gains for the same physical input are usually caused by per-gain gain error and offset, not by a fundamental ADC defect. Each gain code has its own small deviations from the ideal value, and these deviations appear as slightly different scaled results once readings are converted back to physical units.

A practical approach is to perform calibration per gain code. For each relevant gain, the system can measure known reference points (for example, zero and one or two non-zero levels) and compute gain and offset coefficients. These coefficients are then applied in firmware so that all gain codes map to a consistent physical-unit scale.

In multi-range systems, shared overlap regions between ranges allow cross-checking and fine-tuning of these coefficients, ensuring that auto-range transitions do not introduce visible steps in the calibrated reading.

After PCB assembly, the high-gain range is always saturated. What debug sequence is recommended?

A structured debug sequence starts with configuration checks. Verify that the PGA gain, input selection, polarity and reference settings match the intended design. Next, confirm from the data sheet that the sensor common-mode voltage and planned gain code fall within the allowed input common-mode window for that device.

The next step is to measure the actual voltages at the ADC input pins using a multimeter or oscilloscope. This identifies any offset from bias networks, sensor faults, leakage or incorrect component values that could push the inputs beyond the ADC full-scale range when amplified. Solder bridges, opens and swapped connections in the high impedance path should also be checked.

If lower gain settings behave normally while only high-gain modes saturate, common causes are out-of-range common mode, incorrect reference selection or cumulative offsets that become large when multiplied by the PGA gain. These issues should be resolved before suspecting a damaged ADC.

Can the internal PGA of an ADC be used as a general-purpose operational amplifier?

In most devices, the internal PGA is not intended to be used as a general-purpose operational amplifier. It is optimised to drive the internal sampling capacitors or modulator of the ADC and may not have a dedicated output pin, specified output drive capability or stable behaviour with arbitrary external loads.

Using the internal PGA outside its specified signal path can lead to instability, unknown slew limitations or violations of the device’s internal biasing. Only when a data sheet explicitly documents an amplifier function with its own specifications and pins should it be treated as a general-purpose op amp.

For buffering, filtering or comparator functions, a separate amplifier designed and specified for those tasks is the recommended solution. The ADC’s PGA should be reserved for its intended role in the conversion chain.

How should gain and offset be calibrated across channels and gain codes in a multi-channel ADC with PGA?

Calibration can be organised in two layers: channel-to-channel matching and per-gain-code correction. A common approach is to perform offset calibration on each channel using a zero input condition, followed by gain calibration on a selected mid-range gain code with a known reference level.

For detailed gain-code calibration, at least one representative channel can be calibrated across all gain codes to derive relative correction factors. Other channels can then rely on the combination of their absolute mid-gain calibration and the shared relative gain-code factors, reducing total production test time while still achieving good alignment.

The resulting calibration constants are typically stored per channel and per gain code in non-volatile memory and applied whenever readings are converted to physical units. This ensures consistent results even when auto-ranging switches between channels and gain settings.

How do gain and offset drift over temperature and time affect an ADC with PGA, and how should this influence selection?

Total drift in a PGA-based ADC comes from several contributors: reference drift, internal PGA gain drift and ADC offset and gain drift. Data sheets typically specify gain drift in ppm/°C and offset drift in μV/°C, and some devices also provide long-term drift data over thousands of hours.

For precision weighing, metering or instrumentation, these drift terms can accumulate into noticeable scale changes over temperature and lifetime. Selection should therefore consider both initial accuracy and drift specifications, and the system design should include provisions for periodic recalibration or temperature-based compensation tables.

An approximate error budget can be built by multiplying the specified drift by the expected temperature range and comparing the result against allowable system error. Devices whose drift overwhelms this budget are not suitable, even if their room-temperature performance appears adequate.

When is it better to use an external preamplifier with a fixed-gain ADC instead of a high-gain ADC with PGA?

An external preamplifier combined with a fixed-gain ADC is advantageous when the front end must provide complex filtering, isolation, protection or extreme common-mode handling that an integrated PGA cannot support. Dedicated amplifiers can be chosen for high bandwidth, special input ranges or low-distortion performance that exceeds the capabilities of the internal PGA.

A high-gain ADC with PGA is most efficient when the main challenge is dynamic range management for small sensor signals on a relatively clean board. The integrated PGA simplifies layout and gain switching and is particularly attractive in compact multi-range and multi-sensor nodes where PCB area is constrained.

Many systems adopt a hybrid approach: a modest external amplifier performs level shifting, EMI filtering and basic protection, while the ADC’s PGA provides fine-grained range control. This combination leverages the strengths of both discrete and integrated solutions.