This page treats sigma-delta as a metering chain (from sensors to energy registers). Topics such as general ΣΔ proofs, deep decimation math, or isolation design as a standalone subject are kept out of scope to avoid overlap with sibling pages.

• Samples: acquire v[n] and i[n] on a shared timebase (or measure and compensate relative delay).
• Alignment: correct channel-to-channel delay/phase before power computations.
• Instantaneous power: compute p[n] = v[n] · i[n].
• Average / window: compute real power by averaging p[n] over a controlled window (typically cycle-locked).
• Energy registers: accumulate to Wh and VARh with a fixed update cadence and overflow-safe arithmetic.
• PF & harmonics: derive stable metrics using the same windowing/synchronization strategy to avoid leakage and drift.

Common zero-cross reference options

• Voltage channel: detect zero-cross from the sampled voltage waveform after light conditioning.
• Comparator reference: a dedicated zero-cross signal with clean edges for cycle markers.
• Digital detection: filtered crossing + interpolation to stabilize markers under noise and distortion.

The practical requirement is repeatable timing of the marker relative to the voltage/current sample streams. The critical metric is the relative delay between channels and the marker, because it directly affects PF and harmonic stability.

Key selection checks: clock domain, sync markers (triggers/zero-cross alignment), data link (bitstream vs decimated samples), and multi-channel expansion (repeatable relative delay and calibration consistency).

Practical mapping focus (metering view)

• Voltage path: divider range, isolation boundary (if any), and input protection that avoids excess distortion.
• Current path: CT / shunt / Rogowski selection driven by phase, linearity, drift, and kHz-class harmonic needs.
• AFE: anti-alias filtering and matched group delay so voltage/current channels remain aligned for PF and harmonic stability.

Practical error categories to budget (metering view)

• Amplitude: gain, offset, and sensor ratio tolerance (divider/CT/shunt), including temperature drift.
• Timing: voltage–current relative delay, group-delay mismatch, and marker repeatability (sync / zero-cross).
• Linearity: residual nonlinearity that changes error across load points.
• Noise: noise density and low-frequency noise that dominate light-load and long averaging windows.
• Interference: EMC injection paths that shift readings or increase in-band noise.

Error-budget table field checklist (no numbers needed to stay on track)

• Targets: Wh/VARh accuracy by load points, PF accuracy (near-1 and low PF), harmonics reporting scope, temperature range.
• Gain/offset: initial gain/offset, drift vs temperature, calibration method and update cadence.
• Phase/timing: V–I relative delay (pre/post compensation), group-delay match, sync marker jitter/repeatability.
• Linearity: system residual nonlinearity indicator and the dominant contributors (sensor + AFE + converter).
• Noise/EMC: low-frequency noise indicator, mains hum handling approach, known injection points and protection impact.

• Bandwidth: include the fundamental plus the required low-order harmonics for the metering profile.
• Common filter families: SINC / comb-style chains are popular for predictable attenuation and simple implementation.
• Timing consistency: PF and harmonics repeatability depend on matched group delay across channels.
• Verification focus: check PF repeatability and harmonic stability under frequency drift and load changes.

Spec checklist

• Define Wh/VARh accuracy targets by load points (light, nominal, high current).
• Define PF accuracy targets for near-1 and low-PF operating points.
• Define harmonics reporting scope (low-order harmonics required by the metering profile).
• Define line frequency variation range and the windowing/sync expectation.
• Define temperature range and drift expectations (including calibration hold time).
• Define creep power requirement and the detection/reporting behavior.
• Define reporting cadence and register update rate (accumulation window policy).
• Define factory calibration plan and any field recalibration constraints.
• Define isolation boundary (if any) and how signals cross domains.
• Define traceability requirements (settings, firmware versions, test logs).

Circuit checklist

• Ensure voltage and current paths provide a clear phase-match and gain-match hook.
• Verify input protection strategy does not introduce excess in-band distortion or phase shift.
• Ensure anti-alias intent is explicit (what must be attenuated, where, and why).
• Ensure reference and supply noise constraints are documented as measurable limits.
• Ensure sensor selection assumptions are recorded (phase, linearity, drift, kHz harmonic needs).
• Ensure channel-to-channel consistency strategy exists for multi-channel and three-phase designs.
• Ensure a cycle marker path exists (zero-cross or equivalent synchronization marker).
• Ensure test points and debug modes exist for timing/phase verification.
• Ensure tolerance and drift of key networks are accounted for (divider, burden, shunt, bias).
• Ensure self-heating effects are considered for drift and calibration hold behavior.

PCB checklist

• Keep sensing loops compact and control return paths for voltage/current measurements.
• Separate noisy digital/clock regions from AFE and input routing; document partition rules.
• Avoid shared impedance between high-current paths and sensing returns.
• Route differential or paired signals with symmetry when delay matching matters.
• Audit reference and supply decoupling placement (distance, loop area, return quality).
• Define the ground strategy (where partition boundaries exist and where ties are allowed).
• Verify isolation clearances/creepage are respected wherever the safety boundary exists.
• Document EMC entry points and mitigation placement (clamps/RC/CMCs/TVS location logic).
• Reduce coupling from clocks and fast edges into analog inputs and reference nodes.
• Keep calibration/sense routing stable across variants to protect phase consistency.

Validation checklist

• Verify Wh/VARh error across defined load points and line conditions (repeatability included).
• Verify PF accuracy at near-1 and low-PF cases; track sensitivity to timing mismatch.
• Verify harmonics reporting stability under frequency drift (windowing/sync effectiveness).
• Verify temperature drift with soak tests and post-soak re-checks.
• Verify long averaging behavior under light load (low-frequency noise sensitivity).
• Verify creep power behavior and the detection/threshold logic.
• Verify EMC susceptibility and identify the dominant injection paths.
• Verify multi-channel and three-phase match (relative delay and calibration consistency).
• Verify calibration workflow end-to-end (factory flow and any field steps).
• Record configuration traceability (filter settings, OSR, firmware, test artifacts).

• Single-phase: one voltage + one current channel; simpler synchronization and fewer inter-channel mismatch risks.
• Three-phase: multiple voltage and current channels; requires strict alignment and consistent phase calibration.
• Smart meter: prioritizes long-term drift control, verification closure, and consistent calibration workflows.
• Submeter / industrial monitoring: prioritizes cost and scalable deployment while maintaining repeatable timing behavior.

Integrated ΣΔ ADC / metering IC vs ΣΔ modulator (what changes in the RFQ)

RFQ field checklist (grouped for fast vendor replies)

Copy-ready RFQ template (send to vendor / distributor)

Project: Energy metering ΣΔ (Wh/VARh + PF + harmonics + zero-cross sync)

System context
- Phase: single-phase / three-phase
- Sensors: voltage divider / CT / shunt / Rogowski
- Isolation: none / basic / reinforced (boundary description)
- Outputs: Wh/VARh, PF, harmonics (low-order), reporting cadence
- Temperature range: [min..max]
- Line frequency variation range: [min..max]

Requested IC type
- Integrated ΣΔ ADC / metering IC  OR  ΣΔ modulator (bitstream) + external decimation

RFQ fields (please answer with datasheet references)
1) Performance: noise (in-band + LF), drift vs temp, linearity indicator, input range, channel count
2) Timing/Sync: V–I delay match, group-delay match, sync trigger support, zero-cross marker path, clocking model, latency
3) Safety/Diagnostics: self-test, fault flags, recommended protection, isolation method (if required)
4) Interface/Power: interface type, data rate, power, temperature range notes

Requested deliverables
- Suggested parts (2–3 alternatives) + evaluation board availability
- Reference design / application note links
- Recommended verification guidance for PF/harmonics stability and timing alignment
        

Example ICs to anchor the categories (representative part numbers)