Simultaneous-Sampling / MxADC for Phase-Aligned Multi-Phase
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Simultaneous sampling ADCs are essential for applications requiring precise phase alignment, such as multi-phase motor control and power metering. These ADCs ensure accurate and synchronized sampling of multiple channels, eliminating timing errors and improving system performance.
Definitions, scope and channel forms
A simultaneous-sampling ADC or MxADC provides per-channel sample-and-hold circuits that share a common sampling command. All selected analog inputs are captured at the same aperture instant and held for conversion, so the digital results represent the same point in time across channels. Conversion may proceed sequentially or in parallel, but the time stamp of each sample set is effectively identical.
This behaviour contrasts with generic multi-channel converters that time-multiplex a single sample-and-hold and ADC core through an analog multiplexer. In a purely multiplexed device, each channel is sampled at a slightly different moment in time, which is acceptable for slow, loosely related sensor signals but problematic for phase-sensitive quantities such as three-phase currents or voltage–current pairs used for power computation.
Multiplexed SAR ADCs, built from one SAR core with an on-chip input multiplexer, are well suited to scanning many low-bandwidth channels where phase relationships are not critical. Simultaneous-sampling / MxADC devices, instead, are intended for applications that require true time alignment between channels, trading higher silicon area and tighter channel matching for robust phase accuracy in control and measurement loops.
The scope of this page is limited to on-chip, per-channel sample-and-hold based simultaneous sampling inside a single ADC or microcontroller. Board-level and multi-device clock tree design, protocol-level synchronisation, and time-stamping strategies are covered in dedicated clocking and synchronisation topics. Detailed SAR, pipeline, or sigma-delta core architectures, as well as generic track-and-hold front-end design, are treated in their respective architecture and front-end sections.
Internal architectures of MxADC channels
Inside a simultaneous-sampling ADC or MxADC, channels are organised around per-channel sample-and-hold circuits that share a common sampling command. Above that foundation, vendors typically choose between two main topologies: a per-channel ADC core arrangement, where each channel has its own converter, and a shared-core arrangement, where the channels share a single converter that time-interleaves conversions of the held voltages. Both architectures can deliver true simultaneous sampling at the input pins, but they differ in silicon area, power, throughput and latency.
In a per-channel core design, each input channel drives its own S/H and ADC core. After a common sample command arrives, all S/H stages capture their input at the same aperture instant and each ADC core converts in parallel. This offers high aggregate throughput and minimal additional latency between channels, at the cost of larger area and more concurrent load on references, clocks and digital output paths. It is a natural fit for high-performance motion control, grid measurement or instrumentation where both phase alignment and high update rates are required.
In a per-channel S/H plus shared-core design, each input has its own S/H, but the S/H outputs are converted one by one through a single ADC core after the sample command. All channels still share the same aperture instant because the S/H stages latch the inputs at the same time, but digital results become available in a staggered order as the core visits each held voltage. Channel-level effective throughput is reduced by the number of channels, and there is a small channel-to-channel delay between conversion results, even though the underlying analog information corresponds to the same point in time.
Across both topologies, several resources are shared. A common reference and its buffer network must supply charge to all S/H stages when they transition into hold, producing short but significant current transients. If the reference path is under-dimensioned or poorly decoupled, small reference droop or glitches can create channel-to-channel gain variation. A common sampling clock or digital sample command fans out to all S/H gates, introducing a small but finite distribution skew. The digital core often includes arbitration logic and a shared output interface, which defines how simultaneous sample sets are packaged and transferred off chip.
This internal organisation has direct implications for latency and throughput. Simultaneous sampling guarantees that all channels share the same analog time stamp, but it does not guarantee that all channels provide digital data at exactly the same instant. With a shared core, the effective per-channel sampling rate is the core conversion rate divided by the number of channels in the simultaneous group, and the last channel in the conversion sequence exhibits slightly more delay than the first one. Control and measurement loops therefore need to consider both the sampling instant and the conversion timing when budgeting phase margin and response time.
Scope of this section
This section focuses on channel-level organisation inside MxADC devices and on how a shared sampling command is distributed to per-channel S/H circuits. Detailed SAR, pipeline or sigma-delta core architectures, DAC structures, comparator circuits and track-and-hold transistor-level design are covered in the dedicated architecture and front-end sections.
Timing, phase alignment and triggers
For multi-phase systems, simultaneous sampling only delivers its full benefit when the sampling instants are correctly aligned with the underlying power stage timing. The key concepts are the aperture instant, which defines the effective time associated with each sample, the aperture window, which represents the finite duration of the track-to-hold transition, and the hold period, during which the converter works on a stable voltage. Channel-to-channel aperture skew is the small difference in effective sampling time between channels and translates directly into phase error for sinusoidal or periodic waveforms.
When three-phase currents or voltage–current pairs are measured, channel-to-channel aperture skew causes each channel to observe the waveform at a slightly different point in the cycle. For a sinusoid of frequency f, a time offset Δt between channels corresponds to an approximate phase error of 2πfΔt. At mains frequencies, nanosecond-level skew is usually negligible, but at higher electrical frequencies inside a motor or switching converter, even tens of nanoseconds can distort current reconstruction, d/q transformations and power-factor calculations. Simultaneous-sampling devices therefore specify both absolute aperture and channel-to-channel skew to help designers budget allowable phase error.
In PWM-driven stages, a common strategy is to lock the sampling instant to a well-defined point in the PWM carrier, such as the middle of the on-time where current ripple is lowest. A timer or PWM module generates a hardware trigger at this carrier position, and that trigger drives the MxADC sample command so that all phase currents and voltages are captured at the same relative point in the switching cycle. This avoids situations where one phase is sampled near a switching edge while another is sampled in a flat region, which would otherwise appear as phase or amplitude mismatch in the feedback signals.
Simultaneous-sampling ADCs generally support several trigger modes. A one-shot trigger mode allows a single synchronous sample set to be taken in response to an event, such as a fault condition or test stimulus. Periodic trigger modes link the sampling rate to a timer or PWM period so that new sample sets are captured every carrier cycle or every few cycles. Some devices add programmable sampling delays, enabling fine adjustment of the aperture position relative to the PWM edges or modulation waveform. Moving the sampling instant deeper into the flat region of the waveform improves noise immunity but increases total control-loop delay, so the position is normally chosen as a compromise between waveform quality and phase margin.
Jitter and sampling instant uncertainty
Sampling clock jitter appears as uncertainty in the exact timing of the aperture instant around its ideal position. For simultaneous-sampling devices with a shared sampling clock and carefully matched internal routing, most of this jitter is common to all channels, so channel-to-channel phase accuracy is dominated by differential skew rather than absolute jitter. The impact of jitter on signal-to-noise ratio and on RF/IF sampling is treated in dedicated clocking and jitter topics; in the context of MxADC timing, the primary concern is that jitter and skew remain low enough that phase error at the highest relevant signal frequency stays within the limits of the control or measurement algorithm.
Channel matching, errors and calibration hooks
In a simultaneous-sampling ADC, the most critical imperfections are not only absolute accuracy, but how well channels match each other. Channel-to-channel offset and gain mismatch, dynamic differences in bandwidth and aperture timing, and crosstalk from shared resources can all disturb the relative relationships between currents and voltages that multi-phase control and metering algorithms rely on. These effects remain present even when all channels share the same nominal sampling instant and resolution.
DC mismatch appears as different offsets and gains between channels. Offset mismatch causes differences in measured value when the true quantity is zero, while gain mismatch causes unequal scaling of otherwise identical signals. In three-phase current sensing, this can translate into apparent current imbalance even if the actual phase currents are equal. Dynamic mismatch arises from channel-to-channel aperture skew and small differences in front-end RC networks, which manifest as frequency-dependent phase and amplitude errors. Crosstalk and simultaneous loading originate from multiple S/H stages sampling at the same instant, stressing the shared reference, supply and ground networks and producing small but correlated disturbances on channel inputs.
In field-oriented control, channel mismatch directly impacts the accuracy of the d/q current reconstruction. Offset and gain errors in phase current measurements lead to nonzero d-axis current when the control target is pure q-axis torque, and can introduce torque ripple or audible noise as the control loop continuously compensates a distorted current vector. In three-phase grid and energy-metering systems, mismatched voltage and current channels distort phase-angle estimation and power-factor calculation, and degrade the accuracy of active, reactive and harmonic power measurements even when individual channels appear accurate in isolation.
To address these imperfections, simultaneous-sampling devices typically provide explicit calibration hooks. Per-channel offset and gain registers allow static DC mismatch to be trimmed during production test or in the field. Built-in test modes can short multiple inputs together to an internal reference node or midscale point, enabling direct measurement of offset and gain differences without rewiring the external system. Some converters include small digital multiply-and-add blocks in the data path so that measured correction factors can be applied on the fly, with separate coefficients per channel and sometimes per range or operating mode.
Calibration flow and scope of this section
Practical calibration flows typically combine a few simple steps. Channels are first tied to a common known level to estimate and cancel offsets. A second reference level or current is then applied to derive per-channel gain factors. For high-frequency or phase-sensitive applications, a periodic stimulus may be used to characterise effective channel-to-channel delays so that phase corrections can be implemented in the control or measurement algorithm where supported. This section focuses on identifying error mechanisms and on the hardware hooks that enable calibration. Detailed strategies for production trim, in-field re-calibration and self-test are covered in the dedicated Calibration & Self-Test topics.
Application patterns: multi-phase systems and sensing topologies
Simultaneous-sampling ADCs are primarily used wherever several related channels must be observed at the same instant rather than scanned in sequence. In multi-phase power stages, three-phase grid interfaces and multi-axis sensing systems, control and measurement algorithms operate on vector quantities built from multiple currents and voltages. An MxADC front end provides a time-aligned snapshot of all relevant channels at a defined position in the switching cycle, mechanical motion or grid waveform, which simplifies the control design and improves numerical robustness.
In three-phase motor drives and inverters, simultaneous-sampling devices are commonly placed behind low-side, high-side or phase-leg shunt resistors and their associated amplifiers. The phase currents Ia, Ib and Ic are sampled at the same point in the PWM carrier, often in the middle of a flat conduction interval to minimise switching noise. The resulting aligned samples form the basis for d/q current reconstruction and torque control. The exact choice of shunt topology, the relationship between sampling instants and dead-time, and the current reconstruction strategy depend on the drive architecture and are covered in motor-control application topics; the role of the MxADC front end is to deliver phase-coherent current information on each control cycle.
In PFC stages and digital power supplies, simultaneous sampling is used to capture input voltage and inductor current at the same instant so that instantaneous power can be computed accurately. When multiple interleaved phases are used, aligned current measurements from each phase allow reliable current sharing and ripple cancellation. The MxADC channels are typically triggered by a timer or PWM event associated with the power-stage carrier, ensuring that voltage and current samples correspond to the same segment of the switching cycle and that phase differences between interleaved legs are correctly represented in the digital domain.
Three-phase grid interfaces and energy-metering systems rely on accurate phase relationships between Ua, Ub, Uc and Ia, Ib, Ic. Simultaneous-sampling converters are well suited to sampling all voltage and current channels as a coherent set so that phase angles, power factor and harmonic content can be derived without additional timing correction. In this context, simultaneous sampling complements metrology-grade calibration and filtering techniques that handle long-term drift and distortion. Phase-aligned V and I samples simplify the implementation of standards-compliant power and energy calculations on a DSP or dedicated metering processor.
Multi-axis and multi-point sensing, and scope of this section
Beyond power stages and metering, MxADC devices are also used in multi-axis sensing and distributed sensor arrays where spatial information must be captured within a narrow time window. Examples include multi-axis torque or position sensing, multi-point vibration and acoustic monitoring, and pressure or force sensor grids. In these systems, simultaneous sampling ensures that the relative amplitudes and phases across channels reflect the same physical instant, which is essential for modal analysis, correlation and control. This section describes how an MxADC front end fits into such multi-channel topologies. Detailed control algorithms for field-oriented drives, PFC loops, energy metering and advanced sensing applications are treated in their respective application-focused sections.
Key specs and selection logic for Simultaneous-Sampling / MxADC
When selecting a simultaneous-sampling ADC, several key specifications should be considered based on the specific needs of your application. These include the number of channels, sampling rate, resolution, skew characteristics, sync capabilities, front-end features, and isolation requirements. This section outlines the most important parameters to consider and provides guidance for making an informed decision based on system requirements.
From an engineering inquiry perspective, here are the essential questions to ask when choosing an MxADC:
- How many channels support true simultaneous sampling? Is there a grouping concept for sampling?
- What is the effective resolution and maximum sampling rate per channel and in aggregate?
- What is the typical aperture skew and channel-to-channel mismatch (gain/offset)? How do these change with temperature or time?
- Can the ADC be triggered directly by PWM/timer signals? Does it support sampling delay registers and multiple sync modes?
- What is the input range and common-mode range? Does it support directly interfacing with shunt resistors, current transformers, or voltage dividers?
- Does the device support isolation for high-side measurements or grid applications? Should an isolated ADC be chosen?
The following sections delve into each specification in detail and outline the key features to evaluate when selecting the best MxADC for your application.
BOM & inquiry checklist for MxADC-based designs
When designing with a simultaneous-sampling MxADC, it is crucial to specify the necessary parameters to ensure compatibility with your system. This section provides a checklist for key specifications to consider during your inquiry and BOM preparation. This will guide you in communicating clearly with suppliers and help ensure that all design requirements are met.
The checklist includes both **ADC-specific fields** and **system-related fields**, which will help you confirm the key technical details when discussing with suppliers and selecting the appropriate components.
ADC-specific fields
- Number of simultaneous channels: How many channels support true simultaneous sampling? Is there a grouping concept for sampling?
- Resolution / ENOB: What is the effective resolution and ENOB of each channel?
- Max sampling rate per channel: What is the maximum sampling rate per channel and in aggregate?
- Aperture skew (typ / max): What are the typical and maximum values for aperture skew between channels?
- Channel matching (gain/offset): What are the gain and offset matching specifications? Are they adjustable?
- Sync trigger options (timer / GPIO / PWM link): Can the ADC be triggered by PWM, timers, or GPIO for synchronous sampling?
- Supported input types (single-ended / differential): Does the ADC support single-ended and differential inputs?
- Input range / reference options: What are the input range and reference voltage options available?
- Isolation options (if integrated): Does the ADC offer integrated isolation for high-side measurements or grid systems?
System-related fields
- Target PWM frequency / control loop bandwidth: What is the target PWM frequency and control loop bandwidth for synchronization?
- Input shunt / CT topology: What is the topology for the shunt resistors or current transformers used in the system?
- Isolation requirements: Are there isolation requirements for high-side or grid applications?
- Operating temperature range: What is the operating temperature range of the ADC and other components?
Example BOM & Inquiry Checklist
The following table outlines the essential parameters to include in your BOM and inquiry checklist. It will help ensure that the components you select meet the system requirements.
| Component | Description | Quantity | Specs/Requirements | Questions to Supplier |
|---|---|---|---|---|
| MxADC | Simultaneous-Sampling ADC | 1 | Max sampling rate, aperture skew, channel count, resolution | How many simultaneous channels? What is the max sampling rate? |
| Shunt Resistor | Current sense resistor | 3 | Voltage drop, power rating | Is the resistor rated for high power dissipation? |
| Microcontroller | For processing ADC data | 1 | Processor speed, I/O compatibility | What are the I/O pins for ADC data transfer? |
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FAQs – Simultaneous-Sampling / MxADC
Why is simultaneous sampling needed for three-phase motor control?
Answer: Simultaneous sampling ensures that all three-phase currents are captured at the same time, which is critical for accurate torque control in motor drives. Without simultaneous sampling, phase misalignment can result in torque ripple and motor control errors.
Explanation: In three-phase motor control, precise alignment of phase current measurements is essential to calculate the correct torque vector. Any timing mismatch between the samples of each phase results in incorrect `Id` and `Iq` values, causing disturbances like torque ripple and reduced control stability.
How to Address: To avoid phase misalignment, use an MxADC with true simultaneous sampling capabilities or synchronize multiple ADCs to ensure phase coherence across all channels.
Simultaneous sampling ADC vs multiplexed ADC – which one for multi-phase systems?
Answer: Simultaneous sampling ADCs are preferred for multi-phase systems where accurate phase relationship and high-speed synchronization are crucial. Multiplexed ADCs can introduce timing delays that are detrimental to applications requiring tight phase accuracy.
Explanation: While multiplexed ADCs can scan multiple channels, they do so sequentially, introducing small timing mismatches between channels. In contrast, simultaneous sampling ADCs capture all channels at once, ensuring correct phase alignment, making them ideal for multi-phase power systems, motor control, and grid metering applications.
How to Address: If high phase accuracy and real-time performance are critical, a simultaneous sampling ADC should be selected. Multiplexed ADCs may be suitable for slower, less phase-sensitive applications.
What is aperture skew and how does it affect phase accuracy?
Answer: Aperture skew refers to the timing difference in sampling between different channels in a simultaneous sampling ADC. Even a small skew can lead to phase errors, which significantly impact applications that require accurate timing, such as motor control and power metering.
Explanation: In systems like motor control, the phase currents must be sampled at exactly the same instant. Aperture skew, even in the range of nanoseconds, can cause misalignment in the phase currents, leading to errors in torque calculation or inaccurate power factor measurements.
How to Address: To minimize aperture skew, choose an ADC with low skew specifications and ensure that the system’s timing controls are tightly synchronized.
How tight must channel-to-channel skew be for FOC / PFC?
Answer: For Field-Oriented Control (FOC) and Power Factor Correction (PFC), channel-to-channel skew should be minimized to ensure accurate current vector calculations. Ideally, the skew should be less than a few nanoseconds to avoid significant control errors.
Explanation: In FOC and PFC applications, small timing errors between current samples can cause incorrect calculations of the `Id` and `Iq` components, leading to inefficient torque control or unstable voltage regulation. The smaller the skew, the more accurate the control system will be.
How to Address: Look for ADCs with specifications for low aperture skew and ensure proper synchronization in multi-channel sampling systems to meet the required precision for FOC and PFC.
How to align ADC sampling instant with PWM carrier or edge?
Answer: Aligning the ADC sampling instant with the PWM carrier or edge can be done by using a synchronized trigger from the PWM timer or an external trigger signal.
Explanation: In motor control and PFC, synchronizing the sampling point with the PWM carrier ensures that the current samples are captured during the steady conduction phase of the PWM, minimizing errors caused by switching transients.
How to Address: Use ADCs with trigger input capabilities that allow synchronization with PWM, or configure an external trigger mechanism that aligns the sampling instant with the desired PWM edge.
Can a non-simultaneous multi-channel ADC emulate simultaneous sampling by firmware?
Answer: While it is possible to emulate simultaneous sampling using a multi-channel ADC and firmware techniques, the timing mismatch introduced by sequential sampling can still lead to phase misalignment, especially in high-speed applications.
Explanation: Firmware can be used to coordinate the sampling of multiple channels, but inherent delays between channels may still exist, causing phase errors in time-sensitive applications like motor control or power metering.
How to Address: To achieve true simultaneous sampling, it is recommended to use an ADC designed for simultaneous channel sampling rather than relying on firmware-based solutions.
How does simultaneous sampling interact with isolated shunt or isolated ΔΣ modulators?
Answer: Simultaneous sampling works well with isolated shunts and isolated ΔΣ modulators by ensuring that all phase measurements are captured at the same instant, preventing errors due to isolation delays.
Explanation: In high-voltage applications, isolation is necessary to protect sensitive circuitry. Isolated shunts and ΔΣ modulators provide accurate current sensing, and simultaneous sampling ensures that the phase current samples are aligned, minimizing any timing discrepancies.
How to Address: Ensure that the isolated components used for current sensing are compatible with the ADC’s simultaneous sampling capabilities to avoid misalignment in measurements.
Which specs in the datasheet tell me the quality of simultaneous sampling?
Answer: Key specifications include aperture skew, channel matching (gain/offset), maximum sampling rate, and trigger synchronization features.
Explanation: Aperture skew and channel matching directly affect the accuracy of simultaneous sampling. Higher sampling rates and reliable synchronization triggers also indicate a high-quality ADC suitable for simultaneous sampling applications.
How to Address: Review the datasheet for specifications related to aperture skew, channel matching tolerance, trigger synchronization options, and the ADC’s sampling capabilities.
Why do measured phase currents look unbalanced even with a simultaneous sampling ADC?
Answer: Unbalanced phase currents can occur due to external factors such as improper calibration, incorrect shunt placement, or environmental disturbances that affect the measurements.
Explanation: Even with a simultaneous sampling ADC, if the external sensors or system are not calibrated properly, phase current measurements can become unbalanced. System wiring or layout issues may also introduce errors.
How to Address: Ensure correct shunt placement, calibrate all sensors, and check for grounding or wiring issues that may cause measurement discrepancies.
How to calibrate channel gain/offset mismatch in a simultaneous sampling system?
Answer: Channel gain and offset mismatches can be calibrated using internal offset/gain registers and external calibration equipment.
Explanation: Many simultaneous sampling ADCs provide registers for adjusting channel offset and gain. Additionally, calibration equipment can be used to align the channels accurately.
How to Address: Use the ADC’s built-in calibration registers to adjust offsets and gain, and verify accuracy using known reference signals.
What trigger schemes are recommended for multi-phase power or energy metering?
Answer: Recommended trigger schemes include PWM-based triggering or timer-based synchronization for accurate sampling across multiple channels.
Explanation: Using a timer or PWM signal to trigger simultaneous sampling ensures that all phase currents are sampled at the same time, reducing phase misalignment.
How to Address: Configure the ADC’s trigger system to sync with the system’s PWM signal or timer to maintain phase alignment across the channels.
When is simultaneous sampling overkill and a MUXed SAR ADC is enough?
Answer: Simultaneous sampling is overkill for low-speed applications or systems where phase accuracy is not critical. A MUXed SAR ADC may suffice in such cases.
Explanation: For applications like slow sensors or systems that don’t require tight phase synchronization, a multiplexed ADC may be a cost-effective solution.
How to Address: Assess the phase accuracy and speed requirements before selecting a simultaneous sampling ADC. If precise synchronization is not needed, consider using a MUXed SAR ADC instead.
