Motor Control / PSU with SAR ADC
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This page explains how to use SAR ADCs to sample motor and PSU currents/voltages synchronously with low latency, and how to select, design and debug the SAR signal chain so control loops stay stable, efficient and low-ripple rather than chasing metrology-grade accuracy.
What this page solves – SAR in motor control & PSU loops
This page focuses on how SAR ADCs are used for voltage and current sensing inside motor control and power-supply control loops. The scope is limited to sampling for FOC, current loops, voltage loops, PFC and digital PSU regulators, where synchronous sampling and low latency directly define loop stability and dynamic response.
Topics such as revenue energy metering, high-precision laboratory instrumentation and generic ADC architecture theory are intentionally left to other pages. Here the emphasis is on how the SAR ADC interacts with PWM timers, control firmware and noisy power stages to deliver reliable current and voltage information to FOC and PID loops.
- Clarify where SAR ADCs are used in motor drives and digitally controlled PSUs, and which signals are measured.
- Explain why synchronous sampling and microsecond-class latency are critical for FOC and fast voltage or current loops.
- Point readers toward other ADC topic pages when needs shift to energy metering, isolation, or precision DC measurements.
It does not derive full FOC or PID mathematics and does not duplicate detailed front-end or isolation design content, which are covered in dedicated architecture and front-end pages.
Where SAR ADC fits in motor drives & PSUs
SAR ADCs sit between noisy power stages and digital control cores. In motor drives they watch phase currents, DC bus voltage and key temperatures; in digitally controlled PSUs they monitor inductor currents, line and bus voltages, output voltage and thermal points. This section focuses on where the ADC is placed in typical topologies and which signals are routed into its channels.
Only measurement locations and channel allocation are covered here. Detailed shunt design, bridge front-ends and isolation amplifiers are handled in dedicated front-end pages, so that each topic remains clean and non-overlapping.
SAR ADC inside 3-phase motor drives
In a three-phase inverter with FOC, the SAR ADC typically measures phase currents through one or more shunts, DC bus voltage for protection and voltage-loop control, and auxiliary temperature channels such as motor case or heatsink sensors. These measurement points map onto multiple ADC channels and define minimum channel count and input range requirements.
SAR ADC inside digitally controlled PSUs and PFC stages
In PFC and isolated DC/DC converters, the SAR ADC observes inductor current, line voltage, DC bus voltage and the regulated output voltage. Additional channels often track transformer or inductor temperature and secondary-side thermal limits. Together these inputs allow digital control loops to regulate output, maintain power factor and enforce protection thresholds.
Summary of signal types into SAR ADC
Across motor and PSU applications, SAR channels can be viewed as three groups: fast current channels, medium-speed voltage channels and slow auxiliary channels such as temperature. Each group places different demands on channel count, common-mode range and sampling bandwidth, which later drive timing, filtering and OSR choices.
Control-loop timing & synchronous sampling (FOC / PID)
Motor control and digitally controlled PSUs rely on tightly timed loops where PWM switching, current and voltage sampling, and control calculations all align. SAR ADCs are used because their acquisition window and conversion latency can be placed precisely within each PWM period, enabling synchronous sampling and microsecond-class loop updates.
The key questions are when to place the ADC acquisition window inside the PWM cycle, how to avoid noisy switching edges, and how the total delay from sampling to PWM update limits achievable loop bandwidth. These timing decisions directly affect torque ripple, current-loop stability and voltage-loop response.
PWM period as the timing backbone
In FOC and digital PSU designs, the PWM period defines the natural timing grid. Critical current measurements are taken once or several times per PWM cycle, so that each loop iteration sees samples at a consistent electrical phase. Asynchronous sampling that drifts relative to PWM tends to mix different switching edges and noise conditions, causing the estimated current to wander and making loop behaviour less predictable.
Choosing the sampling instant inside the PWM cycle
A PWM cycle contains brief dead-time and switching edges where dv/dt and di/dt are high and current waveforms are distorted. The SAR ADC acquisition window is therefore placed in the flat, fully-conducting region of the PWM pulse, away from edges. Three-shunt current sensing offers relatively wide flat regions per phase, while single-shunt sensing provides narrow windows tied to specific switching states, which drives tighter requirements on acquisition time and trigger jitter.
Sample-to-PWM update delay and loop bandwidth
Once the sample is captured, the SAR conversion time, data transfer, control computation and PWM register update form a total loop delay. Larger delay forces the current or voltage loop bandwidth to be reduced to maintain adequate phase margin. Fast SAR conversion and efficient firmware allow the loop to be updated within the same or next PWM period, supporting higher usable bandwidth and better dynamic response without resorting to complex compensation.
Sampling frequency for currents and voltages
Current channels in FOC and PFC are generally sampled at least once per PWM cycle, and sometimes twice per cycle for symmetric schemes or averaging. Voltage channels often tolerate lower sampling rates while still aligning with the control loop. Extra samples can be used for averaging or simple filtering, but every additional conversion must fit within timing and latency budgets defined by the PWM period and loop delay.
Sensing topologies for SAR in motor & PSU systems
Motor drives and digitally controlled PSUs use a small set of recurring sensing topologies. These include single-shunt and multi-shunt current sensing, phase and bus voltage sensing, and slower auxiliary channels such as temperature and Hall sensors. Each topology drives specific requirements for SAR ADC channel count, input range, common-mode window and allowable acquisition time.
This section focuses on how these topologies map into SAR channels and timing. Detailed trade-offs between shunt and Hall sensing, bridge excitation schemes and precision bridge measurements are handled in dedicated front-end and sensing pages, to avoid overlap and keep this topic centred on motor and PSU SAR usage.
Single-shunt and multi-shunt current sensing
With a single DC-link shunt, the SAR ADC observes bus current pulses that only represent phase currents during specific switching combinations. This yields tight sampling windows and pushes the ADC toward shorter acquisition times, low trigger jitter and close coupling to the PWM timer. Multi-shunt schemes, such as two or three phase shunts, provide wider current flat regions per phase, relaxing timing while increasing the number of fast current channels required.
Voltage channels: phase, bus and output
Phase voltage and DC bus voltage in motor drives, along with Vbus, Vline and Vout in PSUs, form a second group of channels. These inputs generally change more slowly than current but require sufficient resolution and linearity to support protection and regulation. After scaling and conditioning, they often share the same SAR device as current channels and are sampled at one or more points per PWM period or at a lower rate tied to the voltage loop.
Auxiliary sensing and multiplexed inputs
Auxiliary channels such as NTC temperature sensors, analogue Hall outputs and fan feedback signals form a slow tier of measurements. These can often be multiplexed or sampled less frequently, as long as the SAR scheduling guarantees that fast current channels receive priority and that timing requirements derived from control loops are not compromised. Grouping channels into fast, medium and slow tiers simplifies channel allocation and OSR or averaging strategies in later sections.
Key SAR ADC requirements for FOC & PSU control
In motor drives and digitally controlled PSUs, SAR ADC requirements are set by control performance rather than by abstract datasheet metrics. Resolution and ENOB must support target torque ripple and voltage accuracy, sample rate must keep up with current and voltage loop bandwidth, and conversion latency must stay within the allowed delay budget set by PWM frequency and control execution time.
Linearity and static errors also translate directly into control behaviour. INL and DNL contribute to harmonic distortion in measured current and voltage waveforms, while offset, gain error and drift shift torque-producing current components and long-term output regulation. This section links these parameters back to application-level outcomes for FOC and digital power control.
Resolution, noise and ENOB for motor and PSU loops
Nominal resolution sets the code step size, but effective resolution is defined by ENOB once noise and distortion are included. FOC current loops require enough ENOB to resolve small changes in phase currents over the chosen full-scale range so that torque ripple and low-speed jitter remain within limits. PFC and PSU regulators need sufficient ENOB on current and voltage channels to meet ripple, accuracy and harmonic performance targets without excessive filtering latency.
Sample rate and loop bandwidth
Required sampling rate is driven by loop bandwidth and the number of fast channels. For a given current-loop bandwidth, the SAR must provide enough conversions per PWM period to sample each current channel at the required rate, while still leaving room for voltage and auxiliary channels. Multi-kSPS per channel is typical, with hundreds of kSPS to several MSPS total throughput for multi-channel FOC and digital power designs.
Conversion time, latency and control delay budgets
From the moment a sample is acquired, total delay includes SAR conversion time, data transfer, control computation and PWM register updates. This combined delay must stay within the timing budget allowed by the PWM period so that current and voltage loops remain stable at the planned bandwidth. Short, deterministic SAR conversion times make it easier to keep delay within limits and to schedule oversampling or redundant readings.
Linearity, INL/DNL and distortion
INL and DNL errors bend the transfer curve between sensed analogue quantities and ADC codes. In FOC, this distortion appears as extra harmonic content in estimated phase currents, which translates into torque ripple and acoustic noise. In PFC and PSU control, non-linearity can increase current THD and disturb the relationship between control commands and measured power variables, especially near low-current regions where error is more visible.
Offset, gain error and drift
Offset and gain errors, along with their thermal drift, produce systematic shifts in measured current and voltage. In motor drives this can cause non-zero torque at zero command, biased d/q currents and uneven thermal loading. In PSUs and PFC stages, these errors show up as persistent output voltage offset, inaccurate current shaping and degraded efficiency margins. Calibration and error budgeting are therefore essential when selecting SAR devices for demanding control applications.
Front-end, filtering & protection around SAR in noisy power stages
In motor drives and SMPS hardware, the SAR ADC sits close to switching nodes that generate high dv/dt and di/dt noise. The front-end network between shunts or sense points and the SAR input must both clean up this noise and protect the ADC from surges, while still allowing the input to settle within the acquisition window. Component choices in this region directly affect measurement accuracy and timing margin.
This section focuses on RC filtering, driver or buffer stages, simple protection elements and the immediate PCB layout around the analogue inputs. Broader EMC, isolation spacing and global power layout topics are handled in dedicated system-level pages so that this discussion stays local to the SAR input environment.
RC filtering and acquisition-time settling
A small RC network is usually placed between the sense point and SAR input to attenuate switching edges and high-frequency noise. The effective time constant, set by series resistance and the total capacitance seen at the ADC input, must be short enough that the voltage settles within the acquisition window, yet large enough to provide useful filtering. Excessive source impedance or capacitance slows settling and causes samples to reflect a mix of present and previous values.
Drivers, buffers and source impedance
Many designs place a differential amplifier or unity-gain buffer between the RC filter and SAR input. The driver provides a low, well-controlled output impedance so that the sampling capacitor can charge quickly and repeatably during the acquisition phase. At the same time, the amplifier defines gain, common-mode handling and rejection of power-stage noise, and must remain stable across the load presented by the SAR’s switched-capacitor input.
Protection components and their side effects
Series resistors, clamp diodes and TVS devices are added to limit surge current and keep input voltages within absolute ratings during faults, transients and ESD events. These components increase effective source impedance and can lengthen recovery time after clamping, which must be taken into account when defining acquisition time and sampling phase. Protection is therefore chosen with both survival and measurement recovery in mind.
Local grounding and routing near the SAR inputs
The PCB region around the SAR input benefits from clear separation between high-current switching paths and sensitive analogue nodes. Short, direct routes from shunts or dividers to the RC and driver stage reduce coupling, while careful reference and return paths around the ADC help maintain a clean measurement ground. Differential routing, compact loops and shielding from high dv/dt nodes improve the probability that the SAR sees a clean waveform during its acquisition window.
Oversampling, averaging & OSR noise shaping with SAR ADC
Oversampling and averaging let SAR ADCs deliver higher effective resolution and lower noise for motor and PSU control without changing the converter core. Multiple samples of the same current or voltage are combined through simple digital filters so that random noise averages down, while the control loop still runs at its target update rate and bandwidth.
The benefit of oversampling is always traded against added latency and phase delay. Short averaging windows and low-order filters are preferred on fast current channels, while longer windows and stronger smoothing are reserved for slower voltage and auxiliary channels. This section links oversampling depth and filter choice to control bandwidth and stability.
Oversampling and averaging for better effective resolution
When multiple SAR readings of the same quantity are combined, uncorrelated noise tends to cancel while the useful signal adds coherently. Averaging a block of samples or passing them through a simple low-pass filter can improve effective resolution by a fraction of a bit and make current and voltage estimates more repeatable, especially in low-speed and light-load conditions.
Impact on loop latency, bandwidth and phase margin
Collecting more samples and applying wider filters increases measurement delay. For FOC current loops this extra latency and phase lag can quickly reduce achievable bandwidth and phase margin, especially when combined with PWM and computation delays. Digital power voltage loops are less sensitive but still require that oversampling windows remain compatible with the chosen crossover frequency.
Simple FIR and IIR filters for current and voltage readings
Control loops typically rely on very simple digital filters. Moving-average filters over a small sample window reduce noise at the cost of a fixed group delay, while first-order IIR filters act as exponential averages with a tunable time constant. Fast current channels use short windows and light filtering, whereas slower voltage and auxiliary channels can use longer time constants to stabilise displayed and logged values.
OSR strategies for fast, medium and slow channels
Oversampling strategies are best tailored per channel tier. Fast current channels use limited oversampling and minimal filtering to protect loop bandwidth. Medium-speed voltage channels apply moderate OSR and smoothing tied to the voltage loop dynamics. Slow channels such as temperature can exploit high OSR and long averages to obtain very clean readings without affecting fast FOC or PFC loops.
Engineering checklist for motor / PSU SAR designs
This checklist condenses the key considerations for using SAR ADCs in motor drives and digitally controlled PSUs. It is intended as a quick review before design freeze or device selection, helping teams verify that timing, topology, front-end, noise and layout aspects have all been covered.
Each line item represents a decision or verification point that should be documented during requirements capture, architecture and implementation reviews. Detailed parameter definitions and selection fields are handled in later sections so that this part remains a concise engineering board for motor and PSU SAR usage.
Checklist areas
The checklist focuses on five clusters: timing and synchronisation, channels and topology, front-end and protection, noise and oversampling strategy, and local layout and grounding around the SAR inputs.
IC selection logic & RFQ fields for Motor/PSU SAR
SAR ADC selection for motor drives and digitally controlled PSUs is driven by control requirements rather than generic datasheet metrics. A clear application profile for the drive or power stage is translated into concrete ADC parameters such as resolution, ENOB, sampling rate, latency, input structure and operating range, which then become RFQ fields for suppliers and distributors.
This section organises selection logic for motor current sensing and digital power control, and then condenses it into an RFQ checklist with example part numbers. The examples are reference points for performance ranges and feature sets rather than recommendations of specific vendors.
From application profile to SAR requirements
A motor or PSU profile summarises the constraints that drive SAR ADC requirements. For motor control this typically includes motor type, DC bus voltage range, FOC or vector-control usage, target current-loop bandwidth, PWM frequency and modulation scheme, shunt topology and phase count. For PSUs it captures topology, line and load range, output accuracy targets, loop bandwidth, harmonic and efficiency objectives and any industry or safety standards that apply.
These profile items determine how many channels are needed, how fast they must sample, how tightly sampling must align with PWM edges, what dynamic range and ENOB are required and how much delay and oversampling budget is available in the control loop.
Motor current sensing SAR selection logic
For FOC and vector-controlled drives, SAR ADC choice for current sensing is driven by:
- Dynamic performance: total throughput and per-channel sampling rate must support sampling of phase currents, bus voltage and auxiliary signals within each PWM period, with conversion time short enough to fit in the latency budget.
- Synchronization: hardware triggers from PWM timers and simultaneous sampling channels are important for three-shunt sensing and accurate reconstruction.
- Resolution and ENOB: required effective resolution is set by torque ripple, low-speed smoothness and sensing range; typical designs fall in the 12–16 bit band with application-specific ENOB targets.
- Linearity and error: INL, DNL, offset, gain error and drift affect torque bias, harmonic distortion in estimated currents and long-term stability.
- Input structure: differential or pseudo-differential inputs, input range and common-mode window must match the chosen front-end amplifiers and shunt voltages.
Representative SAR ADCs often used as performance references for motor current sensing include:
- ADS8866 (Texas Instruments): 16-bit, 1 MSPS, single-channel precision SAR suitable for high-accuracy phase-current or bus-voltage sensing with external multiplexing.
- AD7380-4 (Analog Devices): 16-bit, multi-MSPS, four-channel simultaneous-sampling SAR for three-phase current plus bus-voltage capture with tight timing.
- AD7656A (Analog Devices): 16-bit, six-channel simultaneous-sampling SAR often used where three-phase currents and multiple voltages are converted in parallel.
- MCP3208 (Microchip): 12-bit, 8-channel SAR for cost-sensitive drives where moderate resolution is sufficient and channels are scanned sequentially.
Digital PSU / PFC SAR selection logic
In digitally controlled PSUs and PFC stages, SAR selection emphasises:
- Channel set: PFC inductor current, input and bus voltages, converter output voltage and current, and thermal or protection sensors.
- Sampling rate: support for PFC current loop bandwidth and fast detection of line disturbances and load steps, with adequate margin for oversampling and filtering.
- Resolution and ENOB: sufficient effective resolution for output regulation targets, efficiency tuning and harmonic performance over the full line and load range.
- Latency: compatibility with chosen loop crossover frequency and phase margin for both current and voltage loops.
- Reference and PSRR: reference accuracy, drift and rejection of supply noise play a significant role in precision voltage measurements.
Example SAR ADCs commonly referenced in digital PSU and PFC applications include:
- AD7980 (Analog Devices): 16-bit, 1 MSPS precision SAR suitable for high-accuracy voltage and current sensing in digital power control.
- ADS7947 (Texas Instruments): 14-bit, dual-channel SAR with up to 1 MSPS per channel for PFC current and voltage measurement.
- MCP33131 (Microchip): 16-bit SAR with hundreds of kSPS throughput for precision output voltage sensing and current monitoring.
- LTC2311-16 (Analog Devices/Linear Technology): 16-bit, multi-MSPS SAR used as a reference where higher speed and dynamic range are required in power stages.
RFQ field checklist and example template
An RFQ for Motor/PSU SAR ADCs typically includes the following technical fields:
- Application type and environment: motor drive / PFC / DC/DC; industrial or automotive; operating temperature range.
- Resolution and effective resolution: nominal bits and required ENOB over the relevant bandwidth.
- Throughput and channels: total sampling rate, per-channel rate, number of fast and slow channels.
- Latency and triggering: maximum allowed conversion and group delay; PWM or timer-based triggering; need for simultaneous sampling.
- Input structure: single-ended, differential or pseudo-differential; input range; common-mode window.
- Reference and accuracy: internal or external reference, required accuracy and drift; gain and offset error limits.
- Power and interface: supply range, power consumption limits, interface type (SPI, LVDS, parallel) and required data throughput.
- Reliability and diagnostics: ESD/surge robustness expectations, self-test or BIST features, industrial or automotive qualification.
Motor-control-specific RFQs typically add details on motor type, shunt topology, target current-loop bandwidth, PWM frequency range and torque ripple limits, while PSU/PFC RFQs add topology, power level, regulation accuracy, transient response targets and PF/THD goals. Reference SAR devices such as ADS8866, AD7380-4, AD7980 or MCP33131 can be mentioned in the RFQ as indicative benchmarks for performance and features.
Application archetypes – patterns for Motor/PSU SAR
The same SAR ADC principles are applied in repeatable patterns across many motor and PSU designs. Typical archetypes differ mainly in which signals are measured, how sampling is aligned with PWM or mains waveforms and how OSR and front-end resources are allocated. Knowing which archetype a project resembles helps focus attention on the most relevant requirements.
This section outlines four common patterns: three-shunt FOC, single-shunt FOC, PFC with downstream DC/DC and multi-motor or multi-PSU systems that share SAR resources. Each pattern is described in terms of measured signals, sampling behaviour and design tendencies rather than full power-stage details.
3-phase FOC, 3-shunt archetype
In this pattern, three shunts in the phase legs or in the return paths provide individual phase currents. The SAR samples all three currents simultaneously at defined PWM instants, often with an additional channel for DC bus voltage and slower channels for temperature and diagnostics. Tight synchronisation, short and deterministic conversion times and good ENOB and linearity for phase currents are the main drivers.
Single-shunt FOC archetype
Single-shunt FOC measures current through a single DC-link shunt and reconstructs phase currents from multiple samples taken at different PWM intervals. The SAR must capture current in narrow time windows between switching edges, with highly accurate triggers and low conversion latency. Reconstruction logic in the control firmware replaces extra hardware shunts at the cost of stricter timing constraints.
PFC + DC/DC digital PSU archetype
In a digital PFC plus DC/DC converter, SAR channels observe PFC inductor current, input voltage and DC bus voltage, along with output voltage and current for the downstream stage. PFC current readings are synchronised to the line waveform and switching cycle, while bus and output voltages use more oversampling and averaging. Voltage accuracy, current-loop bandwidth and compliance with harmonic and efficiency targets guide the ADC configuration.
Multi-motor / multi-PSU shared SAR archetype
Multi-motor or multi-PSU systems often share one or more SAR ADCs across several control loops. Critical motors or PFC stages may receive dedicated fast channels or separate ADC devices, while less demanding loops share multiplexed channels with lower sampling priority. Channel scheduling, trigger mapping and tiered OSR strategies become key design tools to balance performance, cost and resource usage.
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FAQs – Motor / PSU SAR long-tail
This FAQ collects long-tail questions that typically appear during bring-up and debugging of SAR-based motor and PSU control loops. The focus is on timing, front-end behaviour, oversampling, resource sharing, input structure and practical calibration issues rather than general control theory or power-topology design.
Is it OK to sample currents asynchronously and just align them in software?
For fast control quantities such as phase currents or PFC inductor currents, asynchronous sampling is generally unsafe. The actual current waveform depends strongly on the PWM state, so sampling at slightly different instants inside each period observes different portions of the switching ripple. Software alignment without precise time stamps, PWM state information and a reliable current model leaves residual timing error that appears as noise or bias in the estimated currents.
For slow quantities such as DC bus voltage, output voltage or temperature, asynchronous sampling is usually acceptable. Their time constants are much longer than the PWM period, so moderate timing variation is easily removed by low-pass filtering and averaging.
In practice, high-bandwidth current loops and PFC current control should use hardware-synchronised sampling tied to the PWM or a timer. Asynchronous sampling with post-alignment is better reserved for slow housekeeping channels.
Why does current measurement jump at PWM edge with SAR ADC?
Current readings tend to jump near PWM edges because both the power stage and the front-end are in a transient state. High dv/dt and di/dt around switching edges create voltage spikes across shunts, parasitic inductances and layout stray elements. If the SAR acquisition window falls in this unsettled region, the sample captures a mixture of true current and switching artefacts.
Additional error sources include finite RC settling at the input filter and amplifier recovery from large common-mode steps. These effects combine into apparent “steps” or “glitches” in the digitised current, especially at high duty cycles and high bus voltages.
The usual fix is to move the sampling point into a flat region of the PWM period, allow enough acquisition time for the RC and driver to settle and minimise coupling from fast switching nodes through careful layout and shielding.
Can I share one SAR ADC between motor control and PSU control loops?
Sharing one SAR ADC between motor and PSU control loops is possible if the total sampling budget comfortably meets all loop requirements. Fast loops such as motor phase-current control and PFC current control must be given highest priority, with guaranteed sampling slots and conversion deadlines inside each PWM period.
Slower loops such as bus-voltage regulation, output-voltage control or auxiliary monitoring can be scheduled in the remaining time and often tolerate lower sampling rates and additional averaging. Problems arise when too many channels compete for the same SAR, forcing longer scan times or irregular sampling intervals that compromise loop stability.
When a single SAR cannot sustain the required mix of fast, medium and slow channels, the design should migrate to multiple ADC devices or a combination of on-chip ADCs and external SAR converters to protect timing margins of the critical loops.
What happens if SAR acquisition window is too short for my RC front-end?
If the acquisition window is shorter than the settling time of the RC front-end, the sampling capacitor does not reach the true input voltage before conversion begins. The result is an effective gain error that depends on signal amplitude and frequency, and in many cases a code-dependent nonlinearity that is hard to remove with simple calibration.
In motor and PSU systems this shows up as current or voltage readings that are accurate at low frequency but degrade during fast transients, high PWM duty cycles or large load steps. Different channels with different source impedances can exhibit different error patterns when time is insufficient for full acquisition.
A robust design either reduces source impedance, introduces a suitable buffer amplifier, lengthens the acquisition window or lowers the effective sampling rate so that the RC network and driver can settle within the allowed acquisition time.
Why does torque ripple increase when I reduce oversampling/averaging?
Oversampling and averaging reduce the random noise and quantisation error in measured phase currents. When oversampling is reduced, the instantaneous current estimates become noisier and the FOC current regulator reacts to this noise as if it were real torque demand, modulating the applied voltages more aggressively.
The result is increased torque ripple, especially at low speeds and light loads where the mechanical inertia does not fully smooth the effects of noisy control action. Similar effects appear in digitally controlled PSUs as increased output-voltage ripple or irregular switching patterns.
Oversampling and averaging should therefore be reduced only within the limits where current-loop bandwidth and latency remain acceptable, preserving enough smoothing to keep torque and voltage ripple inside the design targets.
Can DMA and ISR jitter ruin synchronous sampling?
Even with hardware-synchronised sampling, jitter in DMA transfers and interrupt service routines can disturb the effective timing seen by the control loop. If completion interrupts or DMA updates arrive at variable times relative to the control algorithm, some iterations may process older samples or see inconsistent sets of channel data.
For fast current loops this timing noise leads to apparent jitter in the estimated currents and can erode phase margin. In digital PSUs, excessive jitter in when new samples are consumed can show up as irregular duty-cycle adjustments and occasional overshoot or undershoot.
A robust implementation keeps ADC-related ISRs short and deterministic, gives them high priority, uses dedicated DMA channels and aligns the main control loop to a fixed time base that only processes complete, time-consistent sample sets.
How to debug wrong phase current signs due to ADC timing?
Wrong phase-current signs or inconsistent current vectors often originate from timing mismatches between PWM states and ADC sampling instants. The ADC may be sampling during a different conduction interval than assumed by the control algorithm, or channels may be associated with the wrong phase or sign convention.
A practical debugging approach is to run the motor at low speed or in a static test mode and then sweep the sampling point through the PWM period while monitoring measured currents against expected waveforms. Checking each ADC channel’s mapping to phase labels and verifying the polarity assumptions for shunt locations also helps identify sign inversions.
Once sampling instants, phase mappings and sign conventions are consistent with the power stage hardware, reconstructed phase currents and the resulting FOC variables converge to the expected behaviour.
Do I need differential inputs or is single-ended enough for motor drives?
Differential inputs are strongly preferred for sensing currents near high di/dt nodes and noisy grounds in motor drives and PFC stages. They provide common-mode rejection of ground bounce and switching-induced disturbances so that the ADC sees mainly the intended shunt or sense voltage.
Single-ended inputs can be sufficient in low-power, low-noise drives where shunts are close to the ADC and return paths are carefully controlled. In such cases, meticulous layout, Kelvin connections and clean reference routing are mandatory to avoid measurement errors caused by shared ground impedance.
For high-current, high-voltage or high-precision motor and PSU systems, differential or pseudo-differential inputs are usually a safer and more scalable choice.
How to calibrate offset and gain of SAR ADC in motor/PSU systems?
Offset and gain calibration in motor and PSU applications covers both the SAR ADC and its analog front-end. Offset is determined by measuring many samples at a known zero-input condition, such as zero phase current or a well-defined zero-voltage point, and averaging the result to estimate the residual code offset.
Gain is usually calibrated at one or two accurately known operating points, for example a reference current in a test phase or a precise output-voltage setting on a power supply. The measured codes are compared to the expected physical values to derive a scaling factor that converts raw codes into engineering units.
In production, these calibration factors are either programmed into non-volatile memory or reconstructed at start-up using built-in test routines. Calibration improves absolute accuracy and tracking over temperature but does not remove random noise or dynamic nonlinearity, so the underlying SAR selection and front-end design remain important.
Is 10-bit ADC enough for low-cost BLDC and flyback PSU?
A 10-bit ADC can be usable in low-cost BLDC drives and simple flyback PSUs where efficiency, torque smoothness and regulation accuracy targets are modest. For narrow current or voltage ranges, 10-bit resolution may provide sufficient granularity to implement basic control and protection.
However, 10-bit resolution limits the ability to handle wide dynamic ranges and fine adjustments. Low-speed torque control, very light-load operation and tight output-voltage specifications become difficult because each code step represents a relatively large change in current or voltage.
When the design requires smooth FOC behaviour, low acoustic noise, accurate efficiency optimisation or tight output regulation, a move to 12–16 bit SAR ADCs with adequate ENOB is usually justified.
Is voltage sensing required to be as tightly synchronised as current sensing?
Voltage sensing generally does not require the same level of tight synchronisation as current sensing in motor control, because bus and output voltages change more slowly than phase currents. Many designs sample voltages multiple times over several PWM periods and use averaging or simple filters to obtain stable readings for the voltage loop and monitoring functions.
An important exception is PFC input-voltage sensing, where the sampled voltage must track the mains waveform with a predictable phase relationship. Here, voltage sampling is still aligned to the line cycle and switching pattern, even though the timing constraints are less strict than for phase-current measurements.
In summary, current sensing demands strict PWM-synchronised sampling, while voltage sensing can be more relaxed but should still follow a consistent timing scheme, especially in PFC applications.
Can SAR ADC nonlinearity be ignored in motor and PSU control loops?
Small integral and differential nonlinearity can often be ignored in low-cost motor drives and basic PSUs where control targets are modest and other tolerances dominate overall performance. In such designs, quantisation noise, component tolerances and thermal effects frequently overshadow the impact of SAR nonlinearity.
In high-performance servo drives, precision motion systems and tightly regulated digital power stages, nonlinearity becomes more important. Distorted current or voltage measurements translate into harmonic content and bias in the control variables, which can increase torque ripple, acoustic noise or output-voltage distortion.
As soon as the specification includes low harmonic distortion, very low ripple or tight static and dynamic accuracy, SAR linearity should be treated as a design parameter and evaluated together with ENOB, noise, timing and front-end design.
