Working definition

A time-interleaved ADC is an architecture where several similar mid-speed ADC channels share the same analog input and sample it in a staggered way over time. Each channel captures different time instants of the same waveform, and the digital backend merges these samples into a single output stream that behaves like one high-speed converter.

The definition focuses on the sampling organization rather than the internal conversion principle of each channel. The subchannels can be implemented with SAR, pipeline, or other ADC cores, but as long as they operate with time-shifted sampling instants and their outputs are recombined into one ordered stream, the overall system forms a time-interleaved ADC.

N-channel interleaving and effective sampling rate

In an N-channel TI-ADC, each sub-ADC operates at a channel sampling rate f_s,ch. The channels sample the same input signal at equally spaced time offsets within one global sampling period. When the samples from all channels are interleaved in the correct order, the combined digital stream has an effective sampling rate of f_s,eff = N × f_s,ch.

Intuitively, the global timeline is divided into N interleaved phases. Channel CH0 samples at instants t = 0, T, 2T, …, channel CH1 samples at t = T/N, T + T/N, 2T + T/N, and so on, where T is the period associated with f_s,ch. Across one interval T, all channels together produce N samples at distinct time instants, so the quantized waveform behaves as if it were sampled N times faster than a single channel at f_s,ch.

Architectural essence: channels, clocks and reconstruction

At an architectural level, a TI-ADC can be viewed as three tightly coupled elements: a bank of matched ADC channels, a synchronized multi-phase sampling clock tree, and a reconstruction or de-interleaving logic in the digital backend. Each ADC channel typically includes its own sample-and-hold, core converter, and local calibration, and all channels see the same analog input node under well-controlled loading conditions.

The clock network generates N sampling phases that are phase-shifted by 360°/N with carefully controlled skew and jitter. These phases trigger the sampling instants of the sub-ADCs in sequence. On the digital side, a de-interleaver maps the channel-tagged samples back into a strictly increasing sample index order, forming a single high-rate digital data stream that can feed subsequent signal-processing blocks.

Why TI-ADC is used in multi-GSPS regimes

As target sampling rates move into the multi-GSPS range, a single monolithic ADC channel faces severe challenges in terms of front-end bandwidth, comparator speed, clocking, power consumption, and thermal management. Time-interleaving distributes the conversion task across several more moderate-speed channels, each operating closer to a feasible design point for the chosen process node and power budget.

This approach enables reuse of proven mid-speed ADC cores while achieving an effective sampling rate that would be very difficult or impractical for a single channel. As a result, TI-ADC architectures are widely used in wideband oscilloscopes, high-speed data-acquisition cards, broadband communication receivers, and other applications that demand multi-GSPS conversion with useful resolution.

Boundaries vs RF-sampling, Flash and Pipeline ADCs

The term time-interleaved ADC describes how sampling is organized in time and how multiple channels are combined. It is orthogonal to both the internal conversion principle and the application frequency band. An RF-sampling ADC is named according to its ability to directly capture RF input bands; such an ADC may internally use TI techniques, but RF-sampling describes the input bandwidth and use case, not the interleaving itself.

Flash and pipeline ADCs are named by their conversion core topology. A single-channel flash or pipeline ADC can be used without interleaving, or multiple flash or pipeline channels can be time-interleaved to reach higher effective sampling rates. In other words, TI-ADC sits at the architectural organization level, while SAR, pipeline or flash describe channel-level conversion mechanisms, and RF-sampling refers to the front-end bandwidth class. Keeping these naming boundaries clear helps avoid confusion when evaluating high-speed ADC data sheets and system architectures.

1 Multi-channel interleaving structure

In an N-channel TI-ADC, channels CH0 through CH(N-1) form a bank of similar ADC slices. Each slice contains its own sample-and-hold network and converter core, but all slices are designed to present closely matched gain, bandwidth, noise, and linearity. The analog input is routed to every channel under controlled loading so that each slice observes the same waveform within the intended signal bandwidth.

A single master clock source generates the sampling phases for all channels. Rather than running one channel at an extreme clock rate, the master clock is divided or phase-shifted into N sampling phases that are evenly spaced over one overall sampling period. Conceptually, CH0 samples at phase 0, CH1 at 1⁄N of the period, CH2 at 2⁄N, and so on. When the digital backend reorders the channel-tagged samples into a single sequence, the effective sampling rate becomes fs,eff = N × fs,ch, where fs,ch is the per-channel sampling rate.

The sample-and-hold and input driver topology strongly influences the robustness of interleaving. A fully shared front-end sample-and-hold offers excellent matching at the cost of higher input capacitance and drive requirements. Independent sample-and hold stages per channel reduce the burden on a single front-end but introduce more places where offset, gain, and bandwidth mismatches can appear. Similarly, a shared driver that fans out to multiple channels creates routing and loading asymmetries that can translate into timing skew and gain differences if not carefully controlled.

Time skew originates wherever different channels see different propagation delays between the master clock edge and the actual sampling instant on the input capacitor. Typical contributors include unequal clock-tree branch delays, differences in buffer chains, variations in switch device sizes and parasitics, and mismatches in routing length or dielectric environment. Skew can also drift with temperature, supply voltage, and aging because delay elements rarely track perfectly across the die. Even picosecond-level skew becomes critical when the input signal has sub-nanosecond transitions and multi-GSPS sampling rates.

2 Three primary mismatch mechanisms

The quality of a TI-ADC is dominated by how well its channels match. In practice, three mismatch classes are most important: offset mismatch, gain mismatch, and timing mismatch. Offset mismatch mainly produces low-frequency artifacts, gain mismatch modulates the signal amplitude, and timing mismatch couples directly to the signal slope and tends to dominate distortion at high input frequencies.

Offset mismatch: even–odd pattern

Offset mismatch arises when channels have different DC offsets at their outputs. During interleaving, this appears as an alternating bias on consecutive samples. For an input sine wave, the reconstructed time-domain waveform exhibits a characteristic even–odd stepping pattern, often called a “cat-ear” shape. In the frequency domain, offset mismatch generates spurious tones near half the interleaving frequency and its harmonics. The underlying causes include offset in sample-and-hold circuits, comparator thresholds, residue amplifiers, or digital offset trims that are not perfectly aligned across channels.

Gain mismatch: periodic amplitude modulation

Gain mismatch occurs when channels have slightly different conversion gains. As the interleaving pattern cycles through the channels, the effective amplitude of the reconstructed waveform is periodically modulated. This periodic modulation introduces sidebands around the input tone and produces spurious components related to the interleaving frequency. Gain mismatch often originates from capacitor value spread, front-end resistance variations, channel-to-channel bandwidth differences, and non-identical loading of the input driver. The impact increases with input frequency as bandwidth-induced gain errors diverge across channels.

Timing mismatch (skew): dominant high-frequency error

Timing mismatch, or skew, is the most harmful mismatch mechanism in high-speed interleaved systems. Skew appears when channels sample the input at slightly different time instants than intended, even though the nominal phase spacing is ideal. For a small timing error delta t, the sampled value can be approximated by x(t + delta t) ≈ x(t) + delta t · (dx/dt). The error term is proportional to the instantaneous slope of the signal; as a result, skew produces distortion that grows rapidly with input frequency. High-frequency tones generate strong intermodulation products and SFDR degradation, and the resulting spurs are often the limiting factor for usable dynamic range in multi-GSPS TI-ADCs.

Jitter versus skew in time-interleaved systems

Clock jitter and timing skew are related but distinct phenomena. Jitter is the random variation of sampling instants around their ideal positions and mainly raises the broadband noise floor, reducing SNR as input frequency increases. Skew is a deterministic timing offset between channels that repeats from cycle to cycle and therefore produces discrete spurs and intermodulation products. In a TI-ADC, shared clock-source jitter affects all channels in a correlated way and behaves similarly to jitter in a single-channel converter, whereas channel-specific skew directly exposes the interleaving structure and typically dominates the spurious-free dynamic range.

1 Analog channel matching

Analog matching targets identical behavior across all TI-ADC channels. The input driver must fan out to each channel with symmetrical routing so that every converter sees the same load and propagation delay. Differences in trace length, metal layer usage or proximity to passive components translate into channel-to-channel variations in gain, bandwidth and timing skew, which later appear as distortion and spurs in the reconstructed signal.

Sample-and-hold stages should use matched switch devices, sampling capacitors and biasing across channels. Any mismatch in the RC time constant of the sampling path creates frequency-dependent gain differences, while mismatched charge injection or leakage leads to offset mismatch. Layout symmetry, including mirrored placement and identical routing around the sampling capacitors, is critical for minimizing these effects over process, voltage and temperature.

The input buffer topology must be chosen with interleaving in mind. A shared buffer that drives all channels offers strong correlation and better tracking but has to handle higher capacitive load. Split buffers reduce the load on each amplifier but introduce more opportunities for gain, bandwidth and timing mismatch if the individual stages do not track perfectly. In both cases, consistent biasing and careful control of loading are essential.

Power distribution should isolate sensitive analog nodes from digital switching currents while preserving symmetry across channels. Local regulation, distributed decoupling and balanced supply routing help avoid situations where the dynamic current drawn by one channel modulates the reference or bias conditions of neighboring channels. Without such precautions, the TI-ADC can exhibit time-varying offset and gain mismatch that standard foreground calibration cannot fully remove.

2 Clock distribution

The clock network in a TI-ADC must generate and distribute multiple sampling phases with tight control over skew and jitter. A multi-phase clock generator, often based on a PLL or DLL, produces N evenly spaced phases from a single frequency reference. These phases are aligned to a common origin so that channel sampling instants can be treated as ideal 1⁄N subdivisions of one effective sampling period.

Skew, bias and phase errors arise along the distribution path between the clock generator and the sampling switches in each channel. Any difference in buffer count, loading, routing length, or local supply condition changes the delay experienced by a given clock edge. These small deviations accumulate and translate into channel-to- channel skew that cannot be removed by simple phase alignment at the generator output alone.

A low-jitter PLL and well-designed clock distribution network are therefore mandatory. Shared jitter from a common PLL behaves similarly to jitter in a single-channel ADC and primarily limits SNR at high input frequency. In contrast, uncorrelated jitter or skew between channels directly exposes the interleaving structure and shows up as spurs. Using a single master PLL with carefully matched branches is usually superior to independent clock sources per channel.

The physical clock tree layout should follow a balanced structure, such as an H-tree, to equalize propagation delay to each channel. Symmetric routing, identical buffer stacks and consistent shielding around clock lines reduce sensitivity to process and thermal gradients. The final segment, from the last buffer to the sampling switch gate, is especially critical, because any asymmetry here directly translates into effective sampling-time skew.

3 Calibration hooks

Calibration support is essential for any practical TI-ADC. Offset calibration removes channel-to-channel DC differences. It can be implemented as a foreground routine, where the converter is taken offline to measure offsets with controlled inputs, or as a background routine that runs concurrently with normal conversion. Background offset tracking is important in environments where temperature and supply conditions drift over time.

Gain calibration typically uses tone-based measurements or adaptive algorithms such as LMS. Known calibration tones are injected into the channels, and the relative amplitudes are compared to derive per-channel gain correction. Because gain error often depends on frequency, a wideband design benefits from calibration at multiple tones across the intended signal band rather than at a single test frequency.

Timing calibration focuses on estimating and compensating channel skew. Estimators may operate on derivatives of the signal, on correlation between channels, or on more advanced models including machine-learning based approaches. In all cases, the timing error is translated into an equivalent amplitude correction that depends on the local slope of the waveform. Because delay varies with operating conditions, a useful timing-calibration scheme must support background operation and periodic refinement.

Foreground calibration is suited to controlled environments or production trimming, where conversion can be paused without impacting service. Background calibration is preferred in communication, radar and industrial systems that must run continuously. Multi-tone or broadband calibration campaigns provide better visibility into frequency-dependent mismatch and are often required to achieve the specified SFDR across the full Nyquist band.

4 Digital reconstruction chain

The digital backend of a TI-ADC converts channel-indexed samples into a single ordered stream suitable for downstream processing. A de-interleaving FIFO accepts data from each channel and writes them into the correct sample positions based on the interleaving pattern. This stage must preserve timing order and maintain deterministic latency so that later stages such as digital downconversion and filtering can operate correctly.

Reconstruction filters are often implemented as FIR or polyphase structures. They can suppress interleaving-related spurs, provide per-channel equalization and implement sample-rate conversion. When combined with the calibration coefficients, these filters can jointly correct residual offset, gain and timing errors and smooth the transition between calibration updates and normal operation.

Equalization compensates for channel-to-channel bandwidth and phase variations. Digital taps applied per channel or per phase align the effective frequency response before samples are merged. In wideband communication receivers, the reconstructed stream typically feeds a digital downconverter and numerically controlled oscillator so that RF or IF input signals can be translated to baseband and decimated to a lower data rate.

5 PCB layout considerations for TI-ADC

TI-ADC performance is highly sensitive to PCB layout. Analog input traces, clock lines and sampling gate drive paths must be matched in length and environment so that external routing does not introduce additional skew between channels. Differences in via count, reference plane transitions or coupling to nearby components can easily create picosecond-level delay mismatches that become visible as spurs at high input frequencies.

The layout from package pins to each channel’s front-end should follow a symmetric pattern, including mirrored placement, equal trace length and consistent impedance. Careful placement of the ADC near its reference and clock source reduces loop area and exposure to external interference. Power and reference routing require isolation between noisy digital regions and sensitive analog domains, with local decoupling kept as symmetric as possible across channels.

Thermal gradients on the PCB and within the package can cause channel parameters to drift differently over time. Heat sources such as regulators, power stages and high-current traces should be placed away from the multi-channel ADC region, and airflow or heatsinking should be arranged to avoid strong temperature differences from one side of the device to the other. Good electromagnetic compatibility practices, including ground stitching, controlled return paths and shielding around high-speed clocks, further reduce susceptibility to radiated and conducted noise.

1 Broadband digital oscilloscopes (multi-GSPS)

Modern broadband digital oscilloscopes need to capture fast transient waveforms with several gigasamples per second and input bandwidths from a few hundred megahertz up to multiple gigahertz. Users expect to observe single-shot events, not just averaged or reconstructed waveforms. The front-end therefore requires true wideband sampling with sufficient instantaneous dynamic range and low distortion across the full input span.

In this regime, designing a single monolithic ADC channel with multi-GSPS sampling rate and 8 to 10 bits of effective resolution quickly runs into limits in comparator speed, analog bandwidth, power and heat dissipation. Practically, high-end scopes achieve their effective sampling rate by interleaving several moderate-speed channels per acquisition path. Time-interleaved ADCs therefore form the backbone of multi-GSPS oscilloscope front-ends, making TI-ADC the de facto choice for wideband digital oscilloscopes above the gigasample-per-second range.

2 Communication receivers (sub-GHz to few GHz)

Communication receivers cover a range of architectures, from traditional superheterodyne designs with narrow IF bands to wideband software-defined radios that sample large portions of the spectrum. At lower and mid IF frequencies, sampling rates in the hundreds of megasamples per second can often be covered by single-channel pipeline or SAR converters, sometimes combined with multiple synchronized ADCs rather than a time-interleaved architecture.

As architectures move toward wideband IF-sampling or direct RF-sampling, the requirements shift to multi-GSPS sampling with 10 to 14 bits of resolution and tight SFDR across a wide Nyquist band. In these systems, the combination of bandwidth, dynamic range and power budget makes multi-GSPS TI-ADCs the dominant solution. For narrowband or moderate-rate receivers, TI-ADC remains a useful option but not the only one; for very wideband RF-sampling front-ends, TI-ADC is effectively required to reach the target performance.

3 Radar front-ends (IF and RF sampling)

Radar systems span automotive, industrial and defense applications, with front-ends that must handle high-frequency waveforms and preserve phase coherence across many channels. IF-sampling radar architectures downconvert the RF carrier to a lower IF, then digitize at sampling rates on the order of tens to hundreds of megasamples per second. These systems may use multiple synchronized ADC devices without necessarily relying on time-interleaving within each device.

In contrast, wideband or direct RF-sampling radars place much higher demands on sampling rate and bandwidth. When IF or RF content extends into the hundreds of megahertz or beyond, and when many channels must be digitized simultaneously for beamforming, TI-ADCs provide a feasible path to multi-GSPS sampling with controlled power and area. For high-resolution, wideband radar front-ends operating in these regimes, time-interleaving becomes the primary practical route to achieving the required sampling performance per channel.

4 Ultrasound and imaging arrays (high frame rate)

Ultrasound and imaging arrays combine many receive channels with stringent timing and dynamic-range requirements. Conventional medical ultrasound often uses dozens or hundreds of channels, each sampling at tens of megasamples per second, implemented with multi-channel SAR or sigma-delta converters. In this regime, large channel counts are more critical than extremely high per-channel sampling rate, and time-interleaving is not always necessary.

High-frame-rate or wideband ultrasound systems, as well as certain high-speed line scan and imaging applications, drive per-channel sampling requirements higher while retaining many synchronized channels. When per-channel rates move toward hundreds of megasamples per second or beyond, TI-ADCs can concentrate high-speed conversion into fewer physical slices and use digital multiplexing or aggregation to manage the data flow. In such high-throughput configurations, time-interleaving becomes an important option for balancing channel count, sampling rate and power.

5 High-speed spectrum and signal analyzers

Spectrum and signal analyzers have traditionally relied on multi-stage analog downconversion to translate high-frequency signals to a narrow IF before digitization. This approach allows the use of relatively slow but high-resolution converters. Newer wideband and real-time analyzers aim to capture large instantaneous bandwidths, sometimes exceeding one gigahertz, and to process complex modulated signals in the digital domain in near real time.

To achieve these wide capture bandwidths with sufficient SFDR and ENOB, analysis front-ends increasingly use multi-GSPS TI-ADCs combined with flexible digital downconversion and channelization. In this class of instruments, time-interleaving is effectively required to reach the joint goals of bandwidth, resolution and processing flexibility. Single-channel ADCs would either fall short in speed or demand impractical levels of power and cooling.

6 When TI-ADC is the only practical option

Across these applications, a common pattern emerges. When a system demands sampling rates at or above a few gigasamples per second, wide analog bandwidth, and effective resolution in the 8 to 12 bit range, single-channel architectures become difficult to implement within realistic power and thermal budgets. Time-interleaving then moves from a convenient performance booster to the only practical way to achieve the required sampling rate and dynamic range on a given process technology.

In contrast, applications with moderate sampling rates and narrower bandwidths can often choose between TI-ADC and alternative architectures such as multi-channel single-converter devices, conventional IF-sampling, or superheterodyne receivers. Here, time-interleaving becomes one option among several, selected based on trade-offs in integration level, calibration complexity, system cost and risk. Clear separation of these regimes helps designers decide whether TI-ADC is mandatory for a given project or simply a strong candidate to optimize performance and integration.