COT / Valley-Switching Buck Regulator ICs
Fast transients, inherent feed-forward, and high conversion-ratio efficiency for modern DC/DC buck regulator ICs.
Intro — What it is and where it fits
Constant-On-Time (COT) and valley-switching buck control keep each on-time fixed and trigger the next pulse at the inductor “valley.” The result is ultra-low loop latency and a frequency that adapts with Vin, giving near-inherent feed-forward for line changes. This page focuses on buck regulator ICs using COT/valley techniques—when to use them, how to stabilize sensing ripple, and how to size components for fast steps.
Principle — How COT/Valley control works
In COT control, each switching pulse has a fixed on-time Ton. Output voltage follows duty ratio D ≈ Ton/(Ton+Toff). When Vin changes, the controller adjusts Toff (and thus frequency), yielding a near-feed-forward line response. Valley switching triggers the next pulse at the inductor current or SW-node voltage “valley,” minimizing delay.
Architectures — True/Emulated COT, D-CAP, and Valley differences
Within the COT/valley family of buck regulator ICs, implementations differ in how Ton is created, how ripple is guaranteed for the comparator, and how valleys are detected. Use the cards below to pick a strategy.
Analog or external network defines fixed Ton. Frequency glides with Vin. Fast transients but needs reliable ripple (ESR/RC/DCR) and respects Ton,min/Toff,min.
Mixed-signal emulation of fixed Ton to tame jitter/limits. Lower ripple dependency than true COT. Often paired with valley trigger for low delay.
Vendor COT variants that internally manage ripple and light-load behavior across generations. More “out-of-box” stability; details vary by revision.
Next pulse at inductor-current or SW-node voltage valley. Impacts light-load acoustics and OCP interaction; artificial ramp may still be required.
Design — Copy-ready formulas & checks
Use this step-by-step path to size Ton, choose L/C/ESR, guarantee ΔVsense for the comparator, respect minimum on/off times, and meet load-step targets before loop tuning.
- Set Ton / frequency window. Choose fSW,target, then
T_on,set ≈ Vout / (Vin_nom · fSW_target). Check limits:T_on,set > T_on,min(IC),T_off,set > T_off,min(IC)at Vin,max. - Choose inductor ripple. Target
ΔI_L ≈ (Vin − Vout)·D/(L·fSW)= 0.2–0.4·Iout(max). Too-low ripple hurts sensing. - Size output caps for static ripple & first-hit transient.
ΔV_ripple ≈ ΔI_L·ESR + ΔI_L/(8·C·fSW). For load steps:C_min ≈ I_step · dt_allow / ΔV_allow(refine by measurement). - Guarantee comparator trip margin. Ensure
ΔV_sense ≥ 1.3–1.5 × V_th(min). If natural ripple is insufficient → inject a ramp (ESR / RC from SW / DCR sensing). - Handle min on/off constraints. If
T_on,set ≤ T_on,minorT_off,set ≤ T_off,min: lower frequency, change IC family (Emulated/D-CAP), or adjust Vout/filter plan. - Light-load acoustics. Pick Forced-PWM (predictable EMI) vs Auto-PFM (efficiency). Use mild ramp, raise frequency, or add a small preload if needed.
- EMI & snubber quick-start. Minimize hot loop first. Estimate snubber by ring frequency fr; coarse start: sweep C, then pick R near critical damping—watch dissipation.
- Layout sanity. Keep ripple-sense return local; isolate SW noise from sense/COMP; separate BST/DRV from high-di/dt nodes.
- Validation matrix. Line steps ±10%; load steps 10%↔80% (≥1 A/µs); EMI 150 kHz–30 MHz; corners (low/high temp; Ton/Toff edges); light-load acoustics.
Layout — Ripple sensing, hot/switching loops, snubber & EMI
COT/valley buck regulator ICs are highly sensitive to the ripple seen by the comparator and to the physical area of high di/dt loops. Follow these layout rules to stabilize trips, minimize ringing, and ease EMI filtering.
Use single-point ground for the sense network. Keep RC/ESR/DCR components close to the IC pin. Route away from SW; add ground guard if needed.
Minimize the HS-FET/LS-FET/Cin loop. Place small ceramics tight to FETs. Keep the SW copper only as large as needed; avoid inner-layer traces under SW.
Use close gate resistors to tune slew. RC snubber across SW–PGND for ringing; keep the snubber loop short. Watch snubber power (C·V²·fSW).
Split PGND/AGND with a star point at the IC reference. Keep input EMI filters at the connector side; consider shielded inductors and damping.
Validation — Transient, line, jitter spectrum, and acoustics
Use this validation matrix to prove COT/valley buck regulator IC performance before full certification. Cover load/line steps, frequency behavior, EMI pre-scan, and audible noise.
Undershoot/overshoot ≤ target mV; settle within ±X% in Y µs.
No protection misfire; frequency glides as expected with Vin.
No sub/over-harmonic behavior; bounded glide window.
PFM SPL below threshold; no periodic chirp/whine.
ICs — Seven-brand families & selection matrix
Use this matrix to shortlist buck regulator IC families based on control style (True/Emulated COT, D-CAP), ripple strategy, minimum on/off time severity, and light-load behavior. Then validate against your Vin/Vout/Iout window, EMI and thermal constraints.
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FAQ — Engineering Q&A (COT/Valley buck ICs)
Practical answers for ripple sensing, minimum on/off limits, light-load acoustics, EMI, and validation. Each item ends with a pointer to a relevant section.
1) High Vin/low Vout breaches Ton,min. What are my options?
Lower the target switching frequency, switch to a family with shorter Ton,min, or use an external Ton-set network if supported. Consider multi-phase or an intermediate rail to ease duty. Always re-check Toff,min at Vin,max to avoid bursty behavior. See: #design.
2) Not enough ESR for a clean comparator trip—how to fix?
Inject an artificial ramp: sample SW via RC to the sense node or use inductor-DCR filtering (R·C ≈ L/DCR). Aim for ΔVsense ≥ 1.3–1.5×Vth(min) with layout-local AGND return and guard ground to avoid SW coupling. See: #design, #layout.
3) COT frequency glide hurts EMI planning—what’s the strategy?
Design filters with margin and damp input LC; use shielded inductors and RC snubbers near SW. Gate-resistor tuning reduces slew-induced ringing. Spread-spectrum (if available) plus minimized hot loop collapses peaks. See: #layout, #validation.
4) Audible chirp at light load—how do I mitigate it?
Prefer Forced-PWM if fixed frequency is mandatory; otherwise, raise nominal fSW slightly, add a mild artificial ramp, or a small preload. Verify SPL at 10/30 cm and ensure no tonal spikes. See: #design, #validation.
5) Valley current vs valley voltage detection—practical differences?
Current-valley trigger aligns with inductor dynamics and can reduce delay; voltage-valley uses SW node, simpler but more layout-sensitive. Either way, ensure adequate ripple and proper filtering to prevent multi-pulsing. See: #architectures.
6) Why is COT called “near feed-forward,” and when does it fail?
Fixed on-time lets the controller adapt off-time to Vin, effectively pre-compensating line steps. It breaks down at Ton,min/Toff,min limits, with extreme slew, or excessive loop/driver delays. See: #principle.
7) Starter values for RC-from-SW ramp and key routing tips?
Begin with R = 10–100 kΩ, C = 100–680 pF, then tune for margin and phase. Place parts next to the sense pin; local AGND return; short traces with ground guard; avoid crossing split planes. See: #design, #layout.
8) Multi-phase with COT—how to keep phases in line and share current?
Use sync or phase-interleaving features when available; match ramp and sense networks per phase; keep common nodes low-impedance. Probe each phase current to confirm sharing across load and temperature. See: #architectures, #validation.
9) First-cut output capacitance for load steps—what’s the quick path?
Ignore loop first: estimate Cmin ≈ Istep·tallow/ΔVallow and check ESR-driven ΔV. Then simulate/measure to refine. Keep a headroom for temperature/bias derating. See: #design.
10) Snubber starting values and power check?
Measure SW ringing frequency, sweep C to reduce the peak, then choose R near critical damping. Estimate dissipation with P ≈ C·V²·fSW and verify thermals; place snubber tight to SW–PGND. See: #layout.
11) When to force PWM instead of PFM?
Choose FPWM when EMI filters or acoustics require a fixed frequency. Accept the efficiency penalty at light load, or raise the boundary where PFM engages to keep noise outside audible bands. See: #design, #validation.
12) Real-world differences: D-CAP vs True/Emulated COT?
D-CAP families tend to embed ripple handling and polish light-load behavior, reducing tuning effort. True/Emulated COT may deliver marginally faster response but need explicit ramp design and tighter layout discipline. See: #architectures.
13) Detecting multi-pulsing or metastability—what to look for?
On step response, watch for irregular short pulses, toggling around valley points, or comparator chatter. Increase ΔVsense, enforce minimum pulse width, or add damping to the ramp network. See: #validation, #design.
14) Which waveforms matter most to capture during validation?
Log Vout undershoot/overshoot and t_settle, SW waveform with ringing and valley markers, fSW glide vs Vin, and a period-jitter histogram. Store exact IC mode (PFM/FPWM), snubber/gateR settings, and temperatures. See: #validation.
