• Speed: decision time depends strongly on overdrive and node capacitances.
• Energy per decision: dynamic action limits static power, but evaluate pulses draw peak current.
• Error & disturbance: input-referred uncertainty and kickback must be managed at the interface.

• SAR ADC comparator: repeated decisions make energy/decision critical; decision window is clock-defined.
• TDC arbiter / race detector: small arrival-time differences require fast, symmetric regeneration.
• Time pickoff / ToF echo gating: extracts a timing event from a threshold crossing with a defined evaluate moment.
• Low-VDD fast thresholding: dynamic latch can outperform biased solutions when static current is constrained.

• Use a StrongARM-type latch when a clocked decision window is acceptable and speed/energy-per-decision dominate.
• Plan mitigation when the source is high impedance or sampling-sensitive: treat kickback as a first-order interface risk.
• Expect tails at small overdrive: metastability-like long delays must be guarded by timing margin or re-sampling.

• Input pair: converts ΔVin into a small node imbalance; limits appear at low VDD and extreme common-mode.
• Regenerative core: sets the speed/overdrive relationship; asymmetry turns into systematic offset and decision bias.
• Reset / precharge: prevents “memory” and correlation; incomplete reset creates history-dependent thresholds.
• Output nodes: define the time constant and metastability tail; loading and sampling timing must be budgeted.

• Preamp-latch: improves small-overdrive decisions and reduces kickback; costs power/area and adds its own noise budget.
• Input isolation: protects high-impedance sources and sampling networks; costs bandwidth and adds input capacitance.
• Hybrid assist: adds static bias or controlled gain to stabilize corners; costs static current and complexity.

• Output nodes: return to a defined level (or near-zero differential) so each decision starts from the same baseline.
• Regeneration core: remove residual charge that would otherwise bias the next decision (“memory”).
• Symmetry: ensure both sides see comparable reset strength; asymmetry behaves like systematic input offset.

• t0: the effective evaluate edge at the latch core (clock arrival + internal gating).
• t_valid: the moment OUTP/OUTN is valid for the next stage (crossing or sufficient swing).
• t_decision = t_valid − t0: the time budget that must be met across overdrive and corners.

• History-dependent decisions → incomplete reset leaves charge (“memory”) → lengthen reset time or lower clock rate and confirm the bias collapses.
• Bias at near-zero input → clock feedthrough creates a fake initial imbalance → change clock swing/edge rate and check whether the decision bias tracks the clock.
• Threshold shifts across modes → duty-cycle changes reshape reset/evaluate overlap → hold reset width constant and sweep duty to see if the threshold moves.

• t_reset_min: shortest reset that eliminates memory and bias.
• t_eval_to_valid: evaluate-to-valid latency under the minimum expected overdrive.
• valid_condition: what the next stage uses as “valid” (crossing, swing threshold, or FF input limit).
• clock_sensitivity: qualitative note on swing/edge-rate/duty dependence.

• Growth: ΔV(t) ≈ ΔV0 · e^(t/τ)
• Time-to-valid: t_decision ≈ τ · ln(ΔV_target / ΔV0)
• What sets τ: stronger transconductance (gm) and smaller effective node capacitance shorten τ.

• ΔV0 is the start line: smaller ΔV0 requires more exponential gain-time to reach the same ΔV_target.
• ln(1/ΔV0) grows fast: below a certain overdrive, timing tails dominate worst-case latency.
• Engineering implication: do not qualify only “typical” delay—review t_pd versus overdrive and corners.

• t_pd(OD): delay versus overdrive across PVT and load conditions.
• Minimum OD: smallest overdrive that still meets timing with acceptable tail risk.
• Decision margin: define “valid” at the digital interface (crossing or swing threshold) and budget to that point.

• Mismatch (layout/sizing): input pair mismatch, cross-coupled asymmetry, and unequal switch injection create a systematic bias.
• Charge memory (reset/timing): incomplete reset leaves residual charge, making the next decision depend on the previous result.
• Clock injection (clock routing/edge): feedthrough can create a “fake” ΔV0 at t0, especially when the true overdrive is small.
• Supply & ground bounce (PDN/layout): evaluate current steps shift internal bias points and appear as input offset during the decision window.

• Offset changes with duty/reset width: prioritize charge memory and reset asymmetry; lengthen reset and verify the bias collapses.
• Offset changes with clock swing/edge rate: prioritize clock injection; compare slow/fast edge conditions and check sign consistency.
• Offset worsens at low VDD / high T: prioritize PVT sensitivity; reduced headroom and gm magnify asymmetries and injection artifacts.

• VOS_mismatch: systematic bias from mismatch (Monte Carlo + temperature trend).
• VOS_memory: bias that depends on reset width, frequency, or decision history.
• VOS_clk: bias that tracks clock swing/edge/duty (feedthrough dominated).
• VOS_PDN: bias that tracks supply ripple or ground bounce during evaluate.

• kT/C at reset: thermal noise sets a baseline differential at the start of evaluate.
• Device noise in evaluate: input pair and regeneration devices inject random perturbations during the most sensitive window.
• Regeneration randomness: with very small initial imbalance, random perturbations can determine the winner.
• Supply coupling: PDN ripple and ground motion modulate the internal operating point and appear as threshold spread.

• σV,in defines an uncertainty band around the ideal threshold.
• If the minimum expected overdrive is not comfortably larger than σV,in, worst-case latency and wrong decisions increase.
• Voltage uncertainty becomes timing uncertainty when the input slope is finite (edge pickoff and TDC-style uses).

• σV,in: input-referred threshold spread under the operating clock and load.
• dominant_window: which part of evaluate is most sensitive (early evaluate is often critical).
• PSU coupling note: qualitative sensitivity to supply ripple/ground motion during evaluate.
• mapping: SAR (code noise/spurs) or TDC (time jitter) as the primary risk indicator.

• Input-pair gm: VICM shifts VGS headroom; weak inversion or linear-region operation reduces gm and slows regeneration.
• Device VDS headroom: limited VDS in low-VDD corners reduces effective gain and increases sensitivity to mismatch and injection.
• Regen core strength: when VDD is low, the cross-coupled pair has less overdrive and the decision tail worsens at small input overdrive.

• “Works but slow”: the latch still flips, but t_pd grows sharply in corners because gm collapses near the rails.
• “Works but biased”: near-rail operation magnifies clock/reset injection, creating apparent offset drift versus duty and edge rate.
• “Does not start”: regeneration is too weak at VDD_min and the output never reaches a valid digital level in time.

• VICM_min @ VDD_min, T_max and VICM_max @ VDD_min, T_max.
• t_pd @ VICM corners: mid-VICM and near-rail points under minimum expected overdrive.
• offset sensitivity vs VICM: whether bias grows rapidly near either rail.
• fail signature: no-flip, slow-tail, or biased decisions.

• Capacitive coupling: internal regen/output node swings couple through Cgd/Cin back to VINP/VINN.
• Switch injection: reset/isolation devices inject unequal charge, creating a differential glitch.
• CM → DM conversion: common-mode input motion converts to differential error due to imperfect symmetry.

• Sampling corruption: the held voltage shifts during the compare window.
• Code-dependent error: the disturbance depends on internal state and decision history, producing deterministic spurs.
• R_source sensitivity: higher source impedance increases glitch amplitude and settling time, worsening SFDR/ENOB.

• R / RC at input: simplest damping; costs settling time and may raise noise.
• Isolation / sampling network: add isolation switch or adjust C; costs kT/C and complexity.
• Preamp-latch: isolates kickback at the cost of power and area.
• Shield / bootstrapped: strongest suppression but highest design and verification burden.

1. Hold the input at a stiff level and toggle only the comparator clock; look for a clock-synchronous input glitch.
2. Change source impedance (or add a small series R); verify whether spur/instability scales with R_source.
3. Shift the evaluate timing relative to sampling; confirm whether the problem moves with the decision window.

• Edge rate: changes feedthrough and the consistency of evaluate release; asymmetry can look like effective offset.
• Clock swing: changes injection strength and internal node kick; sensitivity often increases near rails and low VDD.
• Duty cycle: changes effective reset time and reset–evaluate overlap, which can reintroduce memory and correlated spurs.

• Complete: residual charge must collapse so the next decision is not history-dependent.
• Symmetric: reset and precharge should not inject unequal charge that becomes ΔV0 bias.
• Isolated: reset activity should not disturb the input network or PDN during the compare window.

• With small initial imbalance, regeneration needs more time to separate the nodes; decision-time becomes a distribution with a long tail.
• A fixed capture delay can be unsafe; the sampling instant must be placed beyond the tail onset with explicit guardband.
• Downstream SR latches or flip-flops must meet setup/hold with the comparator output already in a valid digital region.

• clk_swing, edge_rate_class, duty_range_supported.
• t_reset_min (condition that removes memory) and history_dependency (yes/no + notes).
• sampling_instant (relative to evaluate start) and guardband_margin (tail-aware margin).

• Node ownership: the comparator sees the CDAC top-plate behavior during switching; compare only after the node is settled.
• Phase separation: ensure switching transients do not overlap the evaluate window (non-overlap is a requirement, not an optimization).
• Kickback isolation: select the lightest mitigation (R/RC → isolation → preamp) that meets SFDR and settling targets.
• Decision-time budget: include worst-case small-overdrive bits and a tail-aware capture margin from the downstream latch/FF.

• Path symmetry: edge A and edge B must see matched routing, buffering, and loading; mismatch becomes time offset.
• Async handling: define how the arbiter result enters the clock domain (metastability must be contained, not ignored).
• Tail-aware capture: small effective overdrive and slow input slopes increase tail risk; sampling windows must include guardband.

• compare_window, settling_margin, kickback_mitigation_level (SAR).
• path_skew_budget, input_slope_class, sync_strategy_note (TDC).
• capture_point and guardband (tail-aware for both).

• Offset: run PVT and mismatch MC; record mean/σ and any tail behavior under near-rail VICM and VDD_min.
• t_pd(OD): sweep overdrive in 3 bins (small / medium / large); include worst-case corners and duty/edge-rate bins.
• Metastability tail flag: under small overdrive, check if decision-time distribution develops a long tail; plan capture guardband accordingly.
• Kickback estimate: extract input-referred disturbance (symmetry and scaling with input capacitance/source impedance).

• Symmetry & matching: mirror the input pair, cross-coupled core, and reset devices; keep parasitic imbalance minimal.
• Shield & separation: keep CLK and large-swing OUT nodes away from VIN nodes; use shielding routes where coupling is unavoidable.
• Clock routing consistency: matched path length and loading for clock/reset distribution to stabilize the evaluate start condition.
• Ground-bounce control: short return loops and local decoupling to reduce input-referred offset caused by transient current spikes.

• t_pd vs OD: measure delay distribution (p50/p99) at small/medium/large OD; record tail presence and capture recommendation.
• Kickback: hold VIN with a stiff source and toggle only CLK; measure input glitch peak and symmetry; repeat with R_source bins.
• Metastability tail: force very small OD and capture a histogram-like delay distribution; place sampling instant beyond the tail with guardband.
• Reset memory: sweep reset width/duty; check for history dependence (bias or spur moves with duty/edge).

• Corner guardband: base capture timing on p99 + margin at worst-case small OD and VDD_min/T_max.
• Temperature drift note: track whether offset/tail/kickback worsen at hot/cold extremes.
• Supply-noise sensitivity: record whether ripple or ground bounce shifts decision behavior or increases tail risk.
• Minimal bins: lot, VDD bin, temperature point, t_pd bin, tail flag, kickback flag.

• Energy per decision and repeatable evaluate start.
• t_pd at small overdrive (tail-aware capture margin).
• Kickback amplitude and symmetry seen by the CDAC/top-plate node.
• VICM window and near-rail sensitivity at VDD_min/T_max.

• Kickback corrupts sampling and creates code-dependent spurs.
• Compare phase overlaps switching transient (insufficient non-overlap).
• Small-OD tail causes intermittent wrong decisions when capture is too early.

• Light: non-overlap phases + small R/RC damping if settling margin exists.
• Medium: isolation switch / adjusted sampling network to limit kickback into the top-plate.
• Heavy: preamp-latch interface when R_source is high or spur targets are strict.

• Input slope tolerance and threshold uncertainty (tail risk under slow edges).
• Clock/reset consistency to stabilize the evaluate start.
• Supply/ground transient sensitivity (false trigger risk).

• Slow-ramp inputs amplify metastability tail and increase timing jitter.
• Clock feedthrough shifts effective threshold or creates correlated timing bias.
• PDN bounce injects input-referred error during the pick-off instant.

• Light: define a clean sampling window; ensure stable reset and non-overlap gating.
• Medium: symmetric routing/loading and explicit guardband beyond the tail onset.
• Heavy: add a conditioning stage (preamp/limiter) when slope and noise vary widely.

• Path symmetry budget (routing, buffers, loads).
• Tail-aware capture for near-simultaneous arrivals.
• Defined synchronization strategy into the clock domain.

• A/B mismatch turns into systematic time offset (bias) rather than random noise.
• Async boundary expands metastability beyond the arbiter if not contained.
• Thermometer/encoding becomes unstable when capture is placed inside the tail region.

• Light: enforce strict path matching and identical loading.
• Medium: add capture guardband and a defined sync chain for the arbiter result.
• Heavy: redundant sampling/arbiter hardening when tail risk must be minimized.

• VDD_min operating window and near-rail behavior.
• Reset robustness (memory removal) under corners.
• Offset and tail sensitivity versus VDD and temperature.

• Regen becomes weak at VDD_min; decision tails expand and valid-level timing slips.
• Near-rail inputs increase bias sensitivity to injection and asymmetry.
• Incomplete reset creates history dependence (apparent drift) across operating modes.

• Light: keep thresholds away from rails and qualify reset width across VDD/T corners.
• Medium: stabilize the threshold source (buffer/divider strategy) and reduce injection coupling.
• Heavy: add a front-end stage when near-rail operation is unavoidable and tail risk must be bounded.

• A PCB prototype needs fast thresholding or timing pick-off without a custom silicon latch.
• The goal is interface verification (output logic levels, capture window, latency budget) rather than minimum energy/decision.
• Power/area is secondary to repeatability and time-to-measurement.

• Energy per decision and clocked evaluation are first-order constraints (SAR/TDC at high rate).
• The system operates frequently in small overdrive and tail behavior must be shaped by design.
• Kickback and input disturbance must be minimized beyond what discrete comparators can guarantee.

• t_pd vs Overdrive curve (at least small/medium/large OD) with conditions: VDD, VICM, temperature, output load, and input source impedance assumptions.
• Delay dispersion / tail hints: any p99/p999 data, or guidance for safe sampling instant under small OD / slow slopes.
• Latch / LE timing (if present): setup/hold to LE/CLK, recovery time, and whether output is transparent vs sampled.
• Input loading & coupling: Cin (single-ended/differential), bias currents, and any notes on input kickback/disturbance.
• VICR / near-rail behavior: guaranteed operating region across VDD_min/T corners; identify crossover and degraded regions.
• Output type & levels: open-drain vs push-pull vs LVDS/CML/PECL, valid-level timing, and required termination.
• Power/disable behavior: shutdown entry/exit time and whether re-enable creates memory-like behavior.

• Sweep OD in bins: small (worst-case), medium, large; collect delay distribution (p50 / p99).
• Pass rule: capture point must be placed beyond p99 with explicit guardband at VDD_min/T_hot.

• Hold VIN at a stiff source; toggle only CLK/LE; measure input glitch peak (ΔV) and symmetry.
• Repeat with R_source bins; if ΔV scales strongly with R_source, mitigation is mandatory (R/RC, isolation, or preamp).

• Sweep reset width / duty / LE timing; check whether output bias depends on previous decision (memory).
• Fail signature: repeatable bias shift or correlated spur that moves with duty/edge-rate bins.

• VICM×VDD map: validate near-rail and VDD_min operation regions on real boards.
• Supply sensitivity: inject controlled ripple; observe whether tail/kickback signatures worsen.

The list below is intentionally short and bucketed. Exact latch/LE options, output interfaces, and speed grades vary by device and suffix; verify the final choice against datasheet timing tables and interface requirements.

• ADCMP580 / ADCMP581 / ADCMP582 (Analog Devices) — high-speed timing chains; evaluate tail risk and capture window.
• ADCMP572 / ADCMP573 (Analog Devices) — high-speed family; evaluate interface and small-OD behavior.

• LMH7322 (Texas Instruments) — commonly used where latch-enable style capture is required; validate LE timing and recovery.
• LTC6752 (Analog Devices) — family often used for fast thresholding; validate output type and capture assumptions.
• LTC6754 (Analog Devices) — higher-speed family; validate output interface (LVDS/CML variants) and termination needs.

• TLV3501 (Texas Instruments) — low-voltage, fast push-pull comparator; validate near-rail behavior and supply sensitivity.
• LMV7219 (Texas Instruments) — low-voltage comparator option for edge shaping; validate tail behavior if used for sampled decisions.

• TLV1805 (Texas Instruments) — higher input-voltage monitoring family; validate input protection and output interfacing.
• LMV7239 (Texas Instruments) — option for robust thresholding; validate input common-mode and output type for the target domain.

part_number:
output_type:
vdd_bin:
temp_point:
vicm_point:
od_bin: [small|med|large]
tpd_p50_ns:
tpd_p99_ns:
tail_flag: [0|1]
kickback_dv_pk_mV:
kickback_symmetry_note:
reset_memory_flag: [0|1]
capture_instant_ns:
guardband_ns: