In both low-side and high-side sensing, a differential current sense amplifier reads the voltage across a shunt resistor. Designers typically place small RC networks at the amplifier inputs to tame switching edges from buck stages, motor inverters or hot-swap events. These networks may be fully symmetric on both inputs or partially asymmetric to suit layout or connector constraints.

Two families of input RC are common in practice:

• Symmetric RC on both shunt terminals keeps the differential path balanced and preserves high CMRR even when common-mode noise is strong. It is preferred for precision shunt measurement in BMS and server power rails.
• Single-ended or differential-only RC places capacitance on one side or on the differential node only. It can be easier to route or retrofit, but any mismatch turns part of the common-mode content into differential error.

• Balanced RC → better CMRR and predictable gain, at the cost of tighter matching and extra parts.
• Unbalanced RC → simpler layout, but more sensitive to tolerance, drift and layout-induced asymmetry.
• Protection-level clamps and surge paths remain the job of the Front-End Protection stage, not these RCs.

RC networks can sit either in front of the current sense amplifier or after it. A pre-amp RC mainly increases the source impedance and introduces poles with the amplifier’s input capacitances, while a post-amp RC adds loading and extra poles at the amplifier output. Both choices affect phase margin and must be considered as part of the closed-loop design, not as an isolated “cleanup filter”.

• Pre-amplifier RC: shapes the shunt voltage before it reaches the amplifier, helping to knock down very fast edges close to the source. The trade-off is higher effective source impedance, which can amplify input noise and form additional poles with input capacitance.
• Post-amplifier RC: operates on the already amplified signal and is often used to align bandwidth with ADC sampling. It loads the amplifier output and, if too heavy, can introduce a dominant pole that erodes phase margin or causes ringing when driving large capacitive loads.

• Pre-amp RC → strong impact on input-referred noise and CMRR, plus hidden poles from source impedance.
• Post-amp RC → strong impact on output drive capability and load step response.
• Quantitative phase-margin targets and pole placement rules are detailed later in the Design Rules section.

Downstream of the amplifier, the ADC imposes its own constraints on filter placement. ΣΔ converters rely on oversampling and a digital sinc filter to define their measurement band, while SAR converters rely on a sample-and-hold capacitor that must charge to the correct level during a short acquisition window. In both cases, the input RC network needs to complement, not fight, these front-end behaviours.

• For ΣΔ ADCs, the RC cutoff is typically set around or below the analogue Nyquist point but above the useful measurement band. It helps suppress out-of-band noise that the digital sinc filter cannot fully reject, especially around the modulator frequency and its images.
• For SAR ADCs, the key question is whether the RC time constant allows the input to settle within the acquisition time. Excess series resistance together with the ADC input capacitance produces gain and linearity errors long before any obvious aliasing shows up.

• ΣΔ chains care about how RC interacts with oversampling ratio and digital filter stop-band.
• SAR chains care about source impedance and settling error within each sample window.
• Multi-channel synchronisation and timestamping details are handled in the Sync & Timestamp topic.

Every input filter introduces a time constant τ_RC = R · C and a pole at a frequency f_RC ≈ 1 / (2πRC). In a current or power sensing chain, that pole sits somewhere between the useful signal band and the closed-loop bandwidth of the amplifier, f_CL. If f_RC falls too low, the filter will eat into the real signal amplitude. If it sits too high, close to f_CL, it can erode phase margin without delivering much noise benefit.

A useful way to think about placement is to bracket f_RC between the maximum signal frequency and the amplifier’s closed-loop bandwidth. For example, if your measurement band extends to about 100 kHz and the current sense amplifier’s closed-loop bandwidth is about 1 MHz, an RC pole in the few-hundred-kilohertz region often gives a good compromise: it does not attenuate the top of the signal band, but it starts to trim away switching edges before they reach the loop crossover.

As a concrete example, imagine a low-side shunt where the current waveform of interest is DC to 100 kHz, and the gain configuration of the amplifier yields a closed-loop bandwidth near 1 MHz. Placing f_RC around 200–300 kHz keeps the measurement band intact and begins to round off MHz-range spikes. By contrast, choosing f_RC near 800–900 kHz means the pole is fighting directly with the closed-loop dynamics and can contribute noticeably to overshoot and ringing.

• Keep f_RC comfortably above the highest signal frequency you care about.
• Avoid placing f_RC right at the loop crossover; aim at least a factor of three away.
• Revisit RC placement whenever gain settings or amplifier bandwidth change.

From the amplifier’s perspective, the shunt, RC network and parasitic capacitances all combine into a frequency-dependent source impedance. As frequency rises, the effective impedance can increase and form new poles with input capacitances. This is why a modest-looking series resistor or unbalanced input filter sometimes causes much larger ringing than expected: the amplifier is now driving a source that tilts strongly with frequency.

A healthy current sense loop typically aims for at least 45° of phase margin, with 60° or more providing a comfortable buffer for component tolerances and layout variation. In a Bode plot, that translates to the phase curve staying well above −135° at the gain crossover frequency. When the input RC values are pushed too far, the gain crossover can shift and the phase trace near that point will dip, sometimes sharply, resulting in overshoot, long-settling ringing or even sustained oscillation when the load or supply changes quickly.

• Increasing series resistance at the input raises source impedance and tends to add extra poles.
• Extra input capacitance, including from ESD structures and traces, can join with RC values to form new corners.
• Phase margin targets should be checked again after any change to input networks, not just feedback elements.

Any ADC samples the world at a finite rate, and anything in the input spectrum above half that rate can fold back as alias components. The job of the input RC is not only to calm down waveforms for the amplifier, but also to present the ADC with a band-limited signal that does not violate Nyquist in a damaging way. In practical current and power sensing designs, the filter must respect both the analogue dynamics and the converter’s sampling scheme.

In a ΣΔ chain, the converter runs at a high modulator frequency and uses an oversampling ratio (OSR) together with a digital sinc filter to define the measurement band. The RC cutoff is usually placed around or below the analogue Nyquist point, but above the useful DC–AC band of interest, to reduce switching noise and modulator images that the digital filter cannot fully remove. Too little analogue filtering leaves residual high-frequency content that leaks through as low-frequency spurs in the FFT.

In a SAR chain, the dominant concern is the acquisition window of the sample-and-hold capacitor. The input network, including series resistance from the RC filter, must let the capacitor charge to within a small error band during that window. As resolution and sampling rate go up, the allowed source resistance drops quickly. An RC filter that looks harmless in a low-speed 12-bit system can introduce gain and linearity errors long before aliasing is obvious in a 16-bit, multi-hundred-kilosample system.

• Check f_sample, OSR and digital filter settings before finalising f_RC.
• For ΣΔ, use RC to help reject switching and modulator noise that sits near or beyond Nyquist.
• For SAR, treat the RC source resistance as part of the ADC input network and verify settling error.

A heavier filter improves noise and alias performance, but always at the cost of slower response. In current and power sensing this trade-off is not academic: eFuse and hot-swap stages may need to react within microseconds, while billing-grade metering can tolerate slow dynamics but demands extremely clean spectra. It is better to decide up front which side you are optimising for than to aim for a vague compromise.

• Fast protection and event capture: choose RC values that preserve sharp steps and keep group delay small in the band where fault waveforms live. Accept a slightly noisier ADC trace and use limited digital averaging if needed. This suits eFuse, hot-swap, inrush limiting and fast OCP loops.
• Precision metering and slow dynamics: place f_RC low enough to aggressively remove switching noise and flicker outside the billing band. Accept that step waveforms are rounded and alarms may respond more slowly. This is typically used in BMS fuel gauging, server DC power metering and sub-metering of AC loads.
• Mixed-mode systems: sometimes one sense path feeds both fast protection and slow energy logging. In that case, a common pattern is a relatively light analogue RC combined with two digital paths: a fast one with minimal filtering for protection and a heavily averaged one for metering.

When in doubt, sketch the expected fault and load-change waveforms and decide which information must survive the filter. Use that as the anchor for f_RC, then verify the impact on phase margin and ADC behaviour rather than tuning RC in isolation.

If you have access to a loop analyser or FRA capability, the most direct way to quantify stability is to measure the closed-loop gain and phase around the frequency band where the input RC operates. Even in current and power sensing chains that are not traditional regulators, the combination of the amplifier, filter and any feedback paths still forms an effective loop with a crossover and a phase margin.

1. Insert a small-signal injection point in the loop at a node that does not disturb the DC operating point, for example through a transformer or coupling capacitor in series with the feedback path.
2. Sweep frequency from well below the expected crossover (for example a decade below) to at least one or two decades above it, and record both gain and phase.
3. Identify the frequency where the gain crosses 0 dB and read off the phase at that point. The phase margin is the distance from this phase to −180°.

As a rule of thumb, a flat, smooth phase curve with 60° or more of margin at crossover is a good sign. A sharp downward bend near crossover or margin below about 45° should trigger a review of the RC values and source impedance. Broader bandwidth and response-time trade-offs are discussed in the Bandwidth & Response topic.

Where a full FRA setup is not available, time-domain testing with a scope can still reveal most stability issues. A clean, well-damped step response suggests comfortable phase margin, while excessive overshoot and long ringing are warning signs that the input RC and amplifier dynamics are too tightly coupled.

1. Apply controlled load steps or current pulses on the sensed rail and observe the amplifier output and the ADC input node. Use several amplitudes, from small perturbations up to realistic fault levels.
2. Measure overshoot and undershoot relative to the final value, and count how many oscillation cycles are needed before the waveform settles back within a small error band.
3. Repeat with the fastest credible transient (for example a nearly instantaneous disconnect) to stress both the filter and the amplifier.

As a starting guideline, overshoot in the 10–20 % range that damps out within a few cycles is usually workable, while larger overshoot or slowly decaying ringing indicates marginal phase margin. A step response that looks overly rounded, with no visible edge, may indicate that the analogue RC is doing too much of the job that could be handled by digital filtering.

FFT analysis of ADC codes is a powerful way to spot aliasing and filter problems that are not obvious in the time domain. By comparing the expected input spectrum with what appears in the digitised data, you can tell whether switching noise and other out-of-band content are leaking into the measurement band.

1. Capture a block of ADC samples at the normal sampling rate while the system operates in a representative mode, for example at nominal load with the relevant switching rails enabled.
2. Apply an appropriate window function and compute the FFT, plotting magnitude versus frequency up to half the sampling rate.
3. Look for unexpected narrow peaks or dense “grass” in the baseband, especially at frequencies related to switching or modulator clocks that should have been attenuated by the input RC and ΣΔ or SAR front-end.

Persistent spurs or a noisy floor that tracks switching frequency changes often indicate insufficient analogue filtering or a poor match between f_RC and the converter’s sampling behaviour. When the filter is too heavy, the FFT may look clean but step testing will reveal that important event content has been blurred away, so both views should be considered together.

Real systems rarely consist of a single isolated sense channel. Multi-channel ADCs, shared references and shared shunts can all create subtle interactions between RC networks. Hot-plug and large load steps add further stress. These corner cases deserve dedicated tests so that small layout or component value changes do not turn into unexpected field issues.

1. In shared-reference or multi-channel ADC setups, exercise one channel at a time while monitoring all others. If activity on one channel causes visible glitches or correlated noise on another, review the RC placement and common-node impedance.
2. During simultaneous sampling, check whether a single channel with much heavier or lighter filtering appears to disturb the sampling capacitor or reference rails for its neighbours.
3. For hot-plug and abrupt load changes, replicate the worst-case edges with switches or relays and record both analogue waveforms and ADC codes before, during and after the event. Look for long recovery times, stuck-at levels or spurious spikes in black-box logs.

Surge energy, ESD robustness and clamp design for hot-plug are handled in the Front-End Protection topic. Here the focus is on how those events interact with the chosen RC values and whether the measurement chain returns to a stable, accurate state without hidden long-term bias or oscillation.