System Role & Use Cases for On-Chip TIA + Rsense

An on-chip transimpedance amplifier (TIA) integrates the current-sense gain block inside a MCU, metering AFE or dedicated power-monitor IC, exposing only two low-level sense pins to an external PCB shunt resistor. The chip converts the shunt current into a voltage suitable for its internal ADC, reducing layout complexity while centralising the precision analog front-end in silicon.

In system terms, the monitored rail needs only a low-side shunt in the return path. High-current loops remain on the PCB while the sensitive transimpedance, filtering and digitisation happen inside the IC. This makes the approach ideal for low-voltage and multi-channel current monitoring where PCB space and noise immunity matter.

Typical use cases

• Low-voltage embedded rails in BBU, IoT nodes and small battery systems.
• USB/PD sink power paths or DC inputs where the MCU already includes metering IP.
• Energy-metering and PMIC monitors where one AFE hosts multiple TIA + ADC channels.

How it differs from discrete current-sense amplifiers

• Integration vs flexibility: simpler BOM and routing but fewer gain/bandwidth options.
• Layout simplification vs package limits: sense pins are constrained by ESD and CM range.
• Error structure: chip-internal matches well; total accuracy still dominated by Rsense.

For high-side or wide-CM designs, refer instead to: Low-Side CSA / High-Side CSA. For µs-level fault sensing, see Fast Current Sense for Protection.

TIA Topologies & Integration Patterns

Architecturally, an on-chip TIA current-sense front-end can be seen as a short chain: the PCB shunt resistor Rsense converts load current into a small voltage drop, the on-chip TIA turns that drop into a usable signal and the ADC digitises it for firmware or metering engines. The high-current loop and thermal behaviour live on the board; the precision gain and filtering live inside the IC.

Basic building blocks in the signal path

• Shunt resistor (Rsense): placed in the return path of the monitored rail, it defines the voltage developed per ampere and must survive the worst-case I_FS and fault conditions.
• On-chip TIA: implements an effective transimpedance gain using internal feedback elements that sense the small differential voltage at the Rsense sense pins and generate an output within the ADC input range.
• ADC and digital logic: quantises the TIA output, applies averaging or decimation and exposes calibrated current readings to SW or metering state machines.

Integration modes for on-chip TIAs

• Fully on-chip TIA: the feedback resistor and any compensation capacitor are fully integrated. The designer only routes Rsense and returns the sense lines to the device. Layout is straightforward and matching is excellent, but gain and bandwidth are offered as a small number of fixed options, so the usable current range is largely set by the silicon.
• Externally configurable Rf / Cf: the IC exposes a TIA node that allows external Rf and Cf to define transimpedance and dominant pole. This gives more freedom to reuse the same device across different Rsense values or bandwidth targets, at the cost of extra sensitive components that must be routed carefully between the shunt and the IC.
• TIA + PGA / ADC combo: the TIA feeds an internal programmable-gain stage and ADC, often with selectable digital filters. One front-end can then service multiple rails via a multiplexer and support several current ranges by changing gain and sampling configuration in firmware or metering microcode.

Across these modes, the architectural signal flow remains the same: current through Rsense creates a differential sense voltage, the TIA maps that voltage to an internal node with an effective transimpedance and the ADC interprets it as a signed or unidirectional current reading. Detailed error budgeting and stability analysis are covered in later sections, but at this stage the focus is on how much freedom the device gives you to trade current range against resolution and bandwidth.

Grounding and common-mode operating window

Most on-chip TIAs are intended for low-side, near-ground rails. Their sense pins sit inside a narrow common-mode window defined by ESD structures and internal analog headroom. The device expects the shunt to be close to analog ground, with only tens or hundreds of millivolts developed across Rsense during normal operation. Monitoring 12–48 V buses or true high-side nodes normally belongs to a dedicated high-side current-sense amplifier, as discussed on the High-Side Shunt Current Sense Amp page rather than here.

Package pinout and Kelvin routing hooks

Package pinout strongly shapes how cleanly the TIA can observe Rsense. QFN devices often cluster SENSE+, SENSE− and AGND pins in one corner so that a short pair of Kelvin traces can return directly from the shunt. LQFP variants may spread these pins along one edge but still group them near the quiet ground region. BGA packages sometimes place the sense balls in a small island, with surrounding ground balls that shield the measurement paths from noisy digital or power pins. These patterns are deliberate hints from the IC designer about the intended current path and should be matched by the PCB floorplan.

Small-Signal Model & Error Budget

At small-signal level, an on-chip TIA front-end can be reduced to three cascaded stages. The load current I_sense flows through the shunt resistor R_sense and produces a differential voltage V_shunt = I_sense · R_sense. The on-chip TIA multiplies this drop by an effective gain G_TIA, and the ADC then digitises the resulting output voltage.

For many architectures, the small-signal relationship can be approximated as: V_out ≈ I_sense · R_sense · G_TIA, where G_TIA is either an explicit feedback resistor R_f (in V/V) or a specified transimpedance in V/A. The ADC simply maps V_out into a code using its reference and resolution, so any inaccuracy in these three blocks becomes an apparent current error.

Gain chain from current to ADC code

• Shunt stage: V_shunt = I_sense · R_sense. At full-scale current, this drop should remain within the common-mode window of the TIA.
• TIA stage: the device applies a nominal gain G_TIA so that V_out,FS ≈ I_FS · R_sense · G_TIA, usually aiming for a convenient fraction of the ADC input range.
• ADC stage: the output codes map V_out into measured current using the ADC reference, resolution and any digital scaling applied in firmware.

Error building blocks

The total current error can be viewed as a combination of shunt-related, TIA-related and ADC-related terms. Each can be expressed as an equivalent percentage of full-scale current or as an absolute error in milliamps.

Shunt resistor contributions

• Tolerance: the initial tolerance of R_sense (for example ±1 % or ±0.5 %) directly appears as a proportional gain error on current.
• Temperature coefficient: the ppm/°C rating multiplied by the worst-case temperature rise translates into an additional gain drift over temperature.
• Self-heating: at high I²R power levels the resistor runs hotter than ambient, effectively amplifying its temperature coefficient. Thermal design and derating are therefore part of the electrical error budget.

On-chip TIA contributions

• Gain error: finite open-loop gain, resistor matching and internal trimming all show up as a specified transimpedance gain error, often quoted in percent or mV/A.
• Offset: input offset voltage and bias currents create an apparent offset current that can be significant when shunt voltages are in the tens of microvolts.
• External R_f / C_f (if present): external feedback components bring their own tolerance and tempco. If they define part of the gain, their spread must be included alongside the internal transimpedance error.

ADC and reference contributions

• Quantisation: each LSB corresponds to a fixed current step. For very small currents the quantisation step alone may dominate the uncertainty.
• INL / DNL: integral and differential non-linearity appear as a position-dependent error in output code, which can be mapped into an equivalent current error at different operating points.
• Reference drift: if the ADC uses an internal or external reference, its tolerance and tempco effectively scale the whole transfer function and must be counted in the gain budget.

Building a quick error budget

A practical way to size the design is to start from the full-scale current I_FS, the allowed total error (for example ±1 %FS or ±20 mA) and the intended temperature range. This budget is then allocated across Rsense, the TIA and the ADC, leaving some margin for layout-related effects covered in later sections.

A simple spreadsheet can list each contributor with its specification and its translated impact at I_FS. Terms from shunt tolerance, shunt tempco, TIA gain and offset, ADC quantisation and INL/offset are added according to the chosen error model (for example RSS or worst case). If the sum exceeds the available budget, the designer can iterate on shunt precision, TIA architecture, ADC resolution or calibration strategy.

On-chip TIAs generally improve matching, tempco tracking and the interface to the ADC compared with a fully discrete solution, which simplifies the error structure. The trade-off is less freedom to choose arbitrary transimpedance gains or voltage ranges. When the required current span and accuracy no longer fit within the offered gain/ADC combinations, it may be a sign that a discrete current-sense amplifier or a different device family is needed.

Stability with Rsense Parasitics

Even when the small-signal gain chain is correct, an on-chip TIA can misbehave if the shunt, PCB routing and decoupling capacitors introduce unexpected poles and zeros. Long traces, large bypass capacitors and the input capacitance of the device all combine with the TIA feedback network to form a closed-loop system whose phase margin may be marginal.

Rather than deriving a full control-theory model, it is usually sufficient to recognise the key parasitic elements, understand the most common failure scenarios and apply a small set of layout and compensation rules that keep the loop stable over the intended current bandwidth.

Equivalent circuit with parasitics

Around the shunt, the real PCB can be collapsed into a few components. The copper between Rsense and the TIA sense pins behaves as a series inductance L_trace. Any local bypass capacitor or filter across the shunt becomes an effective C_shunt. The TIA inputs and ESD structures contribute an input capacitance C_in, while the feedback path uses an effective R_f / C_f network to set gain and high frequency roll-off. Together, these elements can form a lightly damped RLC system if left unchecked.

Typical instability scenarios

• Large current steps causing ringing: motor starts, inrush events or fast load transients drive a large dI/dt through Rsense. The combination of L_trace, C_shunt and C_in can ring, producing overshoot and oscillation at the TIA output.
• Over-sized shunt capacitors: adding a large capacitor directly across Rsense may help with noise, but for the TIA it introduces an extra pole in the loop. If its value is too large for the selected gain and bandwidth, the net phase margin becomes small and the system behaves like a slow oscillator.
• Multiplexed TIAs with long recovery: when a single TIA is multiplexed across several shunts, each channel change can leave the TIA input capacitance charged to the previous channel voltage. With long traces or heavy shunt capacitance, the new channel takes significant time to settle, reducing the valid sampling window.

Practical design rules for on-chip TIA stability

• Keep Rsense close to the device: minimise the distance and number of vias between the shunt and the TIA sense pins to limit L_trace and shared ground impedance. Short, symmetric Kelvin traces reduce both ringing and common-mode pickup.
• Control C_shunt: use only as much capacitance across Rsense as needed to meet the noise and EMC goals. For metering or slow control loops, tens of nanofarads may be acceptable. For tens-of-kHz bandwidth, C_shunt should usually be kept in the low-nanofarad range and additional filtering applied closer to the ADC instead.
• Use C_f to introduce a stabilising zero: a small capacitor in parallel with R_f (or the equivalent internal transimpedance) creates a zero that can compensate the pole formed by C_shunt and C_in. Increasing C_f improves phase margin but also reduces closed-loop bandwidth, so it must be sized with both stability and response time in mind.
• Verify in time domain: step the load current and observe the TIA output and ADC input on an oscilloscope. A well-behaved system shows limited overshoot and quickly settles to a new value without sustained ringing or low-frequency oscillations.

A simplified Bode perspective

For many designs, it is enough to follow a three-step checklist instead of performing a full loop-stability derivation:

1. Identify parasitics: estimate L_trace, C_shunt, C_in and the expected current bandwidth.
2. Place a compensating zero: choose C_f and C_shunt so that the added zero improves phase margin over the band of interest without cutting too much useful bandwidth.
3. Verify margin with transients: use time-domain tests to confirm that the resulting loop behaves well under the worst-case load steps and line conditions.

Noise, Bandwidth & Filtering

The on-chip TIA, shunt resistor and ADC together define how much random variation appears on the measured current. The wider the bandwidth, the more noise energy enters the conversion. Choosing a bandwidth that is just wide enough for the application, and then placing the right kind of filtering, is often more effective than chasing extremely low noise figures in each individual block.

Noise sources in a shunt plus on-chip TIA system

• Shunt thermal noise: the resistor generates broadband noise that grows with resistance value, temperature and bandwidth. In low current, high precision metering, this 4kTRB term can dominate.
• TIA input noise: the amplifier contributes its own equivalent input voltage and current noise. With very small shunt values, the TIA noise often sets the floor even if shunt thermal noise is low.
• ADC and digital path: quantisation and conversion noise add another layer of uncertainty. Oversampling and averaging can reduce this contribution at the cost of bandwidth and latency.

Matching bandwidth to current waveform

Before tuning filters, it is helpful to classify what kind of current information is actually needed. The required bandwidth will be very different for slow average current tracking than for capturing fast fault events, and the achievable noise floor follows that choice.

• Slow average current: battery fuel gauging, energy metering and thermal design often care about average current over tens of milliseconds or longer. Bandwidths in the 100 to 1000 Hz range are usually sufficient and help significantly reduce noise.
• Medium speed dynamics: monitoring load steps, soft start behaviour or control loop response may require bandwidths in the few kilohertz range. Here, analog and digital filtering must be coordinated so that useful dynamics are preserved while unnecessary high frequency noise is removed.
• Fast pulses and protection: microsecond level fault detection and current limiting rely on inherently wide bandwidth front ends and sacrifice some noise performance. Detailed tradeoffs for these protection paths are covered on the Fast Current Sense for Protection page rather than here.

Filtering strategies: analog and digital

• Analog RC filters: a small RC network at the TIA output or ADC input acts as an anti alias filter and keeps high frequency noise and EMI away from the converter. The corner frequency should sit above the highest useful signal content but low enough to avoid unnecessary noise bandwidth. Excessive capacitance must be checked for stability impact as described in the stability section.
• Digital averaging and decimation: oversampling the TIA output and averaging in firmware or within a metering AFE can greatly reduce effective noise. Longer averaging windows improve resolution but also reduce the ability to follow fast current changes.
• Combined approach: gentle analog filtering to prevent aliasing and ringing, followed by configurable digital filtering, often yields the best balance between noise, bandwidth and implementation cost.

Practical thumb rules for noise versus bandwidth

In many designs, sizing bandwidth can be reduced to a few simple rules. A reasonable starting point is to set the effective current bandwidth to roughly two to five times the highest frequency component that must be measured with accuracy. For metering and long term logging, that often translates into 100 to 1000 Hz rather than tens of kilohertz, which dramatically improves signal to noise ratio.

When bandwidth and noise goals conflict, it is usually better to revisit the system level requirements first rather than forcing the front end into an unrealistic combination of very high speed and very low noise. Choices such as splitting the function into a fast protection path and a slower metering path are often more robust than stretching a single TIA beyond its comfort zone.

Package, Pinout & Layout Hooks

Layout of the shunt and its connection to the on-chip TIA often decides whether the measurement is clean or hopelessly contaminated by switching noise and ground bounce. This section highlights the placement and routing patterns that matter most and shows how to use the package pinout as a guide for a clean Kelvin connection.

Placing Rsense in the current path

• Downstream in the return path: place the shunt so that all relevant load current flows through it before returning to the main ground. Avoid alternative return paths that bypass Rsense.
• Close to the device: keep the physical distance between Rsense and the TIA sense pins small to limit trace inductance and common impedance.
• Keep a quiet region: avoid placing fast switching nodes, large gate drive traces or clock lines directly next to the shunt pads and Kelvin traces.

Kelvin sense routing

• Sense from the pads, not the copper: run the sense traces directly from the Rsense pads rather than tapping into current carrying copper further away. This avoids including unwanted voltage drops in the measurement.
• Short, thin and paired: use a matched pair of short traces for the sense connections, routed close together to minimise loop area and magnetic pickup.
• Avoid parallel runs with noisy lines: do not let sense traces run in parallel with high dV/dt or high di/dt lines. If crossing is unavoidable, cross at right angles and consider using a quieter reference layer.

Using package pinout and grounds correctly

The package and pinout often encode the intended current and sense paths. QFN devices tend to cluster sense and analog ground pins, LQFP variants group them along one side and BGA parts may hide them inside a shielded island of ground balls. Following these patterns greatly simplifies achieving a clean Kelvin connection.

• AGND versus PGND: when the device provides analog ground or sense ground pins, return the Rsense sense traces to these nodes rather than to high current power ground pins.
• Continuous ground plane under the sense region: avoid ground plane splits or slots underneath the shunt and sense traces that would introduce additional impedance and noise pickup.
• Respect recommended pin groupings: if the datasheet shows SENSE plus, SENSE minus and AGND grouped together, treat that region as the preferred landing zone for the Kelvin traces.

For layouts targeting microvolt level offsets and long term stability, including chopper and zero drift amplifiers, see the dedicated Zero-Drift Current Sense Layout page. For shunts that are part of eFuse or hot-swap power paths, including fault energy and copper width planning, refer to the corresponding hot-swap and eFuse layout pages instead of overloading this on-chip TIA overview.

Calibration & Diagnostics Hooks

Because the TIA, ADC and digital logic share the same die, an on-chip current-sense front end can support calibration and self-test features that are difficult to realise with discrete amplifiers. This section describes typical offset and gain calibration schemes, fault detection hooks and how the digital interface exposes these capabilities without diving into protocol-level detail.

Offset and gain calibration

Offset calibration removes the residual voltage that appears at the ADC output when the sensed current should be zero. Many devices include analog switches that can short the TIA inputs together or connect them to an internal reference node. Firmware triggers this condition, collects several ADC readings and stores the average as a zero-offset code that is subtracted from subsequent measurements.

Gain calibration aligns the effective current scale with a known reference. During production test or controlled service procedures, a known current is driven through the shunt or a dedicated calibration resistor. Comparing the measured code with the ideal value yields a gain correction factor. Because the TIA gain is usually offered in discrete ranges rather than as a continuous trim, the correction is typically applied in the digital domain.

Self-test and fault detection

Digital supervision can also detect faults around the shunt and TIA path. When a shunt connection opens or a pad lifts, the sense pins often float towards internal bias points and the measured current snaps to a fixed value that does not respond to real load changes. Monitoring for such stuck or unresponsive readings over several conversions provides a simple shunt-open diagnostic.

Shorted inputs, wiring mistakes or sustained overcurrent may drive the TIA output into saturation. Many devices expose status bits that indicate when the ADC is pinned near its upper or lower limits. Combining these flags with range information allows firmware to distinguish between normal full-scale operation, temporary overload and genuine wiring faults that require service action.

Digital interface hooks

On-chip TIA solutions in dedicated power monitors typically expose their capabilities through I²C or SPI registers. Configuration fields may control calibration triggers, averaging depth, alert thresholds and channel selection when several shunts share one front end. Interrupt or alert pins can signal overcurrent, shunt-open or ADC fault conditions without constant bus polling.

The exact register map and communication timing are device specific and belong to the digital current monitor domain. For protocol details, refer to the dedicated Digital Current Monitor page. Here the focus remains on the kinds of hooks the TIA provides and how they fit into the overall current measurement strategy.

Factory versus field calibration

Calibration can be performed once at the factory, repeated periodically in the field or combined. Factory calibration usually uses precise equipment and well known loads to characterise gain and sometimes second-order effects at a few operating points. The resulting coefficients are stored in non-volatile memory and used as a baseline for all devices.

Field or in-system calibration focuses on removing drift that occurs after shipment. A common strategy is to run a short offset calibration on every power-up, and to schedule occasional gain checks when the system is in a known state, for example with power stages disabled or with a defined calibration load connected. On-chip TIAs benefit from both approaches because the analog path is compact and repeatable, so factory data and field updates combine well.

Example calibration flow at start-up

1. Force the TIA inputs into a known zero-current condition using internal switches or by disabling loads, then average several ADC conversions to capture the offset code.
2. If a calibration current or resistor is available, enable it briefly, measure the corresponding ADC code and derive a gain correction factor.
3. Store the resulting offset and gain values and apply them to all subsequent readings until the next scheduled calibration cycle.

Vendor & Part Mapping

This section highlights device families that combine an on-chip TIA, ADC and digital logic designed to work with external shunt resistors. The goal is to give a few clear directions rather than an exhaustive catalogue. High voltage eFuse and hot-swap controllers, where the current sense function is deeply tied to fault protection, are covered in the dedicated hot-swap and eFuse pages instead.

MCU / SoC families with on-chip current-sense TIA or op-amp

When currents are modest and board space is tight, it can be attractive to use the microcontroller’s built-in TIA or programmable op-amp instead of a discrete current-sense amplifier. The families below are representative of this approach and can interface directly to external shunts on low voltage rails.

Standalone power and energy monitor ICs

These devices integrate the TIA, ADC and often an energy computation engine behind an external shunt. They are well suited to small production runs where firmware and calibration effort should be minimised and standard bus interfaces are preferred.

Dedicated current-sense AFE and TIA devices

When only the analog front end is needed and the system already includes an MCU or ADC, dedicated current-sense amplifiers provide a clean TIA stage for external shunts. They are often used as building blocks in custom measurement chains and protection circuits.

These examples are not a complete list, but they provide reference families when creating shortlists. For high voltage hot-swap, eFuse or PoE controllers where the current sense block is tightly coupled to protection logic, refer to the dedicated hot-swap and eFuse pages and keep this section focused on shunt plus TIA front ends.

BOM & Procurement Notes

Recommended BOM and RFQ fields

At minimum, the BOM for a current-sense channel should specify which rail is monitored, the full-scale current range, the shunt parameters and key expectations for the TIA or monitor IC. The table below shows typical fields and example entries that can be adapted directly into purchase documents.

Example BOM snippets for small-batch builds

Example 1 — Single precision DC rail monitor

• Shunt resistor: a 5 mΩ, 3 W, 1 % 2512 part such as WSMHP2512R0050FEA (or equivalent). The large package and low value support 10–20 A with manageable temperature rise and a layout friendly footprint for Kelvin sensing.
• Monitor IC: INA228AIDGST for precision high-side measurement with a 20-bit ADC and energy accumulation registers. It is a good fit when a single important rail must be monitored with high resolution and fault reporting.
• Host MCU: any 3.3 V MCU with I²C and sufficient flash, for example an STM32G4 or MSP430FR2311 when control and metering are combined on one device.
• Why this combination: the discrete shunt keeps BOM cost low while the monitor IC handles calibration, averaging and alerts, reducing firmware effort in small batches.

Example 2 — Multi-rail board-level power monitoring

• Shunt resistors: four 10 mΩ, 1 %, 0.5 W 1206 shunts for 3.3 V, 5 V and auxiliary rails. The modest power rating is sufficient for a few amps per rail and keeps size and cost under control.
• Monitor IC: PAC1934T-I/JQ, a four-channel DC power monitor with accumulation registers. It can measure current and voltage on several rails simultaneously and report power and energy over I²C.
• Why this combination: for multi-rail systems it is more cost-effective to share a single multi-channel monitor than to place a separate precision IC on each rail. The designer still decides whether rails share a common return and how to allocate shunt values.

Common risks and how to flag them in the BOM

• Fixed gain limits adjustment space: on-chip TIA gain is offered in discrete steps. If the current range later doubles, the ADC may only use a small fraction of its codes. Mitigate this by noting an acceptable gain range or listing alternate part numbers with higher and lower gain in the BOM.
• Shunt power and thermal headroom: choosing a resistor purely on ohms and tolerance without checking continuous and surge dissipation can lead to early drift or damage. Include expected steady-state and peak currents, allowable temperature rise and whether four-terminal packages are required.
• Platform changes break TIA assumptions: migrating from one MCU or AFE family to another may change common-mode range, bandwidth or noise. Capture key TIA requirements in the BOM (for example, low-side, 0–12 V rail, minimum bandwidth and offset limits) so alternative devices are screened properly.
• Calibration and test overhead: high accuracy figures assume that the factory or field calibration procedures are implemented. Add notes that single- or dual-point calibration and appropriate test points are required, so production plans and cost estimates remain realistic.

If the choice between monitor ICs or shunt values is still unclear, it is often enough to provide rail voltage, full-scale current, accuracy target and preferred package types in your enquiry. A short description in the BOM and a link or reference to your layout constraints allow partners to propose suitable shunt and on-chip TIA combinations. For more complex cases, you can route projects through the /submit-bom form and attach schematics or PCB outlines so that Rsense and TIA decisions are made with layout and thermal limits in mind.

FAQs on On-Chip TIA with Sense Resistor