R-2R ladder DACs deliver area-efficient, medium-to-high-speed conversion, but real performance is decided by
major-carry dynamics and reference/return integrity as much as by INL/DNL.
This page turns those mechanisms into a practical workflow: spec → risk → minimum tests → selection, so designs close reliably on the bench.
What this page solves
This page focuses on the R-2R ladder DAC path: an area-efficient, medium-to-high speed architecture used for general-purpose
control and waveform generation. It explains why accuracy and cleanliness break in real hardware, which issues are calibratable,
and how to measure and debug the root cause instead of guessing.
Typical problems (expressed as measurable symptoms)
INL/DNL looks non-uniform: good in some code regions but worse around specific transitions (code-segment sensitivity).
Major-carry steps ring or take too long: large-step settling time is much worse than small-step settling time.
SFDR/THD collapses “randomly”: specific output tones or code patterns create persistent spurs.
Calibration/trim options for R-2R and the verification plan to confirm improvements.
Out-of-scope (to avoid overlap)
Deep implementation of String / Segmented / Current-Steering / ΣΔ DACs (only “when to switch paths” is mentioned).
Detailed output-driver, reconstruction filter, protection design (handled in the Output / Reference-Driver-Filters pages).
JESD204B/C timing alignment and SYSREF/LMFC procedures (handled in the Interfaces & Synchronization pages).
Architecture map: R-2R targets area efficiency with medium-to-high update rate, but requires deliberate control of mismatch, glitch, and return-path behavior.
Definition & mental model
An R-2R ladder DAC uses a repeating R/2R resistor network and a bit-controlled switch matrix to create binary-weighted
contributions at an output node. Its advantage is area efficiency (reused unit resistors). Its core risk is that ratio mismatch
and switch non-idealities convert into code-dependent static errors and dynamic artifacts.
Model A: binary weighting (ideal)
Each bit steers a fraction of the reference through a self-similar ladder.
In the ideal case, weights follow 1/2, 1/4, 1/8… because the ladder presents a consistent equivalent impedance.
Accuracy depends on ratio consistency, not on absolute resistance value.
Model B: sensitivity (why mismatch matters)
Δ(R/2R) changes bit weights → shows up as INL/DNL and monotonicity risk.
Switch RON and parasitics create code-region dependence: some transitions are more sensitive.
Temperature gradients and self-heating can warp the transfer curve, not just shift it.
Model C: update transient (glitch & settling)
Updating code flips multiple switches; timing skew and charge injection create a glitch impulse.
The output then converges to the final value through the node’s effective RC and return paths: settling tail.
Major-carry transitions flip many bits at once → often the worst-case transient.
Output node naming (kept at “name-level” to avoid overlap)
Two common realizations appear in practice: voltage-summing and current-summing. The difference mainly affects the node
impedance and how strongly load and parasitics shape settling and distortion. Detailed driver, filtering, and protection topologies belong to the
Output / Reference-Driver-Filters pages.
Minimal mental model: repeated R/2R cells create binary weights; real silicon adds mismatch and switching dynamics that must be verified with INL/DNL sweeps, step settling, and FFT.
Ideal weighting: why R-2R is area-efficient
The R-2R ladder achieves binary weighting using a repeating R/2R unit rather than a rapidly growing resistor array.
This repeatability is why it is area-efficient: higher resolution primarily adds more identical unit cells.
In the ideal model, each bit “sees” a similar equivalent impedance, so contributions naturally follow 1/2, 1/4, 1/8…
without requiring unique resistor values for each weight.
Key takeaways (ideal model)
Area scaling is near-linear with bits: resolution increases by adding repeated unit cells, not by exploding array size.
Linearity potential depends on ratio consistency: accuracy is governed by the R:2R ratio, not absolute resistance.
Monotonic behavior in the ideal case comes from strictly decreasing weights and consistent switching of each bit’s contribution.
Why this matters for real designs
The ideal weighting picture is the reference point: any deviation from ratio consistency or ideal switching becomes a structured static error
(DNL/INL shape, monotonicity risk) or a code-dependent artifact. The next section turns this ideal model into a practical error map.
R-2R builds binary weights from repeated unit cells, enabling compact scaling. In the ideal model, ratio consistency preserves weighting and monotonic behavior.
Static accuracy limits
Static accuracy is where the ideal R-2R model meets silicon reality. The dominant static metrics are DNL (step-size error between adjacent codes),
INL (transfer-curve deviation), and the global terms gain and offset. For R-2R, the most important question is
not “is the error large”, but “is the error structured and code-region dependent”, because that reveals the physical cause.
Static metrics (engineering meaning)
DNL: local step-size error → monotonicity and missing-code risk.
INL: global curve deviation → absolute accuracy and linear waveform fidelity.
Gain / Offset: global scale and shift → often calibratable, but not the same as linearity.
1) Ratio mismatch (ΔR/R)
Shifts bit weights away from the ideal 1/2 progression.
Creates structured INL/DNL shapes rather than uniform randomness.
Often appears as code-region sensitivity: some code ranges show larger local errors.
2) Switch RON spread (ΔRON)
Acts like an extra code-dependent resistance, effectively perturbing the ratio network.
Introduces code-pattern dependence even in DC/low-frequency tests.
Its temperature coefficient can turn static linearity into a temperature-dependent curve warp.
3) Temp/stress/aging (ΔTC, gradients)
Uniform drift mainly moves gain/offset.
Gradients and self-heating change ratios locally → INL/DNL shape changes across temperature.
Long-term shift can invalidate static calibration if coefficients age out.
Verification focus (static)
Capture full INL/DNL curves (not only peak numbers) and check for repeatable structure.
Repeat sweeps across temperature points to see whether error is a global shift or a shape change.
Use repeated samples/averaging to separate noise from deterministic static error patterns.
Static accuracy in R-2R is dominated by ratio mismatch and switch spread, often producing structured INL/DNL patterns and temperature-dependent curve warping.
Dynamic artifacts: glitch, settling, major carry
Dynamic behavior is dominated by what happens at the update edge. An R-2R ladder changes code by flipping multiple switches,
injecting charge and coupling into the output node. The immediate result is a glitch impulse (a short transient with energy),
followed by convergence to the final value through the node impedance and return paths. Worst-case dynamics often occur at
major-carry transitions, where many bits toggle in the same update.
What to measure (use consistent definitions)
Glitch impulse: transient energy around the update edge (more meaningful than peak-only numbers).
Overshoot / undershoot: large-step excursion beyond the final value.
Settling time: time to enter and stay within a defined band (for example, to ±0.5 LSB or to a ppm target).
Worst-case code step: compare small steps to major-carry steps to expose boundary-limited behavior.
Why major-carry is usually worst-case
Many switches toggle at once → charge injection and coupling add up.
Small timing skews between switches create a larger composite transient.
The ladder’s effective node impedance changes more abruptly at boundary codes.
Where the settling “tail” comes from
Output node RC: code-dependent impedance and parasitics slow convergence.
Reference/return recovery: finite reference impedance and return paths extend recovery.
Residual switching artifacts: injected charge and coupling can leave a slow-decaying residue.
Practical debug splits (fast root-cause hints)
If tails track reference decoupling/impedance → suspect reference/return behavior.
If tails track load/capacitance → suspect output-node RC and buffering interaction.
If worst cases track boundary codes and update rate → suspect switching transients.
Major-carry transitions often produce the largest glitch and longest tails because many switches toggle at once and the output/return network is disturbed most severely.
Distortion & spectral cleanliness
Spectrum quality is the observable “signature” of both static and dynamic errors. Static weight errors tend to produce
harmonics and structured distortion. Dynamic artifacts (glitch and incomplete settling) tend to produce
code-pattern dependent spurs, sidebands, and noise-floor rise. The goal is to connect each spectral shape
to a likely mechanism before attempting fixes.
Harmonics often indicate static nonlinearity (weight/curve errors).
Discrete spurs often indicate periodic or code-pattern dependent mechanisms (switching/return coupling).
Noise-floor rise often indicates dynamic residue spreading energy (glitch/settling not contained in the window).
Sidebands often indicate modulation-like behavior (periodic disturbance of amplitude/phase).
Code-pattern dependent spur hints
Changing output frequency changes which codes are visited and how often boundary codes occur.
Changing update rate changes how switching residue fits inside the observation window.
Changing amplitude/offset shifts code distribution and can amplify or suppress boundary-driven spurs.
Minimal verification actions (without taking over clocking pages)
Sweep frequency at fixed amplitude to see whether distortion is harmonic-dominated or spur-dominated.
Change update rate (or interpolation setting) to test whether spurs track the update edge behavior.
Shift amplitude/offset to move code distribution away from boundary transitions and observe spur movement.
Spectrum shapes reveal mechanisms: static nonlinearity tends to raise harmonics, while glitch and incomplete settling create code-pattern dependent spurs, sidebands, and noise-floor rise.
Calibration & trim options
R-2R calibration is most effective when the error is static and repeatable: weight/ratio-related nonlinearity,
plus global gain and offset. Calibration is far less effective against dynamic artifacts (glitch and incomplete settling) because
those are dominated by switching energy, node impedance, and return-path behavior rather than by a stable transfer curve.
Trim vs digital LUT (what each can realistically correct)
Factory trim: corrects die-level, slowly varying static terms (gain/offset and dominant weight errors) to stabilize baseline specs.
Digital LUT calibration: corrects repeatable static transfer errors measured at the system level (including board-level offsets and gains).
Background calibration (when applicable): tracks slow drift (temperature/aging) if extra measurement time and digital resources are acceptable.
When calibration is worth it
INL/DNL curves show stable, repeatable structure across repeated sweeps.
Errors behave like gain/offset + smooth shaping, not like update-edge chaos.
Temperature shifts mainly move the curve, not warp it aggressively.
Why LUT cannot “fix” glitch or settling
Glitch impulse is switching energy at the update edge; it depends on timing, coupling, and instantaneous node conditions.
Settling tail depends on the output/reference/return network; the residue is not a static mapping error.
Dynamic artifacts change with update rate, load, and layout; static correction tables do not track these dependencies.
Background calibration (only the applicability rule)
Best for slow drift: temperature and aging that change coefficients over minutes to months.
Requires observability: a measurement path or reference points to estimate coefficients.
Requires budget: extra time, firmware/FPGA resources, and verification coverage.
Calibration is strongest on static, repeatable terms (gain/offset and stable INL/DNL shaping) and weak on update-edge artifacts (glitch/settling) that depend on return paths and dynamics.
Reference sensitivity & switching return paths
R-2R ladders can be unusually sensitive to reference impedance and return-path geometry. During code updates,
switching currents disturb the reference network. If the reference source and decoupling cannot hold a low-impedance loop, the result is
reference bounce that shows up as code-pattern dependent error: large steps look dirty, spurs appear, and settling tails extend.
This section focuses on mechanism, symptoms, and verification—not a full reference selection guide.
Compare FFT results under different code distributions (spur movement implies code-pattern coupling).
Probe VREF close to the DAC reference pins during major-carry activity (bounce coincident with updates is a strong indicator).
Boundary (to avoid overlap with reference/driver pages)
No “reference part selection cookbook” is provided here.
No deep buffer stability or filter design is expanded here.
Focus stays on the R-2R mechanism, symptoms, and proof-by-measurement.
During updates, transient switching currents can bounce the reference if the loop is long or shared. A short local decoupling loop and clean return paths reduce code-pattern dependent error, spurs, and settling tails.
Measurement & debug playbook
A good R-2R evaluation separates static transfer, update-edge dynamics, and reference/return sensitivity.
The same hardware can look “great” or “bad” depending on stimulus, capture bandwidth, waiting time, and code distribution.
This playbook focuses on minimum must-run tests and how to read the results to reach a root-cause direction.
Must-run test set (R-2R-focused)
Static: INL/DNL code sweep with controlled waiting time and repeated samples.
Dynamic: step response (small-step vs major-carry) and settling-to-band measurement.
Spectral: FFT for THD/SFDR with amplitude/offset sweeps to expose code-pattern effects.
Glitch energy: integrate a fixed window around the update edge (glitch impulse).
Temperature/time: repeat key tests across temperature points and a long-duration hold.
Static sweep conditions that decide truth
Use a defined settling wait before sampling each code.
Use repeated samples per code to separate noise from structured error.
Check INL shape stability across repeated runs (repeatable vs random).
Dynamic capture conditions that decide meaning
Compare small-step and major-carry transitions (worst-case exposure).
Define settling to a band (LSB or ppm) and hold time in-band.
Fix bandwidth and window when comparing glitch impulse.
Temperature/time: distinguish drift types
Gain/offset drift looks like shift/scale and is often calibratable.
INL shape warp changes curve shape and often indicates ratio/return sensitivity.
Long holds reveal slow recovery or thermal equilibrium effects.
Symptom → first root-cause direction (fast triage)
INL/DNL looks good but SFDR is poor → suspect update-edge residue, reference bounce, return paths, code-pattern spurs.
Small step is clean but major-carry step is dirty → suspect boundary-code switching + reference/return disturbance.
SFDR changes a lot with offset/amplitude → suspect code-distribution dependence (boundary codes and coupling).
Calibration works at room but fails across temperature → suspect INL shape warp (not pure gain/offset).
A minimal flow that makes R-2R problems measurable: define stimulus and capture, compute the right metrics, then branch by symptom to a static or dynamic direction.
Engineering checklist
This checklist compresses the page into actions that can be reviewed and verified. Each action is paired with the primary risk it covers
and the minimum verification that proves it is under control. No new theory is introduced here; this is the closure step for design and bring-up.
Quick checklist (actions → risks → verify)
Run a boundary-code step test → exposes major-carry worst-case → verify settling to band and overshoot.
Measure glitch impulse with a fixed window → controls update-edge energy → verify repeatability across codes.
Map SFDR vs amplitude/offset → catches code-pattern spurs → verify spur movement and suppression.
Probe VREF near the pins during steps → catches reference bounce → verify bounce reduction with local loop changes.
Repeat key tests across temperature → distinguishes drift types → verify shape stability vs pure gain/offset.
A closure checklist that pairs each design action with the risk it covers and the minimum measurement that proves the risk is controlled.
Applications (R-2R fit logic)
R-2R ladder DACs are a strong choice when area/cost efficiency and medium-to-high update rates are needed,
while keeping a practical path to predictable static accuracy. Application fit is best expressed as
constraints → failure modes → datasheet fields → minimum verification.
General bias / setpoints
Area/CostModerate rateStable DC
Constraints: monotonic behavior, predictable DC error, slow drift control.
Slow code sweep with a defined settling wait; repeat across temperature points to separate gain/offset drift from INL shape changes.
Mid-speed waveforms / function gen
Glitch-criticalSettling-criticalSpectral purity
Constraints: clean update edges under large code steps; stable settling to a defined band.
Failure modes: major-carry spikes, long settling tails, code-pattern spurs that move with offset/amplitude.
Watch these fields
Settling to bandGlitch impulseTHD/SFDRDigital feedthroughREF sensitivity
Minimum verification
Step test (small-step vs major-carry) + fixed-window glitch integration + FFT sweeps vs offset/amplitude.
Multi-channel control (sync updates)
Sync updateMatchRepeatability
Constraints: deterministic updates across channels, consistent settling, predictable mismatch behavior.
Failure modes: time skew appearing as “noise/spikes”, mismatch drift across temperature, inconsistent step edges.
Watch these fields
LDAC / latchUpdate timingGain/Offset matchDrift match
Minimum verification
Multi-channel step overlay under a shared trigger; verify time alignment and settling-to-band across temperature.
What is intentionally not covered here
Direct-RF / GSPS-class transmit chains, hi-fi audio reconstruction pipelines, and PLC-style ±10 V / 4–20 mA front-ends are handled in dedicated application pages.
This section stays focused on R-2R fit logic and the minimum checks that keep projects from failing late.
Use the “constraints → spec fields” column to avoid mis-selecting a part that looks good on INL/DNL but fails on major-carry dynamics or reference/return sensitivity.
IC selection logic (R-2R ladder DACs)
Selection for R-2R ladder DACs should start from the output model and the measurement closure plan.
The fastest path is: pick output form → filter by “must-not-fail” specs → confirm with minimum tests → lock a reference/return plan.
Example part numbers below are provided as a practical shortlist to anchor the selection workflow.
Step 1 — Choose the output form
Voltage-output (unbuffered or buffered): simplest for DC setpoints; prioritize INL/DNL, drift, and reference handling.
Current-output / multiplying DAC (MDAC): strongest for mid-speed waveforms and precision scaling; prioritize glitch impulse, settling-to-band, and reference/return behavior.
ADI AD5541A (16-bit, unbuffered): segmented architecture with an R-2R ladder for lower bits; good for DC accuracy when the load is controlled.
ADI AD5761R / AD5721R (16-bit, buffered): R-2R DAC followed by an output buffer; useful when a buffered voltage output is needed while keeping R-2R-based core behavior.
Minimum bring-up for this group
Slow code sweep with a defined settle wait; repeat across temperature points. Verify REF feedthrough and DC repeatability before adding fast updates.
Avoid “wrong-architecture” substitutions
If the project specifically needs an R-2R ladder behavior, do not substitute a resistive-string DAC family (for example, Microchip MCP4901/4911/4921), because the error and glitch mechanisms differ and the debug playbook will not transfer cleanly.
Short, R-2R-specific answers that close common bring-up and selection questions without expanding into other DAC architectures or dedicated application pages.
Q
INL looks great, but performance breaks across temperature. What is the most common reason?
Short answer: The error is often INL shape warp (ratio/return sensitivity), not simple gain/offset drift.
Why it happens
Temperature changes ladder ratios and switch behavior unevenly, altering the curve shape.
Reference/return sensitivity can turn large-code transitions into temperature-dependent error.
Q
Why does reference source impedance create code-pattern errors and spurs in an R-2R DAC?
Short answer: Switching draws code-dependent transient current from VREF, so source impedance turns that current into VREF bounce, which becomes code-correlated error.
Why it happens
Reference disturbance aligns with update edges and can modulate the output in a code-dependent way.
Major-carry transitions maximize the transient current and make bounce-driven spurs easiest to see.
How to verify
Probe VREF at the pin with a consistent method while running major-carry steps.
Run FFT spur mapping vs offset/amplitude; bounce-driven spurs often move with code distribution.
Common pitfall
Treating VREF as “DC only” and ignoring its transient behavior during large code transitions.
Q
INL/DNL plots are beautiful but FFT is ugly. What is the first diagnostic step?
Short answer: Sweep offset and amplitude (code distribution) and see whether spurs move or change drastically.
Why it happens
Static INL/DNL does not capture update-edge residue and reference-bounce coupling.
Code-pattern spurs often reveal themselves only when boundary codes are visited frequently.
How to verify
Keep frequency constant, sweep offset/amplitude, and track dominant spur movement.
Run a major-carry step test under the same update settings to check time-domain residue.
Common pitfall
Trying to “explain the spectrum” without first checking whether the spurs are code-distribution dependent.
Key spec / metric: SFDR vs amplitude/offset, major-carry behavior
Q
How can “spur movement” distinguish static nonlinearity from dynamic/return-path problems?
Short answer: Static nonlinearity tends to produce more stable harmonic patterns, while return-path or bounce-driven spurs often change with offset/amplitude and worsen on major-carry steps.
Why it happens
Static weight error maps into deterministic transfer curvature, often reflecting as consistent harmonics.
Dynamic residue and bounce depend on update edge, code distribution, and shared impedance.
How to verify
Track spur amplitude/location while sweeping offset/amplitude; large changes indicate code-pattern dependence.
Check whether the worst artifacts correlate with major-carry transitions in the time domain.
Common pitfall
Assuming every spur is “INL-related” without checking code-distribution sensitivity first.
