EMC & Edge Control for I2C, SPI & UART
← Back to: I²C / SPI / UART — Serial Peripheral Buses
This page turns I²C/SPI/UART EMC from “trial-and-error” into a controlled loop: manage edge energy, return paths, and common-mode coupling so emissions drop without sacrificing timing or immunity.
It provides practical knobs, first-check diagnostics, and pass-criteria placeholders to standardize design, bring-up, and production verification.
Definition & Scope: EMC & Edge Control for Serial Peripheral Buses
This page focuses on EMC-driven signal shaping for board-level peripheral buses (I²C / SPI / UART): how edge rate, return paths, common-mode currents, and crosstalk translate into emissions and immunity failures. The goal is not “slower equals safer,” but controlled energy + controlled paths + controlled coupling.
- Edge/EMC control toolbox: adjustable knobs (drive strength, slew, series-R, RC, thresholds, buffering) with practical trade-offs.
- Pass-criteria placeholders: structured acceptance checks (shape-based and behavior-based) with replaceable thresholds (X) for each project.
- Measurement loop: a repeatable way to prove the coupling path (scope + near-field + targeted triggers) before and after changes.
- Production hardening: how to convert fixes into gates/checklists so results stay stable across assemblies, cables, and batches.
Most serial-bus emission issues come from fast edges exciting unintended antennas: broken return paths (large loop area), imbalance that converts differential energy into common-mode current, and long aggressor segments (SCLK / push-pull transitions) coupling into cables, shields, or chassis.
Immunity failures often show up as threshold-crossing mistakes: I²C’s wired-AND/open-drain is sensitive to slow crossings and CM disturbances (NACK / stuck-low); SPI failures cluster around sampling windows (CRC bursts / bit-slip); UART is vulnerable to false start/stop/break detection (framing/parity errors).
Shape edges so high-frequency energy is not unnecessarily excited. The objective is fewer strong harmonics, fewer ringing events, and fewer repeated threshold crossings.
Prevent large loop areas and avoid discontinuities across splits/planes. Minimize CM current by maintaining balance and keeping the reference path short and continuous.
Reduce aggressor-to-victim coupling using spacing, pairing, controlled transitions, and correct shield/chassis strategies so the bus does not become an antenna when cables and enclosures are involved.
- Detailed pull-up math / RC rise-time calculation (use the dedicated pull-up/network page).
- Full SPI signal-integrity/termination deep dive (use the long-trace SI and SCLK skew pages).
- Comprehensive ESD/surge device catalog and selection (use the port protection page).
- Complete protocol recovery/state-machine patterns (use the error handling & recovery page).
Related pages (replace links): Open-Drain & Pull-Up Network · Long-Trace SI · Port Protection · Error Handling & Recovery
Failure Signature Map: What EMC Problems Look Like on I²C / SPI / UART
EMC-driven issues rarely appear as “clean, repeatable bugs.” They show up as clusters of symptoms. This map turns symptoms into likely coupling paths and a first check that produces evidence quickly.
Peak appears when a clocked bus speeds up (SPI SCLK / fast UART edges)
Likely path: edge energy excites aggressor loops and converts to common-mode on nearby structures.
First check: confirm edge rate and ringing; inspect return continuity along the aggressor route.
Hot spot near a connector/cable even when board traces are short
Likely path: common-mode current is flowing on the cable/shield/chassis (unintended antenna).
First check: verify shield/chassis bonding strategy and where return current actually closes.
Emissions are sensitive to hand proximity or enclosure assembly steps
Likely path: return discontinuity or capacitive coupling to chassis changes the effective antenna.
First check: identify plane splits, gaps, and cable routes that force return current detours.
Symptom: Random NACKs or corrupted reads on a “healthy” bus
Likely path: common-mode disturbance shifts thresholds or injects glitches during slow crossings.
First check: look for multiple threshold crossings and slow edge segments; verify reference/return stability.
Symptom: Bus stuck low after noise events (brown-out / ESD / EFT)
Likely path: line clamps or state machines latch when CM current and return detours create deep low excursions.
First check: verify where current is being sunk (device pin vs clamp path); confirm return continuity at the noisy boundary.
Symptom: Clock stretching becomes “worse” in the enclosure than on bench
Likely path: immunity margin shrinks; slow edges spend longer near thresholds, amplifying noise impact.
First check: compare edge shapes and CM environment (cable/shield/chassis); confirm whether slow crossings correlate with stalls.
Symptom: CRC bursts after a single disturbance
Likely path: ringing creates repeated threshold crossings; a short event can corrupt multiple bits in a frame.
First check: inspect SCLK/MISO at the receiver for overshoot/ringing; verify return path and aggressor coupling length.
Symptom: Bit-slip or mode-like misalignment without any firmware change
Likely path: sampling edge becomes ambiguous due to ringing/crosstalk near the decision threshold.
First check: check whether the sampled line crosses the threshold more than once per bit; review aggressor proximity (SCLK).
Symptom: Works at low speed, fails sharply above a specific frequency
Likely path: edge energy and interconnect reflections exceed the receiver’s sampling tolerance.
First check: compare waveforms at the receiver, not only at the driver; validate return continuity across layer changes/splits.
Symptom: Framing/parity errors increase near switching loads
Likely path: ground bounce/common-mode pickup shifts the apparent logic level during start/stop decisions.
First check: measure signal vs its true reference; verify return and chassis bonding near the disturbance source.
Symptom: Spurious break/wake events on long harness runs
Likely path: harness acts as an antenna; CM current creates long low excursions that resemble break conditions.
First check: validate cable routing/shield termination and where CM current returns; check threshold filtering/edge shaping.
Symptom: “Garbled characters” correlate with mechanical assembly changes
Likely path: reference shifts and return detours change noise coupling and effective thresholds.
First check: compare assembled vs unassembled return paths; confirm whether CM environment changed (chassis contact points).
- Emission ≠ immunity: a product can radiate less while remaining sensitive to external CM noise and threshold disturbances.
- Assembly/cabling changes CM paths: chassis contact, shield bonding, and harness routing can re-route common-mode currents and reduce margin.
Physics You Actually Use: Edge Rate → Spectrum → Coupling (Return & Common-Mode)
Practical EMC control starts with a single chain: edge rate sets high-frequency energy, then energy follows return paths and converts into common-mode currents when imbalance or reference instability exists. The goal is not “the slowest edge,” but a stable threshold crossing with controlled loop area and controlled coupling.
Faster transitions increase dV/dt and di/dt, which strengthens high-frequency components. Those components are the easiest to radiate and the easiest to couple into neighboring nets and cables.
Use a simple rule: measure rise/fall time at the receiver (not only at the driver). Shorter rise time pushes energy into higher bands and increases the chance of radiated peaks and aggressive crosstalk.
Practical check: if ringing causes multiple threshold crossings per bit/edge, treat it as an EMC + integrity risk even if logic still “works.”
- Overshoot/undershoot and sustained ringing → extra threshold crossings (SPI bit-slip / UART false start).
- Strong near-field hot spots near SCLK/connector regions → emissions dominated by loop/CM paths.
- Sensitivity to enclosure or hand proximity → the “antenna” is in the structure/cable path, not in the MCU register setting.
A slower edge spends more time near the switching threshold. Under common-mode noise or reference bounce, this increases the chance of ambiguous decisions (I²C NACK/stalls, SPI window shrink, UART framing/break). Edge control aims for clean, single crossings with adequate margin—not the maximum rise time.
A “signal” is a loop: forward current on the trace and return current on the nearest reference path. Any interruption forces the return to detour, increasing loop area and strengthening radiation and coupling.
Plane splits, layer transitions without stitching, and connector pinouts that separate signal from its reference turn a compact loop into a large loop. Large loops radiate more and couple more into adjacent nets and shields.
- Imbalance (asymmetry, mismatched return, uneven loading) converts DM into CM.
- Unstable reference (ground bounce / chassis contact variability) injects CM shifts.
- Incorrect shield bonding can route CM current onto shield/harness → the system becomes an antenna.
- Measure at receiver pins: look for ringing and multiple crossings.
- Near-field scan: find hot spots around connector/shield bond and SCLK regions.
- Compare assembled vs open-bench: if sensitivity changes strongly, suspect CM path and return detours.
Edge-Shaping Toolbox: What Can Be Changed (and the Side Effects)
Edge control is a set of knobs. Each knob shifts EMI, timing margin, immunity margin, and power differently. Use the lowest-risk, easiest-to-verify knobs first and verify at the receiver.
- Programmable slew rate / drive strength / IO mode
- Driver output impedance options (if available)
- Clock/output gating during idle (reduce unnecessary transitions)
- Source series-R to reduce ringing / overshoot
- Small RC / small C shaping (use carefully; can harm thresholds)
- Topology clean-up: shorten aggressors and keep a continuous reference
- Schmitt / hysteresis inputs to prevent chatter
- Input filtering / deglitch (watch added delay)
- Threshold planning across rails (avoid “thin” noise margin)
- Buffer / re-driver / re-timer for controlled edges
- Isolation strategy changes (delay + CMTI budget)
- Shield/chassis bonding strategy to reduce CM antenna behavior
Slower edges
- EMI: often improves (less HF energy)
- Timing: can degrade (setup/hold risk; sampling windows tighten)
- Immunity: can degrade (threshold dwell time increases)
- Power: depends (pull-ups and switching losses trade)
Series-R / RC shaping
- Can create rise/fall asymmetry → SPI duty/phase sensitivity
- Can shift threshold crossing time → UART framing risk
- Can hide problems at the driver while the receiver still sees ringing
Schmitt / filtering / buffering
- Schmitt reduces chatter but may add delay and change threshold
- Filtering can reject noise but can distort edge placement
- Buffers help edge control but introduce latency and may change timing budget
- Start with reversible settings: slew/drive/IO mode → verify receiver crossings and near-field hot spots.
- Add minimal damping: source series-R → verify ringing reduction and error statistics.
- Fix path/architecture: return continuity, topology, buffering, and shield/chassis strategy → verify reduced sensitivity to assembly and cabling changes.
Right-Sizing Pull-Ups & Terminations for EMC (Not Just Timing)
Pull-ups and terminations are not only “timing parts.” They also control edge energy, ringing/threshold crossings, and common-mode excitation. The objective is a receiver waveform that crosses the logic threshold once per edge, settles quickly, and stays robust under noise and assembly variability.
- Pass (X placeholder): threshold crossings per edge ≤ X.
- Pass (X placeholder): ringing amplitude at receiver ≤ X% of swing.
For push-pull buses (SPI/UART), reflections that persist near the sampling window can create bursty errors. For open-drain (I²C), edge “stair-steps” and long settling extend susceptibility to interference.
- Avoid strong asymmetry between rising and falling edges.
- Keep return paths continuous so differential energy does not leak into chassis/shield currents.
- Very fast rising edge + hot spots: pull-up may be too strong or edge shaping too aggressive.
- Very slow crossing near threshold: pull-up may be too weak; immunity risk rises under common-mode noise.
- Step-like rise / multi-stage settling: topology reflections or detoured return likely; treat as an EMC + robustness warning.
- Ringing with multiple crossings: damping is insufficient (source-R / termination / return continuity).
- Error bursts (CRC/framing) not random: a reflection is likely landing near the sampling window.
- Strong sensitivity to enclosure/cable changes: common-mode paths and shield bonding are dominating.
- Probe at the receiver: count crossings and estimate settling.
- Near-field scan: check connector, SCLK regions, and shield bonds for hot spots.
- Compare “open bench” vs “assembled”: large deltas indicate path/common-mode dominance.
- Stronger pull-up (smaller R): faster rise and shorter threshold dwell; may worsen EMI and increase pull-up power.
- Weaker pull-up (larger R): lower high-frequency energy and often lower EMI; may reduce immunity due to longer threshold dwell.
- Prefer reversible knobs first (slew/drive/buffering) before pushing pull-ups to extremes.
- Source series-R: often the first, low-risk damping knob to reduce ringing and multi-crossings.
- Endpoint termination: reduces endpoint reflections but increases load and may tighten timing/power budgets.
- Accept success only when receiver crossings reduce and error statistics improve under worst-case assembly/cabling.
- I²C pull-up RC and rise-time compliance math → (link to pull-up sizing page)
- SPI transmission-line/termination calculations → (link to SI/termination page)
- Protection device capacitance vs edge distortion → (link to port protection page)
Shielding, Cabling & Off-Board Runs: Stop Turning the Bus into an Antenna
When a serial bus leaves the PCB, the return path becomes a system property (connector, cable geometry, chassis bonding). The main risk is not only noise pickup, but common-mode current turning shield/harness structures into an antenna. This section focuses on practical wiring/shielding/pinout rules and flags long-reach cases for dedicated extender pages.
- The bus crosses a connector and runs through a cable/harness.
- Results change with enclosure assembly, harness routing, or chassis contact.
- Strong noise sources are nearby (motors, relays, inverters, fast power nodes).
- Return current detours → loop area grows → radiation and coupling increase.
- Differential energy converts to common-mode → shield/harness carries CM current.
- Keep a nearby return: pair signals with a reference conductor whenever possible.
- Treat shield bonds as current paths: minimize loop area and bond length.
Where does common-mode current flow when noise couples into the harness? A shield is a conductor; poor bonding can create a large loop that radiates more than an unshielded cable.
- Near-field probe at shield bond: strong hot spot implies shield carrying CM current.
- If changes in bond length or chassis contact dramatically shift behavior, the CM loop is dominant.
- Prefer short, low-inductance bonds to chassis at connector entry/exit.
- Avoid forcing shield current to return through long PCB ground detours.
- Pair signal pins with nearby return pins (ground/reference) whenever possible.
- Place the fastest aggressor (often SCLK) adjacent to strong reference returns.
- Avoid routing signal returns across split grounds or through long chassis loops.
If the run length or noise environment exceeds a safe margin, treat single-ended signaling as high risk and move to the dedicated long-reach/extender strategy pages for controlled-cable and protocol-specific solutions.
Link placeholders: Long-Reach I²C over Cabling · Bridges & Extenders
Crosstalk Control: Spacing, Pairing, Guarding, and the Real Aggressors
Crosstalk becomes predictable when it is treated as a coupling problem with three dominant levers: coupling length, spacing, and return continuity. The most common aggressors on serial peripheral buses are not subtle: the fastest, most repetitive edges (often SCLK) and any signal that crosses a return discontinuity.
- SCLK / clock-like nets: highest toggle activity and fastest edges.
- Fast push-pull edges: CS, GPIO strobes, or mode pins with sharp transitions.
- Cross-split signals: any net that crosses a return discontinuity (split ground / reference change).
- Aggressor-only toggling: toggle SCLK (or candidate net) while holding victim lines in a static state.
- Receiver-first scope point: check whether the victim sees spikes that approach/cross threshold.
- Hot spot scan: near-field probe at clocks, connectors, and split edges to confirm emission sources.
- Shorten parallel run length: avoid long, tight side-by-side routing.
- Increase spacing near aggressors: prioritize SCLK separation from sensitive victims (MISO, UART RX, SDA/SCL).
- Keep return nearby: maintain a continuous reference and provide return continuity across transitions.
- Guarding (only if done correctly): a guard trace helps only when it is well-referenced and does not create new discontinuities.
- Long, close parallelism dominates: fix geometry first (length/spacing). Edge-rate is secondary.
- Return discontinuity dominates: fix the return path first (stitching/bridge) before chasing edge settings.
- No PCB change possible: reduce edge rate (slew/series-R) and apply localized return fixes (short bonds/jumpers).
- Victim spikes remain below threshold with margin (X placeholder).
- Multi-crossing events disappear near the sampling window.
- Error bursts drop (CRC, framing, NACK/retry counters).
- Assembly sensitivity decreases (enclosure/cable/harness routing changes no longer flip behavior).
Grounding & Return Path Planning for Buses (Across Split Grounds)
Split grounds and reference changes do not “block noise.” They often block return current. When return current detours, loop area grows, radiation increases, and differential energy converts into common-mode currents that couple into shields, chassis, and harness structures.
- Connector and split edges become hot spots in near-field scans.
- Bursty errors appear (SPI CRC bursts, UART framing spikes, I²C retries) and worsen when assembled.
- Add stitching near the transition to provide a short, low-inductance return path.
- If needed, add a local high-frequency bridge (capacitive bridge) to prevent return detours.
- EMI and crosstalk degrade together; resistor tweaks only partially help.
- Sensitivity to harness routing and chassis contact increases.
- Re-route to avoid crossing splits; keep signal and return on the same reference where possible.
- Provide a controlled crossing point with local return stitching/bridging if unavoidable.
- Assembly-dependent behavior (“bench OK, in enclosure unstable”).
- Hot spots at connector entry and shield bonding points.
- Reduce the loop: short, low-inductance chassis bonds at connectors.
- Avoid forcing shield/chassis current to return through long PCB ground detours.
Immunity Hardening: Filters, Thresholds, and Firmware Hooks (EMC-Driven)
This section focuses on minimum necessary robustness driven by EMC: preventing noise-induced false edges, turning sporadic disturbances into measurable events, and recovering quickly without expanding into full protocol-stack design. Deep protocol behavior belongs in the dedicated bus/protocol pages.
- Schmitt / hysteresis: reduces sensitivity to slow/noisy crossings; improves margin against common-mode bursts.
- Digital deglitch filters: rejects narrow spikes; prevents false edges and false start/stop conditions.
- Edge shaping (small C / RC at the right place): reduces high-frequency noise pickup and false toggles when used within timing slack.
- Do not hide real edges: any filter that delays/shortens pulses must be validated against worst-case clock/baud and duty cycles.
- Do not create asymmetry: RC that slows only one direction can shift thresholds and degrade sampling margin.
- Validate at the receiver: accept changes only if receiver-side crossings remain correct under worst-case assembly/noise.
This page covers EMC-driven hardening only. Protocol-level corner cases (state machines, arbitration nuances, command framing rules) should link to the dedicated bus/protocol pages as needed.
- Timeouts: prevent infinite stalls (hung bus, stuck-low, missing edges).
- Retry / re-sync: bounded retry counts; controlled resynchronization after bursts.
- De-bounce of “mode” signals: avoid false wake/break triggers on noisy lines.
- Event counters: convert immunity into measurable statistics (not anecdotes).
- Use bounded retries and escalate to a higher-level reset only after repeated bursts.
- Record “what happened” (error type + time + last state) before clearing status.
- Prefer a recovery path that is reversible and fast to validate under noise injection.
- Error rate: errors per N transactions ≤ X.
- Retry rate: retries per N operations ≤ X.
- Burst severity: max consecutive failures ≤ X.
- Assembly sensitivity: enclosure/harness changes do not exceed X delta in error counters.
Timestamp · bus instance · error class (NACK/CRC/framing/timeout) · last known state · recovery action taken · post-recovery status. This turns immunity into a closed-loop engineering problem.
Measurement & Debug Loop: Prove the Path (Scope + Near-Field + Triggers)
EMC fixes must be supported by an evidence chain: correct probing, observation at meaningful points (receiver + connector), a trigger strategy that captures sporadic bursts, and a conclusion that maps back to a coupling path (aggressor, return, or common-mode).
- Threshold crossings: count multi-cross events near the sampling window.
- Settling vs timing: verify the waveform settles before the decision point.
- Assembly deltas: compare open-bench vs enclosed/harnessed conditions.
- Use short ground (spring) to avoid measurement artifacts.
- Measure at the receiver pin / TP, not only at the driver.
- If needed, use differential measurement across the signal/return reference to reduce probe-loop pickup.
- Scan hot spots (connector entry, clock nets, split edges, shield bonds).
- Compare hot spots before/after a change to confirm whether energy moved or decreased.
- Treat strong activity on shield/chassis areas as a common-mode path clue.
- Glitch / runt: capture narrow spikes on victim lines near thresholds.
- Burst windows: trigger on repeated errors within a time window (CRC/framing/NAK bursts).
- Timeout markers: use firmware “debug pin toggles” on timeouts to align scope capture with events.
Receiver waveform anomalies + a matching near-field hot spot should map to one of three primary paths: aggressor coupling, return discontinuity, or common-mode on shield/chassis. This yields a focused fix, not a broad “tweak everything” cycle.
Engineering Checklist (Design → Bring-up → Production)
This section turns EMC & edge control into an executable SOP with three gates. Each gate defines what to check, how to prove it, and what must be recorded so changes (harness, enclosure, suppliers) do not silently reintroduce failures.
- Edge knobs exist: programmable slew/drive or validated series-R footprints at primary aggressors (often SCLK).
- Return is continuous: reference changes and split crossings have a defined, short return path (stitch/bridge location planned).
- Crosstalk risks mapped: long parallel runs, tight spacing, and clock adjacency are identified and mitigated.
- Off-board strategy defined: connector pin pairing, shield bonding concept, and harness routing constraints are documented.
- Observability is designed-in: receiver-side test points (TP) and a firmware trigger pin exist for burst capture.
- Receiver-side TP exists for each critical net group (Yes/No).
- Return stitching/bridge locations are defined at every reference change (Yes/No).
- Primary aggressor(s) have at least one reversible edge-control option (slew setting or series-R footprint) (Yes/No).
- Only driver-side probing is possible; receiver-side TP is missing.
- Clock nets cross split grounds without a defined return bridge.
- Shield/chassis current is forced to detour through long PCB ground paths.
- Receiver-side shape checks: no multi-crossing near thresholds; ringing does not enter the decision window.
- Aggressor isolation test: toggle aggressor (e.g., SCLK) while victims are static; confirm victim spikes stay below margin.
- Assembly delta: compare open-bench vs enclosure/harness; measure sensitivity to routing and chassis contact.
- Baseline counters: log error/timeout/retry/CRC/framing metrics per N transactions with a fixed test posture.
- Receiver-side multi-cross events per capture ≤ X.
- Error rate / retry rate per N ops ≤ X.
- Assembly sensitivity (enclosure/harness) changes counters by ≤ X.
- Probe ground lead is long; ringing is created by measurement loop area.
- Only “EMI pass/fail” is tracked; immunity is not tracked as counters.
- Triggers are not aligned to events; sporadic bursts cannot be captured.
- Component equivalency: any change to ESD arrays/TVS, small caps, buffers/translators/isolators triggers waveform + counter re-check.
- Harness control: cable vendor/length/shield termination/pinout revisions are versioned and validated.
- Assembly control: chassis bonding points and contact hardware are controlled (inductance matters).
- Regression triggers: field burst clusters, supplier swaps, enclosure revisions, or ESD events trigger a defined re-test flow.
- Lot-to-lot counter delta ≤ X for the standard test posture.
- Harness revision requires re-qualification (Yes/No) and is traceable in logs (Yes/No).
- After defined ESD/EMC events, regression test is executed within X timeframe (policy placeholder).
- ESD/TVS vendor swap changes capacitance/symmetry and shifts common-mode behavior.
- Shield termination method changes without a controlled re-test.
- Chassis bonding hardware change increases inductance and reopens common-mode paths.
Applications & IC Selection Notes (Buffers / Translators / Isolators with Edge Control)
This section selects components only where they strongly impact EMC and edge behavior. It avoids broad catalogs and focuses on controllable slew, threshold behavior, common-mode tolerance, and propagation delay risks. Example part numbers are included for reference; verify package, suffix, and availability.
- EMI dominated by a clock/aggressor edge: use a buffer/driver with controllable slew or add a safe series-R option.
- Immunity dominated by false edges: prefer inputs with Schmitt/hysteresis or validated deglitch behavior (plus firmware counters).
- Split grounds / large CM transients: consider isolation; check CMTI and delay/skew impact.
- Multi-voltage domains: choose translators that preserve bus semantics (open-drain for I²C) and avoid asymmetry.
- Buffer / repeater: control edge energy, reduce reflection sensitivity, manage fanout and segment capacitance.
- Translator: bridge voltage domains; must preserve open-drain behavior for I²C and maintain symmetry for EMC.
- Isolator: break common-mode return paths; demands delay/skew validation and CMTI margin.
Enables reversible tuning of edge energy and ringing sensitivity without redesigning the PCB. Validate receiver-side timing margin after changes.
Impacts reflection and threshold multi-crossing. Strong push-pull outputs can worsen coupling if return paths are weak.
Increases immunity against slow/noisy crossings and narrow spikes. Must not hide valid edges at the worst-case clock/baud.
Determines whether isolation actually solves field failures under fast common-mode transients. Treat wiring and chassis as part of the system.
Isolation and buffering can shrink sampling windows. Validate with receiver-side timing, not only driver-side waveforms.
Extra capacitance or asymmetric clamps can increase common-mode conversion and distort edges (especially on I²C open-drain nets).
Quick check: compare receiver-side rise/fall shape and error counters with/without the device.
Quick check: measure time between threshold crossing and sampling window; look for multi-crossing.
Quick check: trigger on runt pulses near thresholds; compare behavior across assemblies and temperatures.
Quick check: measure receiver-side setup/hold margin with worst-case patterns and burst triggers.
Quick check: isolate aggressor toggling (SCLK) and scan hot spots near splits/connectors.
- TI TCA9517 / TCA9515A — I²C bus buffer/repeater for segmentation and cap isolation.
- TI TCA4307 — I²C hot-swap buffer (useful for stuck-bus recovery strategies and hot-plug robustness).
- NXP PCA9517 / PCA9515A — common I²C buffer families for segmenting and fanout control.
- NXP PCA9615 — I²C to differential extender (off-board risk mitigation; validate the full cable/shield path).
- TI PCA9306 — bidirectional I²C level translator (preserves open-drain semantics; validate pull-up strategy).
- TI TCA9406 — I²C level translator/buffer family commonly used in mixed-voltage I²C.
- TI SN74AXC4T245 / SN74AXC8T245 — direction-controlled level translation (useful for SPI/UART; check edge strength and skew).
- Nexperia 74LVC1G17 — Schmitt-trigger buffer (useful for noise hardening; validate timing at highest rates).
- TI ISO1540 / ISO1541 — I²C isolators (bidirectional I²C isolation; confirm rise-time behavior and pull-up domains).
- Analog Devices ADuM1250 / ADuM1251 — I²C isolation family used for breaking common-mode paths.
- TI ISO7741 / ISO7742 — common 4-ch digital isolators for SPI/UART style signals (delay/skew must be budgeted).
- Analog Devices ADuM1401 — multi-channel digital isolator frequently used for SPI/UART partitions.
- TI TPD4E05U06 — low-cap ESD protection array for high-speed signal lines (verify C and symmetry vs bus needs).
- TI TPD2E007 — compact ESD diode array (commonly used for ports and board edges).
- Littelfuse SP0502BAHT — low-cap ESD array often used at connectors.
- Nexperia PESD5V0S1UL — ESD diode family commonly used for general signal protection.
Use these baskets to anchor the selection process. Do not substitute “similar-looking” parts without re-checking receiver-side waveforms and immunity counters, because capacitance, symmetry, and threshold behavior can change common-mode paths.
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FAQs (EMC & Edge Control) — Fast Troubleshooting
Each answer is a fixed, data-oriented 4-line structure: Likely cause / Quick check / Fix / Pass criteria. Thresholds use placeholders (X) so teams can standardize limits across design, bring-up, and production.
