Open-drain (open-collector) is a one-sided driver: devices can actively pull the line LOW, while the HIGH level is created by the pull-up network.

The pull-up network defines the HIGH level and the rising edge. The open-drain devices define the LOW level. All key margins map to Rpullup, Cbus, sink behavior (IOL/VOL), and leakage paths.

On a shared multi-drop bus, “two devices disagreeing at the same time” is not a corner case. Open-drain makes that disagreement electrically safe by removing the ability to actively drive HIGH.

Open-drain converts “device disagreement” into a controlled electrical outcome: the line can always be pulled LOW without a high-side fight, and the contention current is bounded by the pull-up path.

• Rpullup × Cbus sets the rising edge and noise susceptibility.
• Sink capability sets the LOW-level margin when multiple devices pull down.
• Rail choice determines power-sequencing safety (avoid ghost-powering).

Replace “tuning by feel” with a computable model: every open-drain success or failure maps to R, C, V, I, and leakage.

• Physical meaning: the HIGH transition is a capacitor charge event through Rpullup into Cbus.
• General workflow (no mode-specific constants here): pick the voltage window used by the system for “LOW→HIGH” recognition, then compute/estimate the time for the RC curve to cross that window.
• What inflates Cbus in real boards: trace + device pins + connectors + test pads + probe capacitance.
• Executable takeaway: when tr degrades after an integration step, assume Cbus increased first, then re-check the effective Rpullup.

• Low level is an active sink event: the line voltage is set by the sink device behavior under current, not by an ideal switch.
• Why “I × R” is only a starting point: real devices have an IOL–VOL curve and finite on-resistance; the target is to keep VOL margin under worst case.
• Worst-corner thinking (required): multiple devices can pull LOW simultaneously; temperature and process corners change sink strength.
• Executable takeaway: when VOL is “too high”, audit parallel pull-ups first (Req got smaller), then verify sink capability at the required current.

• Two simultaneous impacts: leakage can pull the HIGH level down and slow the rising edge by stealing pull-up current.
• Common sources: contamination/moisture, connector residue, post-ESD parametric drift, and power-off clamp paths.
• Why “still works but becomes fragile” happens: leakage increases first, reducing noise margin long before a hard short appears.
• Executable takeaway: compare pre/post stress (ESD / humidity) using the same pull-up setting and log the change in rise behavior and static HIGH current (pass threshold X).

This model supports both design-time prediction and bring-up correlation: R and C dominate the rise, IOL/VOL dominates LOW margin, and leakage quietly shrinks both HIGH margin and edge speed.

The goal is not “one resistor value”. The goal is a manufacturing-safe window: Rmin avoids excessive sink current and power, while Rmax preserves edge speed and HIGH robustness.

• R window: [Rmin, Rmax] after tolerance and parallel pull-up accounting.
• Bring-up gates: measure tr and VOL at worst nodes; log rail and environment; pass threshold X.
• If the window collapses: reduce Cbus (segmentation/topology) or add assist devices (buffers/accelerators) via the dedicated subpages.

The workflow produces a bounded resistor range and a clear escalation path when physics makes the window too narrow: either reduce effective capacitance or add assist devices through the dedicated subpages.

Pull-up rail ownership decides more than “logic high”: it determines power-off behavior, noise margin, and whether an unpowered domain gets back-fed through I/O clamp paths.

• Trigger: one domain pulls the bus HIGH while another domain’s VDD is OFF or below its clamp threshold.
• Path: bus pin → I/O clamp / ESD structure → unpowered VDD rail → internal circuitry (partial powering).
• Impact: increased leakage, slowed rising edges, undefined pin states, stuck-low behavior after sequencing, and abnormal standby current.
• Correlation hint: post-ESD or humidity stress can increase clamp leakage, making backfeed easier and the bus more margin-sensitive.

• Audit and unify pull-ups: ensure there is a single “owner” rail (avoid accidental parallel pull-ups across modules).
• Small series resistor (Rs): limits injection peaks and tames ringing, but does not replace structural isolation.
• Translator / isolator boundary: required when domains can be OFF independently or hot-plug scenarios exist (details elsewhere).

The failure is not “logic”: it is an electrical current path from a powered rail into an unpowered domain through an I/O clamp structure. Rail ownership must match power sequencing and clamp behavior.

Treat EMC as a network design problem with knobs. The goal is to reduce ringing and emissions while keeping VIH/VIL margins intact and avoiding false threshold crossings.

• Rpullup × Cbus sets the rise. Excessively fast transitions mainly come from parasitic L/C creating ringing, overshoot, and coupled noise.
• Design target: “slow enough” to reduce high-frequency energy, but not slow enough to violate timing or shrink logic margin (targets belong to the mode page).
• Measurement discipline: probe loading changes Cbus; long ground leads create fake ringing.

• Threshold crossings: ringing or coupled noise can cross VIL/VIH multiple times during one transition.
• Edge sensitivity: sharper edges carry more high-frequency energy and couple more easily into adjacent nets.
• Observed outcome: a short, valid-looking level window can be misinterpreted as a protocol event. Recovery policy belongs to the “Error Handling & Recovery” subpage; the hardware lever here is edge + ringing control.

• Worst-node probing: measure at the far endpoint / largest-C node, not only near the host.
• Timing: rise behavior remains within the chosen target window (pass X).
• Margins: VOL under worst pull-down remains within margin (pass X).
• Ringing: no multiple threshold crossings within X time; overshoot stays within X.

Use the lowest-risk knob first (R-only), then add damping (Rs) if ringing dominates, and treat RC shaping as a last resort requiring worst-case validation against logic thresholds.

These rules focus only on what is tightly coupled to open-drain + pull-up networks: pull-up ownership, accidental parallel pull-ups, defined pull-down return loops, and testability footprints.

• Place pull-ups near the owner domain: the rail and ground reference that define the bus HIGH should be physically close to the pull-up network.
• Avoid distributed pull-ups: pull-ups in multiple corners (modules / mezzanines / daughtercards) often create an unintended parallel Req that shrinks over time as options get populated.
• Failure signature: the same design becomes “harder to pull LOW” or burns more power after a module change, because Req silently decreased.
• Bring-up action: enumerate every pull-up footprint across the BOM (including optional/DNP straps) and compute the worst-case Req when all are populated.

• Pull-up ownership: a single, documented owner rail; no hidden parallel pull-ups when options are populated.
• Return integrity: SDA/SCL does not cross ground splits/slots without a deliberate return bridge.
• Worst-node visibility: at least one far-end TP exists for rise-time/ringing capture.
• Tuning footprints: Rs pad and a controlled DNP option exist; changes require a pass criterion X.

The open-drain LOW state forms a defined current loop. Routing across a split reference plane enlarges the loop and increases ground bounce risk, especially at the far-end worst node.

A scope can “fix” an open-drain bus by adding capacitance, or hide failures with bandwidth/averaging choices. The workflow below removes measurement artifacts first, then maps symptoms to electrical causes.

• Rise-time (tr): measure using a consistent voltage window tied to the system’s VIH/VIL policy; keep the definition stable across builds.
• VOL: measure under the worst pull-down condition expected in-system (multiple devices can pull LOW; temperature corners can reduce sink strength).
• Sequencing state: confirm rails are in the intended power state; ghost-powering can create misleading “almost powered” behavior.

The tree forces artifact checks first (probe/settings/measure point/rail state), then converges to the electrical model variables: R, C, leakage, sink strength, return integrity, and ringing.

This section is a reusable hardware troubleshooting library for open-drain pull-up nets. It focuses on electrical failure signatures and quick checks, and avoids protocol-level recovery algorithms.

• Electrical picture: the bus sees a parallel leakage path (Rleak / Ileak) that drags HIGH down and slows the rise.
• Typical symptoms: idle HIGH level looks “not fully high”, sporadic NACK/false edges, and strong sensitivity to humidity/handling.
• Fast checks:
  • Measure Idle VHIGH at the far-end node: compare to expected pull-up rail (pass X).
  • Force the line HIGH via pull-up and measure Ileak (pass X), then compare across boards and after cleaning.
  • Compare rise-time with and without attached fixtures/cables to rule out “added C” vs true leakage.
• Design pitfall: relying on “looks clean on near-end TP” while the far-end node is the true worst case.

• Electrical picture: clamp structures can shift leakage after stress; the bus becomes more sensitive to noise and thresholds.
• Typical symptoms: intermittent failures begin only after handling/ESD events; far-end rise-time worsens; idle VHIGH droops under temperature/humidity.
• Do-not-skip verification: after ESD/handling events, re-measure Ileak, tr, and VHIGH at the far-end node (pass X each).
• Design pitfall: validating only logic-level compliance at one node and missing “margin collapse” over time.

Keep the library symptom-driven: measure at the far-end worst node, confirm rail states, then converge to leakage/partial short/clamp drift rather than chasing protocol ghosts.

Convert the open-drain model into acceptance gates. Every checklist item must be auditable and linked to a measurable pass criterion (X placeholders).

• Resistor window documented: define Rmin/Rmax from DC+AC constraints and tolerance; pass: Req stays within X…X across corners.
• Parallel pull-up audit: list all pull-up footprints (modules/options); pass: worst-case Req ≥ X and ≤ X.
• Rail ownership defined: pull-up owner rail is explicit for each bus segment; pass: no backfeed raising an OFF rail above X.
• Power-off behavior checked: drop-out/brown-out sequence set; pass: no stuck-low longer than X.
• Edge-control knobs reserved: Rs pads and controlled DNP options exist; pass: population changes require tr/VOL gates X.
• Test visibility: near-end and far-end TP reserved; pass: far-end TP accessible in fixture X.
• Return integrity: SDA/SCL avoids ground split/slot crossings; pass: defined return bridge if crossing is unavoidable (X).
• Worst-node definition: identify the highest-C / noisiest node; pass: acceptance measurements use that node by default.

• Measure at the worst node: far-end TP first, not near-end; pass: tr ≤ X, VOL ≤ X, VHIGH ≥ X.
• Probe discipline: verify probe loading and bandwidth/averaging settings; pass: tr changes ≤ X when probe/setup changes.
• Corner sweep: voltage and temperature corners; pass: tr/VOL stay within X across corners.
• Option sweep: populate modules/options that add pull-ups/capacitance; pass: Req and tr do not cross gate X.
• Sequencing/brown-out sweep: multiple power-down orders; pass: no stuck-low > X, no OFF-rail backfeed > X.
• Post-handling re-check: after ESD/plug cycles, re-test Ileak and tr; pass: ΔIleak ≤ X, Δtr ≤ X.
• Noise exposure check: verify ringing and threshold crossings at worst node; pass: no multi-crossing within X time.
• Golden signature captured: record baseline tr/VOL/Ileak for production comparison; pass: baseline stored with board ID and environment.

A checklist is only useful when each item is measurable. Treat every gate as a “no-excuse” stop: if the measurement cannot be made at the worst node, the design is not ready to ship.

1) Pull-up components: single resistor vs resistor network

• Single resistor (simple + flexible): easiest to tune per line; preferred when each line needs a different R window.
• Resistor network / array (layout control + BOM efficiency): reduces “pull-ups scattered everywhere”; helps keep a single effective pull-up owner.
• Key checks: tolerance/TC, power per element (low duty vs stuck-low), and whether multiple boards accidentally add parallel pull-ups.

2) Open-drain line drivers: when “the source” is not truly open-drain

• Use-case: converting push-pull GPIO into open-drain for wired-OR alert lines.
• Key checks: guaranteed sink current (IOL), VOL at that current, and partial-power-down behavior (avoid back-powering through I/O).

3) Level translation: keep open-drain semantics intact

• Goal: translate voltage domains without introducing direction-control failure modes.
• Key checks: power-off I/O state, internal pull-ups (if any), and how translation interacts with the effective pull-up window.

4) Bus buffering / segmentation: when Cbus breaks the pull-up window

• Trigger conditions: required rise-time cannot be met without making sink current / VOL unacceptable, or when a single net accumulates too much capacitance.
• Placement logic: buffer splits the bus so each side has its own pull-up and its own R window; the “home rail” becomes explicit per segment.
• Avoid turning this into a new chapter: detailed buffer topology and corner rules belong to the dedicated Buffers/Isolators/Switches page; this section only defines the decision boundary.

5) Isolation strategy: treat each isolated side as its own pull-up domain

• Rule of thumb: isolated SDA/SCL are not “one net” anymore; each side needs its own pull-up rail and its own R window.
• Key checks: sink current capability per side, propagation delay vs timing margin, and hot-swap / power sequencing behavior.

6) Port protection: leakage and capacitance directly reshape the pull-up window

• Why it belongs here: ESD devices add capacitance (slower rise) and leakage (lower VOH), both of which change the safe R window.
• Keep it disciplined: detailed IEC waveforms and placement belong to the protection page; this section only lists the pull-up-relevant knobs.

Output of this flow is not “one resistor value”, but a validated window plus a clear boundary: if the window collapses, the design needs segmentation / translation / isolation rather than forcing an unsafe pull-up.

Practical rule: treat “pull-up rail ownership” as a first-class spec. If a line crosses rails, power domains, or isolation, the pull-up must be re-owned at the boundary (translator/buffer/isolator), not left implicit.