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Isolation Strategy: Delay Budget & CMTI for I2C/SPI/UART

Isolation Strategy: Delay Budget & CMTI for I2C/SPI/UART

← Back to: I²C / SPI / UART — Serial Peripheral Buses

Isolation strategy is about controlling where energy and common-mode currents can flow, so I²C/SPI/UART remain correct under ground shift, dv/dt events, and safety constraints. A robust design starts with delay/CMTI/power/layout budgets, then proves them with timing-vs-CMTI bring-up tests and production pass criteria.

H2-1 · Definition & When to Isolate

Isolation is a system decision: it blocks energy/common-mode paths, but it also consumes timing margin and power budget.

What “isolation” means here

  • Functional isolation: improves robustness against ground shift and high dv/dt common-mode events. Acceptance focuses on error rate, lock-up recovery, timing margin.
  • Safety isolation: required by regulations or human-touch risk. Acceptance focuses on working voltage, creepage/clearance, insulation test (HiPot), certified components.
  • Not a universal EMI fix: isolation can reduce certain coupling paths, but it can also introduce new injection through barrier capacitance and isolated power noise. (For EMI tactics, see EMC & Edge Control.)

30-second self-check (YES/NO)

Q1 · Ground shift risk?

Different ground references across boards/cables, or large load current steps causing fast ground bounce. YES → functional isolation is strongly favored.

Q2 · High dv/dt common-mode events nearby?

Motor/half-bridge switching, relay/EFT bursts, hot-plug transients, long-cable common-mode steps. YES → CMTI and injection paths become primary design constraints.

Q3 · Safety / regulation / human-touch requirement?

Any requirement for certified insulation, working voltage rating, or mandatory isolation testing. YES → safety isolation; layout and certification drive the design.

If all answers are NO, prioritize Port Protection, Level Translation, and Topology Planning before adding isolation.

SVG-1 · “Isolate or not” decision gate

Isolate or not decision gate Three inputs (ground shift, dv/dt common-mode, safety requirement) feed a decision gate that outputs safety isolation, functional isolation, or no isolation. Ground shift static / dynamic ΔGND High dv/dt common-mode events Safety req. regulation / touch risk Decision isolation class Safety isolation certification + layout Functional isolation delay + CMTI driven No isolation use protection / EMC Output class determines acceptance: safety tests vs timing/CMTI margin closure.

Reading tip: a “YES” on Safety immediately defines the isolation class. Otherwise, prioritize closure on delay budget and CMTI margin.

H2-2 · Threat Model for Serial Buses

Model the problem as a path: Source → Coupling → Barrier → Receiver decision. Most field failures collapse into one of two mechanisms:

  • Timing window collapse: propagation delay/skew steals setup/hold or shifts sampling points.
  • Common-mode injection upset: high dv/dt drives barrier capacitance currents, moving thresholds or rails during sampling.

Threat → symptom signature → first probe

Ground shift (static / dynamic)

Symptoms: intermittent NAKs, stuck-bus states, framing/parity bursts, sporadic bit slips during load steps.

First probe: measure ΔGND between domains during worst-case load transition; correlate with protocol errors on a logic analyzer.

High dv/dt common-mode events (EFT / switching / hot-plug)

Symptoms: error bursts tightly time-aligned to switching edges; “clean” periods between events; occasional lock-up after a surge-like transient.

First probe: observe common-mode step and isolated-rail disturbance; check whether lowering speed changes failure probability (timing vs injection split).

EFT/Surge triggers state-machine lock-up

Symptoms: bus becomes “stuck” until power-cycle; recoverable only with reset sequencing; repeated retries no longer help.

First probe: verify fail-safe output state of isolator under transient; log reset/timeout behavior and confirm recovery path closes without manual intervention.

Routing note: timing-driven signatures should lead to Delay Budget & Timing Windows; injection-driven signatures should lead to CMTI, dv/dt & Common-Mode Injection; rail droops should lead to Isolated Power Strategy.

SVG-2 · Noise path model (Source → Coupling → Barrier → Decision)

Noise path model for isolated serial buses A block diagram showing disturbance source, coupling path, isolation barrier, and receiver decision with timing margin and threshold margin callouts. Source ground shift EFT / surge high dv/dt Coupling parasitic C return path shield bonding Isolation barrier prop delay / skew CMTI margin barrier capacitance common-mode injection Receiver decision (protocol sampling) Timing margin setup/hold window Threshold rail / VIH-VIL Two failure modes 1) timing collapse 2) injection upset separate by correlation

Debug shortcut: if lowering speed greatly improves stability, suspect timing window collapse. If failures align to switching edges or EFT bursts, suspect common-mode injection upset.

H2-3 · Isolation Technologies & Key Parameters Map

Datasheet fields must map to system failure modes: timing window collapse, common-mode injection upset, and power/reset lock-up behavior.

Technology families (concept-level)

Capacitive digital isolation

  • Primary risk lens: dv/dt injection paths and rail/threshold upset under fast common-mode steps.
  • Selection focus: CMTI margin, default/fail-safe state, channel-to-channel skew closure.

Magnetic (inductive) isolation

  • Primary risk lens: timing and channel matching at high throughput; robust behavior during transients.
  • Selection focus: propagation delay/skew, data-rate headroom, defined output state during brown-out.

Optical isolation (opto)

  • Primary risk lens: long-term behavior and interface constraints; ensure output defaults are compatible with bus idle state.
  • Selection focus: speed/latency envelope, fail-safe output, and operating conditions over lifetime.

Note: data-rate capability alone does not guarantee protocol margin. Always close timing and injection margins at system level.

Key fields to read (and what each one actually controls)

CMTI

Controls susceptibility to fast common-mode steps; it does not eliminate injection through isolated power or poor return-path/layout.

Propagation delay (tPD)

Sets absolute latency and impacts setup/hold closure; it must be budgeted end-to-end with cables and receivers.

Skew / channel matching

Controls relative alignment across SCLK/DATA/CS (SPI) and multi-signal timing; skew is often the real limiter at high speed.

Data rate / pulse width limits

Describes internal encoding/edge handling capability; it does not guarantee protocol timing margin without skew closure.

Working voltage / insulation rating

Defines safety envelope and test requirements; it drives creepage/clearance and certified component needs.

Surge / ESD robustness

Ensures the barrier interface survives system-level transients; board-level protection and grounding still set the final pass/fail.

Fail-safe state / default output

Determines what the receiver sees during brown-out, reset, or input floating; wrong defaults can lock up I²C/SPI/UART stacks.

Hard trade-offs (the “triangle”)

  • High CMTI typically pushes designs toward stronger transient immunity requirements.
  • Low delay + low skew protects timing windows at high throughput.
  • Low power is optimized only after timing and transient margins are closed.

Selection order: lock the threat model (dv/dt and safety) → close timing window (delay/skew) → optimize power.

SVG-3 · Priority matrix (Scenario × Datasheet field)

Isolation parameter priority matrix A matrix mapping scenarios to key datasheet parameters with priority markers P0, P1, and P2. Legend: P0 must P1 strong P2 optimize Field ↓ / Scenario → Motor dv/dt High V Safety Long cable HS SPI CMTI prop delay skew / match working V surge / ESD fail-safe

Use this matrix to set “P0 must” gates early. Once P0 fields are satisfied, close timing margin (delay/skew) before optimizing power.

H2-4 · Delay Budget & Timing Windows (I²C/SPI/UART)

The most common isolation failure is not “wrong protocol” but timing margin loss: propagation delay and skew eat the sampling window.

Where delay and skew show up

  • Setup/hold closure: extra tPD shifts data relative to the sampling edge; skew misaligns multi-signal timing (SCLK/DATA/CS).
  • Duty/edge placement sensitivity: clock duty distortion and asymmetric rise/fall delays can move the effective capture point.
  • Receiver decision window: UART oversampling relies on stable edge timing; noisy or delayed edges increase framing/parity bursts.

Bus-specific timing pressure points (principles)

I²C

  • Isolation adds edge/recognition delay, pushing timeout and recovery policies closer to the limit.
  • Clock stretching and master timeout rules must be re-reviewed after isolation.
  • Detailed policies belong to Clock Stretching.

SPI

  • Skew between SCLK and DATA is the usual limiter at high speed; return-path (MISO) is often the worst case.
  • CS-to-CLK and CLK-to-DATA must include isolator + interconnect latency and worst-case skew.
  • SI/termination details belong to Long-Trace SI.

UART

  • Oversampling assumes stable edge timing; added delay/skew and edge degradation can increase framing/parity bursts.
  • Baud error budget must include clock drift plus any timing distortion that shifts the effective sampling center.
  • Calibration details belong to Baud Rate & Error Budget.

Unified delay budget template (record and close margins)

Segment the link (one direction)

MCU/host → Isolator A → Cable/connector/trace → Isolator B → Device

Record delay terms (per segment)

  • Propagation delay (tPD), min/typ/max
  • Skew / channel mismatch (worst-case)
  • Interconnect latency (trace/cable)
  • Receiver constraints (setup/hold or sampling center)

Close worst-case margin (action ladder)

  • Reduce rate / widen sampling window (lowest cost)
  • Change mode/phase (SPI) or adjust timeout policy (I²C)
  • Select lower-skew / lower-delay isolation channels
  • Shorten interconnect or re-partition where isolation sits
  • Add buffering/re-timing (highest cost)

SVG-4 · Timing budget bar (segment delays + remaining margin)

Timing budget bar for isolated serial links A stacked timing budget bar showing host, isolator A, interconnect, isolator B, device, skew penalty, and remaining margin. Total sampling window = segment delays + skew penalty + remaining margin HOST ISO-A CABLE/PCB ISO-B DEVICE MARGIN SKEW Worst-case stacking: use max tPD + worst skew + longest interconnect; margin must remain positive under temperature/voltage corners. if margin is small: reduce rate, adjust phase/timeout, choose lower skew, shorten link, or re-time.

This bar is a bookkeeping tool: it prevents “data-rate only” selection mistakes and forces closure on delay/skew margins before field failures appear.

H2-5 · CMTI, dv/dt & Common-Mode Injection

CMTI must be treated as a system margin: measurable, repeatable, and tied to pass/fail criteria (not a standalone datasheet number).

dv/dt scenarios that typically dominate isolation behavior

Power switching dv/dt

Motor half-bridge, inverter nodes, fast switching edges that create repeating common-mode steps.

Hot-plug / power-path transients

Cable insert/remove, supply switching, contact bounce that produces sharp, irregular dv/dt events.

EFT-style burst disturbances

Repetitive fast edges that can trigger intermittent upset, then escalate into lock-up if recovery is weak.

Long-cable common-mode steps

Harness and shield reference changes that create sudden common-mode shifts at the far end.

Minimal model: dv/dt becomes injection current through the barrier

Iinj = Ciso × (dv/dt)

The current itself is unavoidable; the failure mode is set by the return path: ground bounce (ΔGND), receiver threshold upset, or isolated-rail disturbance.

What it can look like at protocol level

  • SPI: bursts of CRC errors or “bit-slip” clustered around switching events.
  • I²C: sporadic NAKs or a bus that becomes stuck low after a transient.
  • UART: framing/parity bursts correlated with relay/motor/hot-plug moments.

Fast discriminator (timing vs injection)

  • Injection-likely: errors align with dv/dt events; grounding/shield changes shift the failure rate.
  • Timing-likely: rate reduction or phase/mode adjustment improves stability without strong event correlation.
  • Lock-up-likely: a transient leaves the system stuck until reset → check rails and fail-safe defaults.

CMTI acceptance approach (stimulus → observability → criteria)

Stimulus (representative dv/dt events)

Use system-representative switching/hot-plug/burst events and correlate them to communication health. Avoid “datasheet-only” assumptions.

Observability (minimum probes)

  • dv/dt trigger point or common-mode reference marker.
  • ΔGND across the barrier and/or receiver reference movement.
  • Isolated rail (VISO) ripple/dips during events.
  • Protocol counters: CRC/NAK/framing, retries, watchdog recoveries.

Pass criteria (system-level)

  • Bit errors / frame drops ≤ X per test window (define X).
  • Lock-up events = 0 (no manual power-cycle).
  • If errors occur, automatic recovery within T seconds (define T).

Related: EMI tactics belong to EMC & Edge Control. Protection component details belong to Port Protection.

SVG-5 · dv/dt → Iinj → ΔGND / threshold upset (simplified barrier model)

Common-mode injection model across an isolation barrier A block diagram showing dv/dt source, barrier capacitance, injection current, ground bounce, and receiver threshold margin shift with probe points. dv/dt source Half-bridge Hot-plug Burst noise Isolation barrier Primary side Secondary side Ciso Iinj Receiver Decision Threshold margin ΔGND / VISO dv/dt Probe A dv/dt marker Probe B ΔGND / VISO / RX Key idea: current return path defines whether the outcome is a bit upset, burst errors, or a lock-up.

If protocol errors cluster around dv/dt moments, prioritize injection path, isolated-rail stability, and receiver threshold margin before tuning protocol settings.

H2-6 · Reference & Pull-ups Across the Barrier (Open-Drain & Biasing)

For I²C/open-drain isolation, the pull-up and reference rules must be closed first; wrong defaults can lock the bus before firmware runs.

Golden rules (open-drain across a barrier)

Rule 1: pull-ups are per-domain

SDA/SCL must be pulled up to VDD1 on the primary side and to VDD2 on the secondary side. Do not “share” pull-ups across the barrier.

Rule 2: default output must not force LOW

During reset/brown-out, the isolation channel should not drive SDA/SCL low unless explicitly designed for a safe state. I²C idle requires a released (high) bus.

Rule 3: prevent ghost power

When one side is unpowered, signals must not back-feed through I/O structures. Use clear power-off behavior and controlled enable/reset sequencing.

Power-up / reset behavior (what to verify)

  • Output mode: High-Z vs driven; ensure bus is released at idle.
  • Enable/reset sequencing: apply EN/RESET so the bus is not forced into a stuck state while rails ramp.
  • Brown-out recovery: after a transient, the bus must return to idle without manual power-cycle.

Rise-time sizing and pull-up value calculation belong to Open-Drain & Pull-Up Network. Clock stretching policies belong to Clock Stretching.

I²C isolation checklist (power, pull-ups, reset, bus release)

1) Rails & references

  • VDD1 and VDD2 are defined and decoupled locally.
  • Barrier references are not unintentionally bridged by shields or wiring.

2) Pull-ups

  • SCL/SDA pulled up to VDD1 on primary, VDD2 on secondary.
  • No cross-domain pull-up paths or “shared” rails through signals.

3) Reset/enable & defaults

  • Default state does not force SDA/SCL low during reset.
  • EN/RESET line is available to coordinate power-up and recovery.

4) Bus release & recovery

  • After brown-out, the bus returns to idle without manual power-cycle.
  • A defined recovery path exists (watchdog/reset/bus-clear policy).

SVG-6 · I²C isolation topology (pull-ups per side + EN/RESET control)

Correct I2C isolation topology with pull-ups on both sides A block diagram showing primary and secondary power domains, pull-up resistors to VDD1 and VDD2, an I2C isolator, and an enable/reset line. Primary domain (VDD1) Secondary domain (VDD2) VDD1 VDD2 MCU / Master I²C I²C slaves DEV A DEV B I²C Isolator SCL / SDA High-Z on reset SCL SDA SCL SDA Pull-ups to VDD1 Rpu Rpu Pull-ups to VDD2 Rpu Rpu EN / RESET control Barrier Rule: pull-ups are per-domain; defaults must not hold SDA/SCL low; control EN/RESET to avoid stuck-low after brown-out.

This topology prevents cross-domain pull-up mistakes and reduces bus lock-up risk by enforcing defined power and default-state behavior.

H2-7 · Isolated Power Strategy (Powering the Far Side)

Before isolating signals, isolate power and reference behavior: UVLO/POR/soft-start and sequencing decide whether the far side boots into a valid bus idle state.

When an isolated DC/DC is effectively required

P0: Safety isolation / compliance boundary

Safety requirements demand a certified isolation boundary for both signal and power, with auditable separation and predictable behavior under faults.

P0: Large or uncontrolled ground potential differences

If the far side reference can shift unpredictably, a controlled isolated rail prevents “half-powered” states and reduces lock-up risk during transients.

P0: No reliable far-side supply

When the far side cannot guarantee stable power, isolating the DC rail enables a defined POR/UVLO policy and consistent bus idle behavior.

Far-side powering modes (compare by behavior, not by topology)

Mode A — Far-side self-supply

  • Best at: higher power budget, independence from the primary rail.
  • Risk: brown-outs create undefined defaults and “half-awake” state machines.
  • Must define: EN/RESET coordination and bus-release policy during ramps.

Mode B — Isolated DC/DC powers far side

  • Best at: safety boundaries, large ground shifts, consistent POR/UVLO behavior.
  • Risk: layout partitioning and dv/dt coupling must be controlled (see H2-8).
  • Must define: soft-start, UVLO threshold, and enable sequencing to guarantee a clean bus idle.

Mode C — Harvest / auxiliary power

  • Best at: very low-power nodes with limited wiring and long maintenance intervals.
  • Risk: frequent UVLO/POR cycling → highest probability of stuck states without strict defaults.
  • Must define: aggressive POR/UVLO gating and recovery logic for every power cycle.

Control signals that determine bus correctness during ramps

UVLO (Under-Voltage Lockout)

Prevents “half-valid logic” states. Without a strict UVLO boundary, I/O can leak, pull lines, or mis-decode edges during brown-out events.

POR (Power-On Reset)

Defines when outputs become valid and what default state is presented before firmware is ready. This is a primary determinant of “bus idle correctness.”

Soft-start & sequencing

Ramp slope and ordering decide how long thresholds remain in the “ambiguous region.” Use EN/RESET to keep bus channels released until rails are stable.

Related: open-drain pull-up placement belongs to Reference & Pull-ups Across the Barrier. Timing-window failures belong to Delay Budget & Timing Windows.

Power strategy chooser (mobile-safe scorecards)

Self-supply (Mode A)

Power: P0 Distance: P1 Safety: P2 Maintain: P1 Robustness: P1

Isolated DC/DC (Mode B)

Power: P1 Distance: P0 Safety: P0 Maintain: P1 Robustness: P0

Harvest / auxiliary (Mode C)

Power: P2 Distance: P0 Safety: P1 Maintain: P0 Robustness: P2

SVG-7 · Power domains: Primary → Isolated DC/DC → Far-side rails → Bus devices

Power domain block diagram for isolated power strategy A diagram showing primary supply rails feeding an isolated DC/DC converter, generating far-side isolated rails for bus devices with EN, POR and UVLO control lines. Primary domain VIN / AC-DC 5V / 3V3 rails Control EN / POR / UVLO Isolated DC/DC Soft-start UVLO / POR Barrier Far side VISO rails Bus devices I²C / SPI / UART Defaults High-Z / safe idle Power VISO EN POR UVLO Aim: a predictable far-side rail behavior so bus lines idle correctly across POR/UVLO and transients.

The far-side rail policy (UVLO/POR/soft-start + EN sequencing) should be validated together with bus recovery behavior under brown-out and dv/dt events.

H2-8 · Safety & Layout: Creepage/Clearance, Partitioning, Grounding

Isolation must be expressed as layout partitioning: separation distances, a controlled keepout moat, and disciplined return paths — otherwise paper compliance does not translate to hardware.

Creepage vs clearance (concepts that set real-world margin)

Clearance (air distance)

The shortest through-air path. Mechanical constraints, placement, and unexpected metal parts can shrink effective clearance.

Creepage (surface distance)

The path along the PCB surface. Contamination, humidity, residues, and “bridges” can reduce effective creepage and long-term reliability.

Why slots / keepouts matter

A deliberate isolation moat and slots increase surface path length and force routing discipline. Manufacturing and cleanliness must be treated as part of the design.

Related: deeper return-path and ground strategy belongs to Clock & Grounding.

Layout Do / Don’t (hard checks, ≤10)

Do

  • Plan the isolation moat/keepout early and route around it, not across it.
  • Separate high dv/dt power loops from the barrier and sensitive digital region.
  • Place local decoupling on each side of the barrier close to its rail consumers.
  • Keep cross-barrier signal routing short and domain-contained with clean return paths.
  • Reserve test points for ΔGND, VISO and key bus lines to support acceptance testing.

Don’t

  • Do not allow copper pours, vias, test pads, or stitching to bridge the moat.
  • Do not place high dv/dt nodes next to the barrier boundary or keepout edge.
  • Do not let chassis/shield/fastener hardware unintentionally connect both references.
  • Do not treat creepage as “only geometry”: cleanliness, coating and residues change the margin.
  • Do not squeeze isolation routing through ambiguous mixed zones; keep domains explicit.

SVG-8 · PCB partitioning (isolation moat + keepout + no-cross routing rule)

PCB isolation partitioning with keepout moat A top-view PCB diagram showing a high dv/dt power region, an isolation moat keepout area, a digital bus region, and examples of allowed routing and forbidden crossing. Power dv/dt zone Half-bridge Driver High current loop Switch node Isolation moat Keepout Digital / bus zone MCU Isolator Bus devices Route around No-cross Keepout moat: no copper, no vias, no pads, no stitching across the barrier.

Treat any cross-moat copper or hardware path as a candidate isolation violation: verify separation, return paths, and mechanical connections early.

H2-9 · Architecture Patterns by Bus (I²C vs SPI vs UART)

Stable isolation architectures are bus-specific: I²C needs fault-domain segmentation and deterministic bus release; SPI needs skew control across clock/data/CS; UART needs a clean layering boundary between logic and PHY.

I²C pattern: segment the fault domain, then place recovery at the boundary

Recommended

  • Use segmentation (buffer/switch/mux) to limit capacitance and isolate a stuck device.
  • Define bus release with EN/RESET near the isolator boundary (High-Z default preferred).
  • Keep pull-ups domain-local on both sides of the barrier (do not “share” pull-ups across domains).

Anti-pattern

  • Single long bus across the barrier with no segmentation and undefined defaults.
  • Any brown-out that forces SDA/SCL low can create stuck-low conditions that persist until manual reset.

Deep dive: pull-up placement and defaults belong to Reference & Pull-ups Across the Barrier.

SPI pattern: control skew across SCLK / data / CS (especially at high throughput)

Recommended

  • Keep clock distribution explicit: SCLK and CS should be timed as a set, not as unrelated signals.
  • Budget channel-to-channel skew through isolator + interconnect + receiver sampling.
  • Treat MISO return delay as a first-class item in the timing budget (round-trip matters).

Anti-pattern

  • Fan out SCLK after isolation across long traces/cables to multiple slaves.
  • Route CS through a different path than SCLK, breaking CS-to-CLK relationships → intermittent CRC/bit-slip.

Deep dive: SI and termination belong to Long-Trace SI. Protocol modes belong to SPI CPOL/CPHA Modes.

UART pattern: isolate the logic, place the PHY where the cable exists (clear layering boundary)

Recommended

  • MCU UART (logic) → UART isolator → far-side RS-232/RS-485 transceiver → cable.
  • Define power defaults so the isolator does not drive undefined levels during POR/UVLO.
  • Keep protection and cable EMC closest to the connector (handled in sibling pages).

Anti-pattern

  • Place the transceiver on the wrong side of the barrier, so cable common-mode reaches the logic reference.
  • Allow back-powering during partial power states → framing/parity bursts and persistent lock-ups.

Deep dive: PHY selection and long-cable behavior belong to UART Voltage Levels & PHY and bus protection belongs to Port Protection.

SVG-9 · Topology patterns (Recommended vs Anti-pattern) for I²C / SPI / UART

Architecture patterns by bus: I2C, SPI, UART A three-panel diagram showing recommended and anti-pattern topologies for I2C, SPI, and UART across an isolation barrier. I²C SPI UART Recommended MCU BUF ISO RPU DEV Anti-pattern MCU DEV No recovery Recommended MCU ISO CS DEV SCLK Anti-pattern MCU DEV Skew uncontrolled Recommended MCU ISO PHY Cable Anti-pattern MCU PHY Cable Layer boundary broken Recommended: defined defaults + recovery point + budgetable timing. Anti-pattern: uncontrolled skew / no recovery / broken layering.

Use the recommended topology as the baseline. If a workaround adds ambiguity to defaults, recovery, or skew, treat it as an anti-pattern until proven by acceptance testing.

H2-10 · Bring-up & Debug: Prove Timing vs Prove CMTI

A fast isolation bring-up relies on attribution: first prove whether failures track timing windows (delay/skew) or common-mode injection (dv/dt/CMTI). The workflow below is designed to converge quickly.

10-step debug flow (each step produces a branching conclusion)

1) Capture a baseline error signature

Record what fails (CRC/NAK/framing/lock-up), frequency, and whether events correlate with switching, hot-plug, or load changes.

2) Reduce rate (one step)

If errors drop sharply, a timing window is likely being consumed by delay/skew. If unchanged, prioritize common-mode and rail paths.

3) Add idle spacing / guard time

If stability improves, setup/hold, CS-to-CLK, or receiver settle time is marginal. Treat this as a timing-dominant signature.

4) Adjust sampling alignment (where applicable)

SPI phase/edge alignment changes that fix the issue indicate skew placement inside the sampling window. Keep changes deterministic and logged.

5) Relax timeouts (only to classify)

If lock-ups reduce but corruption persists, suspect power state/rail upset rather than pure timing. Restore production-safe policies after classification.

6) Minimize the link (shortest path)

Compare a minimal path against the full system. If only the full build fails, the extra segment contributes delay/skew or common-mode coupling.

7) Observe VISO and ΔGND during errors

If errors coincide with rail dips or ground bounce, treat the failure as injection/rail-dominant. This is a strong CMTI-path indicator.

8) Change shielding/ground reference (single variable)

If the failure rate changes materially, common-mode injection and return paths dominate. Document the exact mechanical/grounding change.

9) Correlate with dv/dt events (system or lab stimulus)

Strong time alignment between errors and switching/hot-plug pulses points to CMTI/injection. Use compliant equipment and safe procedures.

10) Close with a fix ladder

Timing path: relocate/budget channels, change sampling policy, reduce skew. CMTI path: improve partitioning, rail robustness, and return-path discipline.

SVG-10 · Debug flowchart (Timing path vs CMTI path)

Debug flowchart for isolated serial buses A flowchart that branches between timing-window issues and common-mode injection issues using a sequence of diagnostic steps. Baseline signature Rate ↓ fixes? Timing path CMTI / injection path YES NO Add idle / guard time Adjust phase / sampling Budget delay & skew Timing fix ladder relocate / reduce skew / re-sample Probe VISO / ΔGND Change shield/ground Event correlation (dv/dt) CMTI fix ladder partition / rails / return paths Principle: classify first (timing vs injection), then apply the correct fix ladder with measurable pass criteria.

Avoid mixing fixes before classification. Timing changes that improve stability usually indicate window margin issues; grounding/shield changes that improve stability indicate common-mode coupling dominance.

Engineering Checklist (Design → Bring-up → Production)

This gate-based checklist turns isolation strategy into evidence-driven acceptance: budgets are signed at design time, failures are attributed fast during bring-up, and production quality is closed with measurable statistics.

Design Gate · Budgets & constraints are signed
1) Delay/Skew budget is explicit (worst-case)
  • Why: Protocol timing windows shrink fast once isolator prop delay + channel skew + round-trip are added.
  • How: Record worst-case path segments (MCU → isolator → interconnect → isolator → device) and remaining margin.
  • Pass criteria: Margin ≥ X% (or ≥ X ns) at target rate/mode.
  • Evidence: Budget sheet + mode/rate assumptions + timing diagram snapshot.
2) CMTI / dv/dt risk level and acceptance plan exist
  • Why: Common-mode injection can look like CRC bursts/NAKs while the root cause is threshold upset.
  • How: Define the system event set (switching/hot-plug/EFT) and the observation points (logic errors + VISO + ΔGND).
  • Pass criteria: Lock-up = 0 in N events; CRC/NAK ≤ X ppm.
  • Evidence: Error counters + event timestamps + correlation plot (event vs error burst).
3) Power/reset/default-state behavior is defined across the barrier
  • Why: Brown-out + half-powered domains are a top cause of stuck buses and “ghost powered” receivers.
  • How: Specify UVLO/POR order, isolator enable/reset wiring, and bus idle ownership (High-Z vs drive).
  • Pass criteria: After brown-out/hot-plug: no stuck-low; auto-recovery ≤ T.
  • Evidence: Power sequencing capture + bus-idle verification + reset recovery log.
4) Safety/layout constraints are implementable on PCB
  • Why: Creepage/clearance and partitioning determine real isolation immunity, not schematic symbols.
  • How: Lock keepouts, isolation gap, and “no-cross” zones; ensure return paths do not sneak across the barrier.
  • Pass criteria: Meets project standard requirement (placeholder): STD = X.
  • Evidence: PCB review checklist + DRC screenshots + isolation gap measurement notes.
5) Observability & recovery hooks are present
  • Why: Isolation failures need fast attribution (timing vs CMTI vs rail upset).
  • How: Provide test pads (VISO, ΔGND, key lines), counter logs (CRC/retry/NAK), and controlled reset/EN pins.
  • Pass criteria: Probes reachable; firmware logs include fields: CRC, retry, lock-up count.
  • Evidence: Test point map + example log lines from bench bring-up.
Bring-up Gate · Prove timing first, then prove CMTI
1) Minimal link baseline (short path)
  • Observe: protocol correctness and idle state stability.
  • Pass criteria: 0 errors over N frames.
2) Rate/phase/timeout sweep (timing attribution)
  • Observe: error sensitivity to speed, sampling edge, and inter-frame spacing.
  • Pass criteria: stable at target with margin ≥ X%.
3) Full path (long interconnect / far-side)
  • Observe: fault domain containment and recovery behavior.
  • Pass criteria: recovery ≤ T; no stuck bus after resets.
4) Single-variable common-mode changes (CMTI attribution)
  • Observe: error correlation with shielding/ground reference routing and system switching events.
  • Pass criteria: error delta within X across allowed configurations.
5) Evidence pack is captured
  • Include: logic error logs (CRC/NAK/framing), timestamps, and rail snapshots (VISO, ΔGND) aligned to events.
  • Pass criteria: attribution is unambiguous: Timing path or CMTI path.
Production Gate · Isolation quality is statistical, not anecdotal
1) Dielectric withstand / HiPot per build spec
  • Pass criteria: per project spec: V = X, t = Y.
  • Evidence: station log + lot traceability.
2) Error statistics (CRC/retry/NAK/framing)
  • Pass criteria: CRC ≤ X ppm; retry ≤ Y%.
  • Evidence: counter readout + test duration.
3) Lock-up rate and auto-recovery time
  • Pass criteria: lock-up = 0 in N cycles; recovery ≤ T.
  • Evidence: watchdog/reset counters + recovery log.
4) Power boundary audit (UVLO/POR consistency)
  • Pass criteria: POR/UVLO windows within X across lots.
  • Evidence: sampled rail measurements + lot-to-lot summary.
5) Build partition checks (isolation gap, cleanliness, no-cross)
  • Pass criteria: meets build rules (slot/keepout/creepage) with 0 violations.
  • Evidence: inspection records + photo evidence (if applicable).
SVG-11 · Gate flow (Design → Bring-up → Production)
Isolation gates flow bar with checkpoints Three-stage gate bar with checklist checkpoints for design, bring-up, and production. Design Gate Bring-up Gate Production Gate Checkpoints Delay/Skew budget CMTI plan Rails/POR/default Safety/layout rules Checkpoints Baseline (short link) Rate/phase sweep Full path (long) CMTI attribution Checkpoints HiPot / withstand CRC/retry stats Lock-up = 0 goal Build partition audit

Applications & IC Selection Logic (Isolation-focused)

Selection is driven by constraints, not brand: choose channel directionality first, then timing margin, then common-mode immunity, then power/default-state behavior, and finally safety certifications that the PCB can actually build.

Scenario buckets → parameter priorities
A) Motor drive proximity (high dv/dt)
  • Primary risk: common-mode injection and rail upset.
  • Priority: CMTI → default/fail-safe behavior → isolated power robustness → skew.
  • Typical class: high-immunity digital isolator or integrated-power isolator for space-limited designs.
B) Long reach / remote I/O (cable + maintenance)
  • Primary risk: remote brown-outs + stuck states + slow recovery.
  • Priority: default state on power loss → EN/RESET hooks → working voltage → CMTI.
  • Typical class: isolator with clearly documented power-off behavior and controllable enable.
C) Chassis / cabinet ground shift
  • Primary risk: unintended return paths across the barrier.
  • Priority: insulation rating (working voltage) → package creepage feasibility → CMTI → delay.
  • Typical class: reinforced/basic-rated isolator that the PCB partition can truly implement.
D) Safety isolation (industrial/medical compliance)
  • Primary risk: certification and production consistency.
  • Priority: approvals/standards → creepage/clearance → HiPot plan → default state.
  • Typical class: reinforced isolators / certified modules with a production gate plan.
Selection order (hard filter chain)
  1. Channels & direction: open-drain/bidirectional (I²C) vs fixed directions (SPI/UART).
  2. Rate: target clock/baud with margin.
  3. Delay & skew: ensure protocol windows survive worst-case propagation and mismatch.
  4. CMTI: match the dv/dt environment; require measurable immunity and acceptance criteria.
  5. Isolated power: choose far-side supply method; confirm UVLO/POR behavior aligns with bus recovery.
  6. Default/fail-safe: define power-off behavior to avoid stuck states and back-powering paths.
  7. Certifications: final gate: isolation rating + approvals + PCB feasibility.
Minimal spec fields to capture (field names)
Channel count / Directionality
Bidirectional/open-drain compatibility vs fixed directions; include enable/reset pins.
Data rate + timing
Max data rate, propagation delay (max), channel-to-channel skew (max), jitter, pulse-width distortion.
CMTI (min) + immunity notes
Match the dv/dt environment; define system-level acceptance (CRC/lock-up) not just device numbers.
Isolation rating
Working voltage, UL/VDE claims, and package creepage suitability for the PCB partition.
Power/default-state behavior
Supply range, UVLO/POR behavior, power-off output state, fail-safe receiver behavior, and back-power prevention notes.
Example material numbers (by class, not a “product list”)

These examples anchor datasheet fields. Verify channel directions, insulation rating, package creepage, and ordering suffix for the project.

  • I²C bidirectional isolators (open-drain compatible): ADuM1250 / ADuM1251 (ADI) · ISO1540 / ISO1541 (TI)
  • Dedicated SPI isolator (CLK/MOSI/MISO/SS optimized timing): ADuM4150 (ADI)
  • General-purpose digital isolator (multi-channel control/CS/aux lines): ISO7741 (TI)
  • Digital isolator with integrated isolated power (space-limited designs): ISOW7741 (TI)
  • Integrated isolated DC/DC converter (isolated rail for far side): ADuM5020 (ADI)
  • Transformer driver for isolated supplies (external transformer + rect/reg): SN6505A (TI)
  • Isolated DC/DC module (quick isolated rail, small footprint): NXE1 series (Murata)
  • Isolated RS-485/RS-422 transceiver (layering for UART over field wiring): ISO3082 (TI) · ADM2587E (ADI, integrated isoPower)
SVG-12 · Selection flow (inputs → decision nodes → recommended class)
Isolation selection flow from constraints to device class Inputs feed a chain of decision nodes: channels/direction, rate, delay/skew, CMTI, power/default, certification; outputs are recommended isolator classes. Inputs Bus type I²C / SPI / UART Isolation goal Safety / Functional Environment dv/dt / shift / cable Power model local / iso / module Decision nodes Channels / Direction Rate (clock/baud) Delay / Skew budget CMTI vs dv/dt Power + Default state Certifications / creepage Recommended class I²C bidirectional ADuM1250 / ISO1540 SPI-optimized ADuM4150 Multi-channel control ISO7741 Integrated power ISOW7741 UART over field wiring ISO3082 / ADM2587E

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FAQs (Isolation Strategy)

Scope: these FAQs only close long-tail isolation debugging and acceptance. They do not expand into protection/EMC/level-translation details.

After isolation, I²C shows occasional NAK / bus hang — prove timing first or CMTI first?
Likely cause: Either timing margin collapse (delay/skew shrinks sampling window) or common-mode injection causing false edges / stuck states.
Quick check: First, reduce bus speed one step and increase timeout/idle spacing; if errors drop sharply, suspect timing. If errors correlate with switching/hot-plug events, suspect CMTI.
Fix: Timing path: tighten budget (lower speed, reduce skew, simplify segments) and ensure isolator I²C mode matches. CMTI path: improve partition/return path and stabilize isolated rails; ensure defined power-off state (bus release).
Pass criteria: Hang = 0 in N power/switching events; NAK ≤ X ppm at target speed; recovery ≤ T.
SPI is stable at low speed, but bit-slip appears at high speed — how to validate skew budget quickly?
Likely cause: Channel-to-channel skew (CLK vs data) + propagation delay pushes sampling beyond setup/hold, especially on MISO return path.
Quick check: Shift sampling edge/phase (CPHA or controller delay taps) and add extra inter-frame spacing; if one phase reliably works and another fails, skew/timing margin is the limiter.
Fix: Reduce SPI clock, constrain route length mismatch, prefer low-skew isolators, and re-balance CLK/MOSI/MISO topology (shortest CLK, controlled MISO return).
Pass criteria: Bit-slip = 0 over N frames at target fSCLK; timing margin ≥ X% worst-case.
UART drops frames only in the field — common-mode injection or power UVLO?
Likely cause: UVLO/POR rail upset causes receiver reset or metastable state; common-mode injection causes threshold upset that looks like framing/parity bursts.
Quick check: Correlate drop events with isolated-rail dips/reset counters. If drops align with switching/hot-plug but rails are stable, suspect common-mode injection.
Fix: UVLO path: improve isolated supply headroom/decoupling and POR sequencing; add brown-out recovery. CMTI path: tighten partition/return path and ensure shielding strategy does not create cross-domain return.
Pass criteria: Framing/parity errors ≤ X ppm during N field-equivalent events; UVLO trips = 0 (or within spec).
Datasheet CMTI is “very high” but errors still happen — what is the most common system-level reason?
Likely cause: The limiting factor is often not the isolator core, but rail/ground bounce, layout partition leaks, or a return path that sneaks across the barrier.
Quick check: Compare error rate across shielding/ground reference variants and watch isolated-rail noise at the exact error instant; strong correlation indicates a system-level injection path.
Fix: Rework partitioning (keepout/isolation gap), reduce coupling into VISO (filtering/placement), and ensure default/fail-safe outputs do not amplify transient states into protocol errors.
Pass criteria: Under worst-case dv/dt event set: CRC/NAK ≤ X ppm and lock-up = 0 in N events.
Power increases noticeably after isolation — where is the “hidden” power usually consumed?
Likely cause: Isolated DC/DC quiescent/efficiency loss, duplicated pull-ups (open-drain), and default-state biasing that creates continuous current.
Quick check: Measure idle current per rail: primary logic, isolated supply input, isolated rail, and bus pull-up paths (SCL/SDA). Identify which rail rises by ΔI.
Fix: Use lower-Iq isolated power where feasible, gate power in sleep, and right-size pull-ups with duty-cycle awareness; ensure no unintended back-power paths exist.
Pass criteria: Added isolation overhead ≤ X mW idle (or ≤ Y% of budget); sleep current ≤ Z.
Occasional lock-up after hot-plug — how to check far-side default state and power-up order?
Likely cause: Undefined output state during partial power leads to stuck-low/open-drain contention, or state machines see illegal edges during sequencing.
Quick check: Capture rails and bus lines during plug/unplug; verify whether SCL/SDA are released (High-Z + proper pull-up) before transactions start.
Fix: Enforce deterministic sequencing (EN/RESET gating), define bus ownership during power transitions, and add a recovery routine that forces bus release after hot-plug.
Pass criteria: After N hot-plug cycles: lock-up = 0; bus becomes idle within ≤ T.
Isolated DC/DC noise causes communication glitches — which coupling path should be checked first?
Likely cause: Rail ripple couples into isolator thresholds or reference ground, creating false edges; or DC/DC switching currents leak through layout partitioning.
Quick check: Compare glitches with DC/DC switching frequency/harmonics and rail ripple; if glitches align with ripple peaks, the rail-to-threshold path is dominant.
Fix: Improve decoupling/filters near isolator rails, tighten power loop layout, and keep switching nodes away from signal/edge-sensitive lines across the barrier.
Pass criteria: Glitches/CRC bursts ≤ X ppm at worst-case load; rail ripple ≤ Y mVpp at the isolator pins.
HiPot passes, but the system is still unstable in the field — what does that indicate?
Likely cause: Dielectric withstand verifies insulation strength, not dynamic immunity; instability points to CMTI/rail upset/timing margin, not breakdown.
Quick check: Look for error correlation with switching/hot-plug and verify timing margin at operating rate; HiPot-only success should not change these error signatures.
Fix: Treat it as an immunity/timing problem: improve partition/return, stabilize rails, and increase protocol margin (rate/phase/timeout).
Pass criteria: Under field-equivalent event set: lock-up = 0 in N events; error rate ≤ X.
Same PCB, different lot is more prone to lock-up — suspect delay drift or CMTI margin first?
Likely cause: Lot sensitivity often points to tight margins: timing (prop delay/skew variation) or power thresholds (UVLO/POR variation) that amplify CMTI events.
Quick check: Run a controlled rate/phase sweep across lots: if one lot fails only at higher speed, timing margin is tight. If failures correlate with switching while timing sweep is similar, suspect CMTI/rail immunity.
Fix: Increase margin (lower rate, lower skew topology, stronger rail robustness) and move acceptance to statistical gates (lock-up rate, retry rate) for production control.
Pass criteria: Across lots: same margin ≥ X% at target; lock-up = 0 in N events; retry ≤ Y%.
With long cable + isolation, edges get slower — isolator or pull-up/load (isolation-only diagnosis)?
Likely cause: For open-drain (I²C), rise time is dominated by pull-up and total capacitance on each side; isolation can add segment capacitance and change effective loading.
Quick check: Measure rise time separately on each side of the barrier; if one side is fast and the other is slow, the slow side pull-up/load dominates rather than the isolator core.
Fix: Ensure both sides have correct pull-ups and that the isolator is truly open-drain compatible; segment the bus so cable capacitance is not reflected across the barrier.
Pass criteria: Rise time meets the chosen mode requirement with margin: tR ≤ X on each side; error ≤ Y ppm.
Shielding change makes error rate swing a lot — in an isolated system, which domain “owns” the shield?
Likely cause: The shield can become an unintended return path that bridges domains, altering common-mode currents and effectively bypassing the barrier’s intended partition.
Quick check: Evaluate error rate under consistent switching conditions with shield connected to only one reference at a time; large deltas indicate shield-as-return behavior.
Fix: Treat shield termination as part of the partition plan: define a single “owner” domain (project-specific) and ensure the barrier is not bypassed by shield bonding choices.
Pass criteria: Across allowed shield terminations: error delta ≤ X; lock-up = 0 in N events.
How to define production acceptance thresholds: lock-up rate / retry rate / error rate?
Likely cause: Thresholds fail when they are not tied to system risk: lock-up is a “hard fail” metric, retries/errors are “degradation” metrics and must map to functional impact.
Quick check: Define an event set (power/switching/hot-plug) and the time window; decide what is unacceptable: any lock-up, or retries beyond service-level limits.
Fix: Use a tiered spec: (1) lock-up must be zero in N events; (2) retries must stay below Y%; (3) CRC/NAK/framing must stay below X ppm; include recovery time T.
Pass criteria: Lock-up = 0 in N events; retry ≤ Y%; error ≤ X ppm; recovery ≤ T.
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