Isolation, Creepage/Clearance & Intrinsic Safety (Ex i)
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Isolation compliance is not “withstand voltage only”—it is a controllable system made of insulation class, creepage/clearance geometry, material/contamination reality, and verifiable process gates. This page turns those variables into repeatable rules and acceptance evidence, including intrinsic-safety boundaries where energy limitation meets isolation.
Definition & Scope: Isolation, Creepage, Clearance, Intrinsic Safety
This section standardizes terminology and page boundaries so isolation design decisions remain safety-correct and do not drift into grounding/surge/EMI topics.
Terms & definitions (engineering-ready)
- Isolation — A safety boundary that limits hazardous energy transfer under normal and fault conditions. Typical failures: insulation breakdown, partial discharge leading to aging, barrier puncture.
- Protective Earth (PE) — A fault-current path for protective clearing; not a substitute for isolation. Typical failures: missing bond, high impedance bond, unintended shared paths.
- Clearance — The shortest air distance between conductive parts. Typical failures: air arcing (worse with altitude/field enhancement), contamination bridging.
- Creepage — The shortest path along an insulating surface. Typical failures: surface tracking from humidity/ionic residue/dust, carbonized paths.
- Intrinsic Safety (Ex i) — A hazardous-area method based on limiting available electrical/thermal energy. In this page: boundary/interface and energy-limited architecture only.
Measurement note:
Clearance and creepage are always evaluated by the shortest real path (air or surface), not by the “drawn spacing” in CAD.
What this page covers / excludes (stop-line for scope creep)
Covers
- Isolation categories (functional/basic/supplementary/double/reinforced) as safety claims.
- Creepage/clearance drivers: material CTI, pollution assumptions, altitude/air, coatings, manufacturing cleanliness.
- PCB barrier patterns: keepouts, slots, stack-up constraints near the barrier, weak-link identification.
- Intrinsic safety boundary: energy-limited interface concept and barrier placement in system architecture.
- Verification evidence chain: dielectric withstand (HiPot), insulation resistance, process controls and traceability fields.
Excludes (route to sibling pages)
- Surge/ESD/TVS placement and return-path engineering (link to Long Cable & Grounding and Low-C TVS pages).
- Magnetics/CMC/PoE center-tap protection details (link to Magnetics & Common-Mode Chokes and PoE / Data Co-Design pages).
- Protocol/TSN/PTP behavior (link to TSN Switch/Bridge and Timing & Sync pages).
Routing rule:
If a question is primarily about return paths, shield bonds, ESD or surge energy flow, it does not belong here—route to the grounding/protection pages.
Reader outcomes (deliverables, not just knowledge)
- Define the exact hazardous vs safe boundary and identify which conductors must never cross it.
- Build an inputs list for spacing decisions: Vwork, pollution assumption, CTI/material class, altitude, coating policy, manufacturing cleanliness.
- Choose an isolation approach consistent with safety claims: basic vs reinforced/double and document the claim.
- Describe an Ex i interface at architecture level: energy-limited boundary + barrier placement (no explosion-handbook scope).
- Specify verification evidence: HiPot/IR plan, process controls, and traceability fields for production.
Regulatory & Risk Model: Why “Reinforced” Exists
Reinforced isolation is not “a bigger HiPot number.” It is a safety claim that must be supported by an evidence chain: insulation system, spacing, process controls, and verification under defined assumptions.
Standards landscape (roles, not tables)
- Product safety standards define what must be safe (touch energy, fire risk, single-fault expectations) and what evidence must be retained.
- Insulation coordination methods define how spacing is determined from assumptions (working voltage, pollution, material class, altitude/air).
- Hazardous-area / intrinsic safety frameworks define energy-limited boundaries and how interfaces must be documented under fault conditions.
- Component certifications can simplify system proof, but do not remove the need to validate the weakest link at the board and assembly level.
Practical rule:
Use standards as a constraint system (assumptions → distances → verification), not as a list of memorized numbers.
Safety objective (what must be proven)
- Energy containment: hazardous energy shall not become accessible across the boundary under normal and foreseeable fault conditions.
- Spacing integrity: shortest air and surface paths shall meet the assumed environment (pollution/material/altitude/coating policy).
- Aging resilience: degradation mechanisms (tracking, partial discharge, contamination) shall be addressed by design and process controls.
- Evidence chain completeness: spacing on drawings + build cleanliness + verification data must support the safety claim.
Evidence checklist (fill with X):
Vwork=X · Pollution assumption=X · Material class/CTI=X · Altitude=X · Coating policy=X · Cleanliness controls=X · HiPot/IR plan=X
Risk-to-design mapping (turn hazards into actions)
Contamination / humidity → surface tracking
Actions: increase creepage where needed, select higher CTI materials, enforce ionic cleanliness, define coating policy, validate with worst-case environment assumptions.
Altitude / low air density → reduced air withstand
Actions: apply altitude derating to clearance, avoid sharp field features near the boundary, add spacing or physical barriers, confirm with appropriate stress tests.
Manufacturing variation → shortest path violations
Actions: define barrier keepouts/slots with DFM tolerances, prohibit copper under the barrier where required, control solder mask openings, and audit build-to-drawing.
Aging / partial discharge → long-term degradation
Actions: choose components with appropriate isolation structure, avoid voids/stress points at the boundary, and make verification reflect lifetime stress rather than “one-time pass.”
“Don’t do this” pitfalls (fast scope guard)
- Passing HiPot once does not automatically justify a reinforced claim; the claim must match assumptions and evidence chain.
- CAD spacing is not proof; shortest real air/surface paths can bypass intended slots or keepouts.
- Coating is not a default “second insulation barrier”; it must be controlled, documented, and verified against contamination and aging.
- Isolation vs grounding are different problem spaces; return-path and shield-bond decisions belong to grounding/protection pages.
Insulation System Types: Basic / Supplementary / Double / Reinforced
Insulation categories are safety claims. Practical selection requires mapping the claim to a physical barrier system, then proving independence where multiple barriers exist.
Category cheat sheet (claim → intent → typical evidence)
Functional insulation (no safety claim)
Intent: functional separation for operation only. Evidence focus: reliability/EMC performance, not touch-safety proof.
Basic insulation (single protective barrier)
Intent: one barrier prevents hazardous energy transfer under defined assumptions. Evidence: spacing, material system, process controls, and withstand/IR verification.
Supplementary insulation (additional barrier)
Intent: adds protection if basic fails. Evidence: independence checks plus documentation that the second barrier does not share the same weak link.
Double insulation (basic + supplementary)
Intent: two independent barriers provide fault tolerance. Evidence: clear separation of mechanisms, geometry, and process pathways.
Reinforced insulation (single barrier, higher objective)
Intent: one barrier achieves a higher safety objective equivalent to double insulation under defined assumptions. Evidence chain must be complete at the system level.
Key discipline:
A component certificate can simplify proof, but the system claim still hinges on the weakest air/surface path and the build process.
Architecture options (signal vs power vs both)
Signal isolation only
- Use when: data must cross a boundary, and the power system does not transfer hazardous energy across it.
- Weak link: unintended bypass paths (connectors, fixtures, chassis parts) can dominate.
- Proof focus: barrier rating + creepage/clearance around the package + build cleanliness.
Power isolation only
- Use when: isolated supply defines the boundary and signal paths are intrinsically confined or coupled via an isolated mechanism.
- Weak link: signal wiring/measurement access can re-introduce cross-boundary coupling.
- Proof focus: transformer/module spacing, PCB barrier geometry, and production consistency.
Signal + power isolation
- Use when: a strong boundary is required and both supply and data cross the boundary under controlled isolation mechanisms.
- Weak link: “two barriers” can still fail if both share the same shortest creepage path or contamination source.
- Proof focus: independence, weakest-link analysis, and a coherent evidence chain across the whole assembly.
System split reminder:
The barrier must be defined as a boundary in the architecture (hazardous vs safe). “Isolated component present” is not equivalent to “isolation boundary achieved.”
Independence checklist (two barriers must not share the same failure)
- Mechanism independence: barriers rely on different physical mechanisms (not two surfaces of the same material system).
- Geometry independence: the shortest creepage/clearance path does not traverse both barriers in the same line-of-sight.
- Process independence: manufacturing steps that can introduce residue/voids do not affect both barriers simultaneously.
- Stress independence: thermal/mechanical stress concentration is not shared (avoid stacked hotspots and cracks at one point).
- Contamination independence: typical contamination paths cannot bridge both barriers with a single residue film.
- Bypass check: metal hardware, fixtures, test points, or exposed shields do not create a cross-boundary conductive shortcut.
- Interface documentation: the boundary is explicit in the design docs and can be audited from drawings and layout.
- Evidence alignment: verification data covers the boundary’s weakest link, not only a convenient test point.
Practical consequence:
If two barriers share a single dominant weak link, the system behaves like a single barrier during aging and contamination.
Common traps (fast rejection reasons)
- Coating as “second insulation”: a coating is not automatically a supplementary barrier unless it is controlled, qualified, and verified under defined assumptions.
- Component rating equals system claim: certified parts do not fix shortest-path violations on the PCB or at connectors.
- Two barriers equals independence: two barriers can share the same creepage path if geometry and contamination are not separated.
- Ignoring bypass paths: fixtures and mechanical metalwork can dominate the boundary if not audited.
Creepage & Clearance Fundamentals: What Actually Sets the Distance
Spacing is not a constant. Clearance and creepage are outcomes of assumptions about voltage stress, environment, material behavior, and the shortest real path geometry.
Input variables checklist (missing inputs invalidate distances)
- Working voltage: RMS/DC value across the boundary under normal operation (dominant for creepage).
- Peak / transient stress: expected overvoltage and waveform assumptions (dominant for clearance).
- Environment: pollution assumption, humidity/condensation likelihood, and exposure to dust/chemicals (dominant for creepage tracking risk).
- Altitude / air: reduced air density increases arcing risk, pushing clearance requirements upward.
- Material behavior: CTI/material class and surface condition influence tracking onset and creepage effectiveness.
- Process policy: solder mask openings, cleaning/ionic residue control, and coating policy define real surface conditions.
- Geometry reality: shortest air and surface paths can bypass intended keepouts via corners, edges, or connector features.
Interpretation rule:
If the expected dominant failure mode is unknown, treat both clearance arcing and creepage tracking as plausible and design to the weaker margin.
Clearance drivers (air arcing is peak- and air-dependent)
- Peak / overvoltage: clearance is governed by the highest credible electric stress, not only nominal operation.
- Altitude / air density: reduced air withstand can turn a marginal clearance into arcing at deployment.
- Field enhancement: sharp metal edges, vias near the barrier, and connector pins concentrate field lines.
- Uncontrolled gaps: mechanical tolerances can reduce effective air distance (warpage, assembly offsets).
Design moves:
keep air paths straight and generous, reduce sharp features near the barrier, and treat altitude as a first-order input when applicable.
Creepage drivers (surface tracking is material- and contamination-dependent)
- Working voltage: creepage ties to RMS/DC stress across the surface in normal operation.
- Pollution assumption: dust, chemicals, and condensation can create a conductive film that enables tracking.
- Material CTI/class: surface resistance to tracking varies widely by material system.
- Surface condition: flux residue and ionic contamination can dominate tracking onset even when geometry appears adequate.
- Mask/coating policy: openings, edges, and partial coverage can create unexpected shortest creepage paths.
Design moves:
control contamination pathways, select materials intentionally, and treat creepage as a combined geometry + process + environment problem.
Design implication (layout, package, coating, verification)
- Layout: barrier keepouts and slots must be evaluated by shortest paths; corners and edges often dominate.
- Stack-up: copper under or near the barrier can create unintended shortest paths; define a barrier policy early.
- Packages/connectors: pin geometry and mold surfaces can become the shortest creepage path even if PCB spacing is generous.
- Coating: treat as a controlled process decision; partial coverage can worsen creepage by concentrating contamination.
- Verification: inspection should explicitly identify the controlling shortest air and surface paths before electrical withstand testing.
Forward link:
Pollution/CTI/coating deep dive belongs to the next section; altitude derating belongs to the altitude section; PCB barrier patterns belong to the PCB barrier section.
Pollution Degree, Material CTI, Coating, and Real-World Contamination
Creepage reliability is governed by surface conditions. Environment classification, material tracking resistance, and manufacturing hygiene often dominate over “distance alone.”
Environment classification (pollution degree as a practical risk model)
Clean / controlled (low deposition)
- Typical contaminants: minor dust, handling residue, occasional ionic film from rework.
- Dominant risk: localized residue at solder mask edges, test pads, and component undersides.
- Usually missed: rework areas and “hidden” low-clearance gaps under tall parts.
- Primary controls: cleaning discipline + defined keepouts + residue inspection points.
Dusty / industrial aerosols (moderate deposition)
- Typical contaminants: dust, oil mist, conductive particles, chemical vapors.
- Dominant risk: conductive film formation enabling surface leakage and tracking initiation.
- Usually missed: deposits at enclosure vents, connector edges, and PCB slot rims.
- Primary controls: surface protection strategy + contamination-resistant geometry + maintenance assumptions.
Condensing / cycling humidity (high tracking risk)
- Typical contaminants: water film, ionic contamination activated by moisture, salts.
- Dominant risk: rapid leakage increase → localized heating → tracking/carbonization.
- Usually missed: cold surfaces and corners where condensation nucleates first.
- Primary controls: controlled coating/encapsulation decisions + process proof + condensation management assumptions.
Key interpretation:
Creepage risk increases sharply once a stable moisture/ionic film can form. Distance helps, but surface condition and process discipline often dominate.
Material selection notes (CTI as a tracking-resistance lever)
- Engineering meaning: CTI reflects how resistant a material surface is to forming a permanent tracking path under contaminated conditions.
- Scope of “material”: not only PCB laminate—package mold compounds, connector plastics, slot edges, and mask systems can become the controlling creepage surface.
- Design consequence: higher tracking resistance can reduce creepage sensitivity to small contamination events, but does not remove the need for hygiene and geometry control.
- Surface condition matters: rough edges, mask openings, and residue films can nullify the intended advantage of a better material system.
Weakest-surface rule:
Creepage is governed by the surface that actually forms the shortest leakage path under contamination—not the surface that looks best in CAD.
Coating decision (what it helps, what it cannot replace, and trade-offs)
Helps when…
- deposition and moisture films are credible risks and coverage can be controlled and inspected.
- the design needs added robustness against intermittent contamination events over product lifetime.
Cannot replace…
- a defined assumption set, controlled shortest creepage paths, and a complete evidence chain.
- proper clearance design (air arcing risk remains a separate problem addressed elsewhere).
Trade-offs to budget
- manufacturing window: masking, cure control, coverage verification, and rework constraints.
- field service: repairability, inspection visibility, and failure analysis difficulty.
Failure modes if done wrong
- partial coverage creates new shortest surface paths at coating edges.
- voids/bubbles/edge beading concentrate leakage and accelerate tracking initiation.
Decision discipline:
Treat coating/encapsulation as a controlled process with inspectable coverage, not as an informal “safety margin multiplier.”
Manufacturing hygiene checklist (prevent ionic films and tracking seeds)
- Boundary map: mark the isolation boundary and the creepage-critical surfaces on drawings and layout views.
- Residue hotspots: identify rework zones, hand-solder zones, and component undersides as primary residue risks.
- Mask openings control: constrain solder mask openings near creepage-critical paths; avoid sharp mask corners at the boundary.
- Cleaning plan: define cleaning steps and acceptance criteria for residue removal (including hard-to-reach gaps).
- Inspection points: add inspection views for slot edges, connector feet, and boundary-adjacent test pads.
- Rework governance: track rework count and require re-clean + re-inspection after any touch-up near the boundary.
- Handling discipline: control fingerprints and fibers near the boundary (surface films can seed leakage).
- Coating readiness: if coating is used, define masking areas, coverage targets, and verification method before release.
- Coverage verification: verify coating continuity at edges; edge beading is a common failure seed.
- Traceability fields: record cleaning batch, coating batch, cure conditions, and rework history for boundary-critical builds.
- Aging assumptions: document expected dust/moisture exposure and maintenance intervals in the product use-case.
- Weakest-path review: explicitly identify the controlling creepage path under plausible contamination scenarios before verification.
Outcome:
The goal is to prevent stable conductive films and tracking seeds from forming on the controlling surface path.
Altitude / Spacing Derating and Enclosure Strategies
Clearance is governed by air withstand. Reduced air density at altitude can shrink arcing margin, making deployment conditions a first-order input to spacing, enclosure, and layout decisions.
Altitude effect summary (why clearance margin changes in the field)
- What changes: lower air density reduces withstand, increasing arcing likelihood for the same air gap.
- What does not change: creepage along surfaces is driven primarily by contamination and material behavior (handled in the previous section).
- Typical surprise: designs pass in lab conditions but become marginal at deployment altitude or in low-pressure enclosures.
- Practical rule: if deployment altitude is unknown, spacing decisions should assume conservative conditions early.
Controlling path:
Clearance failures usually follow the shortest air path near sharp features, connector pins, and edge geometries.
Enclosure tactics (when barriers help, and when they do not)
- Partition / inner chamber: effective when it physically separates the hazardous region and prevents line-of-sight air paths across the boundary.
- Insulating shields: helpful when they lengthen air paths and reduce field concentration; ineffective if edge gaps preserve the shortest path.
- Potting / encapsulation: can change the effective dielectric environment, but only if voids are controlled and the process is inspectable.
- Failure seeds: vents, seams, and mounting features can create unrecognized shortest air paths that dominate clearance margin.
Enclosure discipline:
A barrier is only useful if it changes the controlling path. Decorative plastic near the boundary does not count.
Layout tactics (make the shortest air path longer and less stressed)
- Route around the boundary: avoid “straight across” air gaps; create intentional detours for the shortest path.
- Remove sharp features: keep vias, pads, and pin tips away from the boundary; sharp geometry concentrates field.
- Control edges and corners: PCB edges and slot rims often set the controlling air distance.
- Define keepouts: declare a barrier keepout region and enforce it consistently across copper, mask, and silkscreen.
- Mechanical alignment: include assembly tolerances; warpage and offsets can reduce real clearance.
Field-ready mindset:
Clearance must survive deployment conditions, assembly tolerances, and the worst credible geometry—not a best-case drawing view.
Verification notes (prove derating assumptions are covered)
- Identify the controlling clearance path: document the shortest air route and the sharpest field features near it.
- Bind deployment assumptions: record the altitude/pressure range and enclosure configuration used for the design decision.
- Validate with representative builds: include mechanical tolerances and the real enclosure/barrier parts in the test article.
- Record traceability: enclosure version, barrier parts, potting batch (if used), and assembly offsets.
Pass logic:
The design is acceptable when the controlling air path remains non-controlling under the worst assumed deployment conditions.
Intrinsic Safety (Ex i) Basics: Energy Limitation Meets Isolation
Intrinsic safety is not “stronger isolation.” It is a system method that limits available energy and documents a clear boundary so the hazardous-side circuit remains non-incendive in normal and fault conditions.
Ex i mental model (non-incendive by design, not by “withstand”)
- Goal: ensure the hazardous-side circuit cannot deliver sufficient energy to ignite an explosive atmosphere under normal operation and defined faults.
- Boundary: define a physical and documentation boundary between the safe side and the field device side.
- Energy view: treat the field side as a load that can store energy (capacitance/inductance) and release it during faults.
- Proof chain: limit source capability, bound external wiring/device parameters, and maintain traceable interface documentation.
Common pitfall:
High dielectric withstand alone does not imply intrinsic safety; energy limitation and boundary conditions must be explicit.
Entity parameters primer (how to think and how to write the interface)
Source capability (what the barrier can supply)
- V / I / P limits: define maximum output voltage, current, and power under normal and fault assumptions.
- Fault framing: specify which single-fault or credible faults the limits cover (documented, testable scope).
External allowance (what may be connected on the field side)
- C / L bounds: specify maximum external capacitance and inductance allowed at the hazardous-side interface.
- System sum: field device + cable + any permitted accessories must remain within the stated allowance.
Field device inputs (what the device contributes)
- Cᵢ / Lᵢ concept: the device can store energy; document its effective input capacitance and inductance.
- Parallel risk: multiple devices or add-on modules can raise total capacitance; limit counts explicitly.
Cable modeling (how wiring changes the energy budget)
- C/m and L/m: document the per-meter parameters and maximum cable length used in the compliance argument.
- Change control: cable type or length changes require re-checking the entity-parameter sums.
Practical template:
“Barrier output limits (V/I/P) + allowed external C/L + cable limits + field device C/L inputs” is the minimum interface set required for review and field installation control.
Barrier types overview (what changes at the system boundary)
- Zener barrier (clamp + limit): energy limitation via clamping/limiting; documentation must specify installation dependencies and the allowed field-side entity parameters.
- Galvanic isolating barrier: integrates isolation with controlled output limits; reduces reliance on external references, but still requires explicit V/I/P and C/L allowances.
- Integrated barrier module: combines power and signal conditioning; gains integration, but must remain transparent in interface documentation and verification traceability.
Selection lens:
Prefer barrier types that make the boundary assumptions explicit and enforceable, not only electrically plausible.
Interface documentation checklist (make the boundary reviewable)
- Boundary diagram: Safe side → Barrier → Hazardous device, including terminals and cable segment.
- Output limits: Vmax / Imax / Pmax under the defined normal/fault assumptions.
- External allowance: maximum permitted external C and L at the hazardous interface.
- Field device inputs: required Ci/Li data fields and how to sum multi-drop devices (if allowed).
- Cable limits: cable type assumptions (C/m, L/m) and maximum length.
- Accessory policy: explicit rules for add-on modules; prohibit unreviewed parallel capacitance on the field side.
- Installation notes: any barrier-type dependencies must be recorded as installation constraints.
- Change control: cable length/type, field device swap, and wiring topology changes trigger a parameter re-check.
- Verification references: link the interface parameters to test records and configuration snapshots.
- Trace fields: barrier part, firmware/config, wiring length, and device parameters used in the assessment.
- Pass criteria: controlling assumptions are documented and enforceable at installation and service time.
Review outcome:
A compliant interface is one where the hazardous-side energy budget remains bounded by documented parameters even after credible field changes.
PCB Isolation Barrier Patterns: Slots, Keepouts, Layer Stack, Assembly
Translate creepage/clearance requirements into a visible isolation band on the PCB. The best layouts make the controlling path obvious, enforceable across layers, and robust against assembly and contamination.
Barrier geometry patterns (repeatable templates)
Pattern A: straight isolation band
- What: one continuous keepout band that visually separates domains.
- Why: simplifies review and prevents accidental crossings.
- Watch: silk, glue, and test pads near the band can become contamination seeds.
Pattern B: detoured surface path
- What: shape the boundary so the controlling creepage path must “walk around” features.
- Why: improves creepage without expanding the entire board outline.
- Watch: corners and narrow channels can trap residues and moisture films.
Pattern C: edge / connector-adjacent barrier
- What: reinforce the isolation band near pins, edges, and mechanical features.
- Why: sharp features and assembly offsets often control real clearance distance.
- Watch: edge burrs, slot rims, and mechanical tolerance stack-ups.
Design intent:
Make the controlling path visible in layout reviews and enforce it with zone-based rules across all layers.
Slot / keepout trade-offs (when slots help and what they cost)
Benefits
- lengthens the surface path by forcing creepage detours around a void.
- reduces direct contamination bridges across the boundary when geometry is controlled.
Costs and risks
- manufacturing tolerance and edge quality can dominate the real margin.
- mechanical strength changes; slot location must consider assembly stress.
- slot rims can trap residues if cleaning access is poor.
Inspection points
- verify slot edge quality and absence of burrs or residual debris.
- check mask integrity near slot rims; edge defects can become shortest paths.
- confirm mechanical offsets do not reduce the controlling air gap near the slot.
Use condition:
A slot only “counts” when it forces the controlling creepage path to detour and the edge quality is consistently verifiable.
Stack-up rules (enforce the barrier across all layers)
- Zone-based keepouts: define a barrier keepout region object and apply it to top, inner, and bottom layers consistently.
- No copper under the barrier: keep the isolation band free of copper and vias to prevent hidden shortest paths on inner layers.
- Avoid sharp copper near edges: pads, via fences, and pointed pours near the boundary can concentrate field and reduce effective clearance.
- Mask discipline: uncontrolled mask openings near the band can promote residue accumulation and shorten creepage under contamination.
- Mark the boundary: add a clear boundary marking on mechanical and assembly views (without placing silk across the barrier zone).
Review focus:
The controlling path must be evaluated in 3D (layers + assembly offsets), not only in a single top-layer screenshot.
Assembly & cleanliness (protect the barrier from real-world residues)
- No process clutter at the band: avoid placing silk blocks, glue dots, and boundary-adjacent test pads within the isolation keepout.
- Rework governance: any rework near the barrier triggers re-clean and re-inspection of the controlling creepage path.
- Hidden gaps matter: component undersides and narrow channels near the band are common cleaning blind spots.
- Change control: modifications to cleaning, coating, or adhesives near the band require an updated evidence chain.
Field robustness:
A barrier that is cleanable, inspectable, and traceable is more reliable than a barrier that is only wide on paper.
“Pass criteria” checklist (reviewable and auditable)
- Barrier zone defined: an explicit keepout region exists and is referenced in design rules and drawings.
- All-layer enforcement: top, inner, and bottom layers respect the same barrier zone constraints.
- Controlling creepage path identified: the shortest surface path is marked and reviewed under contamination assumptions.
- Controlling clearance path identified: the shortest air path near sharp features and edges is reviewed with assembly tolerances.
- No copper under band: copper pours, vias, and inner-layer features do not create hidden shortest paths.
- Slot integrity (if used): slot edge quality and tolerance are documented and inspected.
- No process artifacts: silk, glue, and test features are excluded from the barrier keepout.
- Cleanability confirmed: the barrier region can be cleaned and inspected in the real assembly.
- Rework rule defined: rework near the barrier triggers cleaning + inspection + trace recording.
- Trace fields ready: board revision, assembly process, and inspection records are tied to the barrier assumptions.
Acceptance intent:
The barrier is acceptable when the controlling paths remain controlled after tolerances, assembly, and credible contamination events.
Components at the Barrier: Packages, Isolation Ratings, and Weak Links
Many isolation failures are not caused by the PCB gap itself, but by the weakest point around packages, module surfaces, and connector interfaces where the shortest path or contamination bridge forms.
Component taxonomy (classification by barrier role)
Signal isolation parts
- digital isolators, optocouplers, isolated amplifiers
- Focus: package creepage/clearance, working vs withstand ratings, aging/PD evidence
Power isolation blocks
- isolated DC-DC modules, isolated supplies, integrated barrier modules
- Focus: insulation system integrity, thermal aging, module surface paths, sealing seams
Boundary connectors / terminals
- terminal blocks, board-to-wire connectors, pluggable modules
- Focus: pitch & surface tracking, contamination sensitivity, service wear and cleanability
Review lens:
Classify by barrier role to avoid missing the controlling weakest path at the interface.
Weak-link checklist (shortest-path + contamination sensitivity)
- Pin-to-pin air gap: solder beads, residues, and tolerance shifts can reduce the effective clearance at the tightest pin spacing.
- Along package surface: creepage often follows the molded surface, not the PCB outline; identify the controlling path explicitly.
- Under-body blind zones: shadowed regions under packages and modules are common cleaning blind spots for ionic residue bridges.
- Connector body surface: plastics can form long, contamination-sensitive surface paths between adjacent terminals.
- Assembly artifacts: silk, glue, flux, and conformal-coating edges can unintentionally create continuous surface films across the boundary.
- Module edge / seam: seams, potting edges, and housing joints can define the real shortest path in humid or dusty deployments.
Practical rule:
The weakest link is where the shortest path overlaps with a contamination-prone surface and an uncontrolled process step.
Package/layout coupling (how placement can “steal” margin)
Orientation and body proximity
- rotate packages so the controlling surface path does not become the shortest route.
- keep a clean keepout ring around the body; the body surface can control creepage.
Slots and detours must align
- a slot only helps if it forces the controlling creepage path to detour around the void.
- avoid placing slot rims under residue-prone regions or rework zones.
Process features near the boundary
- exclude silk blocks, glue dots, and dense test pads from the barrier-adjacent area.
- treat rework near the barrier as a controlled event requiring re-clean and inspection.
Design intent:
Placement must preserve the intended controlling path margin after tolerances, residues, and service events.
Documentation fields (lock the assumptions into BOM and drawings)
Device-level insulation fields
- insulation class (basic / reinforced / double) aligned to the system target
- working voltage basis (RMS/DC) vs dielectric withstand basis (test condition)
- package creepage and clearance distances (as provided by the component)
- aging / partial discharge note field (evidence reference or requirement)
Connector / terminal interface fields
- pitch and insulating surface path notes (creepage/clearance at the interface)
- contamination sensitivity note and cleanability/service expectation field
- approved orientation and keepout callouts near the boundary
Change-control triggers
- package change, connector change, coating/cleaning process change → re-qualification required
- approved alternates list with evidence references
- inspection checkpoints and trace fields for each lot
Outcome:
Documentation turns “one-time compliance” into repeatable manufacturing and service consistency.
Engineering Checklist: Design → Bring-up → Production (Quality & Consistency)
A robust isolation boundary is achieved when assumptions, layout rules, verification evidence, and production controls form a consistent gate-by-gate workflow with traceable outputs.
Gate 1 — Design inputs (assumptions locked)
Checklist
- □ maximum working voltage and intended insulation class (basic/reinforced/double)
- □ environment assumptions: pollution degree and surface contamination risk
- □ material assumptions: CTI/material group field is defined (or flagged as TBD)
- □ altitude range and whether spacing derating applies
- □ coating/potting decision and its scope is recorded
Outputs
- assumptions sheet + boundary diagram
- BOM fields for isolation ratings and package creepage/clearance
Pass criteria
All controlling variables have a defined basis and owner; “unknown” items are tracked with closure actions.
Gate 2 — Layout enforcement (controlling paths visible)
Checklist
- □ isolation band defined as a region object (not ad-hoc keepouts)
- □ all-layer keepout and “no copper under band” rules applied
- □ controlling creepage and clearance paths are marked (screenshots)
- □ slot/DFM tolerance and edge quality requirements are documented (if used)
- □ package weak-link review: body surface, under-body blind zones, connector surfaces
Outputs
- DRC report + annotated path screenshots
- weak-link map notes tied to placement and connector choices
Pass criteria
Controlling paths remain controlled across layers and tolerances; the barrier region is enforceable and reviewable.
Gate 3 — Bring-up verification (evidence chain)
Checklist
- □ insulation resistance (IR) checks under defined conditions
- □ dielectric withstand / HiPot per the defined plan and assumptions
- □ stress strategy: humidity/contamination exposure plan is defined and recorded
- □ pre/post inspection of the barrier region for tracking marks or residue bridges
Outputs
- test plan + raw logs + configuration snapshot
- photos of the barrier region before/after tests
Pass criteria
Isolation metrics remain stable under defined stresses; any deviation is traceable to a specific weak-link category with corrective actions.
Gate 4 — Production control (consistency and traceability)
Checklist
- □ test strategy defined (sampling vs 100%) based on risk and weakest-link sensitivity
- □ fixture discipline: keep the barrier region protected from contamination and unintended shortcuts
- □ cleanliness controls and inspection checkpoints are recorded per lot
- □ rework triggers and re-inspection rules are explicit and enforceable
- □ change-control triggers (package/connector/process) automatically route to re-qualification
Outputs
- production control plan + lot records + rework logs
- approved alternates list with evidence references
Pass criteria
Every shipment preserves the same boundary assumptions; deviations are caught by traceable records and controlled re-qualification triggers.
Applications: Where Isolation & Spacing Rules Matter in Industrial Ethernet
Each use case is reduced to three decisions: where the boundary sits, why reinforced insulation is required, and what weak link typically fails first under real contamination and service conditions.
Use case 1 — Remote I/O island (cabinet ↔ remote I/O)
- Boundary: controller/cabinet safe domain ↔ remote I/O field domain (serviceable, contamination-prone edge).
- Why reinforced: higher fault-tolerance target where user access, pollution, and foreseeable misuse are realistic.
- Most common weak link: terminal/connector surface tracking; under-body residue bridge near the barrier; “shortest path” migrating after rework.
Example BOM items (part numbers)
- Digital isolator (signal barrier): TI ISO7741, ADI ADuM141E, Silicon Labs Si8642
- Isolated power (module): Murata NME0505SC, Murata NXJ2S0505MC, RECOM R05P05S
- Isolated analog sensing (if required): TI AMC1301, TI AMC1311
Links-out (stop line): Protection/TVS/Surge and Grounding/Shielding belong to their dedicated pages.
Use case 2 — Field sensor / transmitter boundary (safe side ↔ hazardous/field device)
- Boundary: safe-side control/power ↔ field device interface where contamination and maintenance are expected.
- Why reinforced: the barrier is treated as a safety boundary with single-fault tolerance expectations.
- Most common weak link: interface documentation mismatch (rating basis not aligned); connector/terminal surface tracking under humidity; residue bridges after wiring service.
Example BOM items (part numbers)
- Isolated analog front-end (measurement boundary): TI AMC1311, TI AMC1301, TI ISO124
- Digital isolator (control/status lines): TI ISO7842, ADI ADuM1201
- Isolated power (module): Murata NME0505SC, RECOM R05P05S
- Industrial barrier module (system-level, if applicable): MTL MTL5541, Pepperl+Fuchs KFD2-STC4-Ex1
Links-out (stop line): detailed hazardous-area compliance and protection topology must remain in dedicated pages.
Use case 3 — Gateway / switch port service edge (internal logic ↔ external port domain)
- Boundary: internal power/logic domain ↔ external port/service domain where wiring and rework are common.
- Why reinforced: the port edge is exposed to uncontrolled environment and repeated handling; safety objective requires stable margin across life.
- Most common weak link: connector surface path; module seam/edge path; residue film near the boundary after service events.
Example BOM items (part numbers)
- Digital isolator (service/auxiliary lines): TI ISO7741, ADI ADuM141E
- Isolated power (module): Murata NXJ2S0505MC, RECOM R05P05S
- Isolated feedback/control (if needed): ADI ADuM3190
Links-out (stop line): surge/TVS and cable grounding decisions must link out to the protection/grounding pages.
Use case 4 — Motor cabinet / process boundary (control domain ↔ high-energy equipment domain)
- Boundary: control/communication domain ↔ equipment domain where contamination and maintenance are recurrent.
- Why reinforced: reinforced insulation is used to meet safety objective with single-fault tolerance and foreseeable misuse constraints.
- Most common weak link: pollution degree underestimated; coating mistaken as “second insulation”; slot/keepout loses margin under DFM tolerance and rework.
Example BOM items (part numbers)
- Isolated sensing (equipment feedback boundary): TI AMC1301, TI AMC1311
- Digital isolator (control interface boundary): TI ISO7842, Silicon Labs Si8642
- Isolated power (module): Murata NME0505SC, RECOM R05P05S
Links-out (stop line): grounding/shielding and protection implementation details must link out to their dedicated pages.
IC Selection Logic: Choosing Isolation Devices Without Crossing Into Other Pages
Selection is treated as a rating-alignment workflow: define inputs, choose a device category, validate insulation/spacing claims using consistent bases, then bind the choice to a verification plan and documentation fields.
Selection inputs (must be stated explicitly)
- Safety target: basic vs reinforced/double insulation objective (system-level intent).
- Interface needs: channel count, directionality, timing constraints (avoid protocol deep-dives here).
- Power strategy: isolated power required or not; allowed dissipation/thermal margin.
- Environment: pollution degree assumption, CTI/material group basis, altitude derating expectation.
- Life & evidence: lifetime expectation and whether PD/aging evidence is required in documentation.
Category decision (examples with concrete part numbers)
Digital isolators (capacitive/magnetic coupling)
Typical when timing and multi-channel integration matter; validate package creepage/clearance and reinforced claim basis.
- TI: ISO7741, ISO7842
- ADI: ADuM141E, ADuM1201
- Silicon Labs: Si8642
Optocouplers (LED/photodetector)
Typical when legacy qualification or specific isolation behaviors are required; check aging/lifetime evidence and CTR margins.
- Broadcom: HCPL-0601, ACPL-064L
- Vishay: VO615A, VO617A
- Toshiba: TLP2361
Isolated power: module vs discrete
Modules simplify spacing consistency; discrete designs demand tighter process control and documentation of the insulation system.
- Module: Murata NME0505SC, Murata NXJ2S0505MC, RECOM R05P05S
- Discrete driver example: TI SN6505 (pair with an appropriately rated transformer per insulation objective)
- Isolator with integrated power example: ADI ADuM5401
Isolated analog measurement (if the boundary crosses analog)
Use when measurement integrity must remain across the barrier; align working/withstand bases and verify under pollution/humidity stress assumptions.
- TI: AMC1301, AMC1311, ISO124
- ADI (control/feedback isolation example): ADuM3190
Critical rating bases (must align across datasheet, BOM, and verification)
- Working voltage basis: RMS/DC basis used for creepage sizing and long-term stress assumptions.
- Dielectric withstand basis: test condition basis (duration, waveform, environmental condition) must be documented.
- Package creepage/clearance: the component’s own distances can be the controlling weakest path.
- Insulation class claim basis: basic/reinforced/double claim must match the system safety objective.
- Aging / PD evidence field (if applicable): record what evidence is required and how it will be verified/qualified.
- Certification alignment field: record which safety/cert family the build targets (do not mix bases silently).
Verification plan binding + stop line
Bind the choice to a plan
- IR checks with recorded conditions and boundary photos.
- Dielectric withstand/HiPot per the declared basis with raw logs retained.
- Humidity/contamination stress strategy recorded (as an assumption-driven plan).
- Lot/variant trace: exact ordering suffix, package option, and process notes recorded in BOM.
Stop line (link out, do not expand here)
If the selection decision depends on TVS, surge energy, grounding return paths, or shielding termination, stop and link to the dedicated Protection / Grounding pages.
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FAQs: Isolation, Creepage/Clearance, and Intrinsic-Safety Boundary Pitfalls
These FAQs close common field and audit disputes without expanding the main body. Each answer is a fixed four-line checklist for fast triage and repeatable acceptance.
HiPot passes once, later units fail—process contamination or spacing margin?
Likely cause: insulation margin is being consumed by contamination/ionic residue drift or assembly variance at the barrier’s weakest path.
Quick check: compare IR/HiPot leakage logs by lot + cleaning/flux batch + humidity exposure; inspect barrier edge for residue bridges and solder “fingers.”
Fix: lock the cleanliness window (flux/cleaning/bake), tighten keepout/slot tolerances, and add a “weak-link photo record” at the barrier for each build variant.
Pass criteria: leakage ≤ X at Vtest for t=X; IR ≥ X MΩ at V=X; failure rate ≤ X ppm across X lots with traceable process records.
Clearance OK on CAD, but inspector says fail—where is the “shortest air path” actually measured?
Likely cause: the true minimum clearance is a 3D path around component bodies, solder fillets, burrs, or misalignment—not the 2D CAD dimension.
Quick check: re-measure the minimum air path on the assembled unit (including solder meniscus and tolerances) using the same inspection definition and reference points.
Fix: add explicit “inspection geometry” notes (datum-to-datum), increase clearance at the real choke point, and control assembly variance (standoff, coplanarity, solder limit).
Pass criteria: measured minimum clearance ≥ X mm using the inspector’s method across X samples; documented measurement method and photos retained.
Added conformal coating but tracking still happens—what’s the first hygiene check?
Likely cause: coating does not remove ionic residues; it can trap contamination or leave coverage voids that become conductive under humidity.
Quick check: perform an ionic contamination screen (quick method) and inspect coating coverage at the barrier edge/under components for thin spots, bubbles, or shadowing.
Fix: enforce cleaning verification before coating, define coating keepout/coverage rules near the barrier, and eliminate “contamination reservoirs” (silkscreen/adhesive near the band).
Pass criteria: ionic contamination ≤ X (per chosen method); no visible voids at barrier; IR ≥ X MΩ at V=X under RH=X% for t=X.
Reinforced target met on device datasheet, but system still rejected—what documentation field is missing?
Likely cause: the system file lacks a consistent basis for working voltage/withstand conditions, creepage/clearance path definition, or the insulation class claim mapping.
Quick check: verify the BOM/drawing explicitly records: working voltage basis, withstand test basis, package creepage/clearance, insulation class claim basis, and targeted certification family.
Fix: add a mandatory “insulation evidence block” to BOM + drawings, lock ordering suffix/variant fields, and attach verification logs/photos per gate.
Pass criteria: evidence block completeness = X/100%; reviewer can trace claim → basis → test record within X minutes; version-locked documents maintained.
Slot added but creepage didn’t improve—did the creepage path bypass the slot via solder mask?
Likely cause: the real creepage path follows solder mask, board edge, component surface, or residue films and can “bridge around” the slot.
Quick check: trace the shortest along-surface path on the finished assembly (mask openings, fillets, sidewalls) and mark the true minimum creepage route with photos.
Fix: adjust mask strategy (keepout/openings), widen/relocate slot, enforce copper keepouts under the band, and remove contamination traps near the detour path.
Pass criteria: verified shortest creepage path ≥ X mm per documented route; DFM tolerance analysis shows worst-case ≥ X mm.
Works in lab, fails in humid plant—pollution degree assumption wrong or cleaning residue?
Likely cause: the assumed pollution degree/material behavior does not match reality, and humidity activates residual ionic contamination into a conductive creepage path.
Quick check: reproduce with controlled RH/condensation window; run an ionic contamination screen and inspect barrier-adjacent surfaces for residue films and dust-catch geometry.
Fix: upgrade the environmental assumption in the insulation file, enforce hygiene gates (cleaning + verification), and increase margin via barrier geometry (keepout/slot/coverage rules).
Pass criteria: IR/HiPot stable within X% under RH=X% for t=X; contamination ≤ X; failure-free across X cycles of humidity exposure.
Altitude deployment causes unexpected arcing—first derating check?
Likely cause: clearance margin is reduced at lower air density; the design used a sea-level assumption without altitude derating basis.
Quick check: confirm deployment altitude and whether the insulation file explicitly applies an altitude factor to clearance at the true minimum air path.
Fix: increase clearance at the choke point, add internal barriers/compartments where appropriate, and lock an altitude derating rule into the design gate inputs.
Pass criteria: clearance (measured path) ≥ X mm after derating at altitude=X; no breakdown at Vtest=X for t=X across X samples.
Intrinsic-safety review fails—entity parameters mismatch or barrier type wrong?
Likely cause: entity parameter interface is incomplete or inconsistent (V/I/P and external C/L) or the barrier type assumption does not match the interface documentation.
Quick check: reconcile the safe-side output limits vs field-device allowed inputs and external C/L limits using one declared basis; verify the barrier type is stated in the interface file.
Fix: standardize the entity-parameter table template, lock versions for both sides of the interface, and add a review gate that blocks release on mismatch.
Pass criteria: all entity parameter fields complete; margin ≥ X for V/I/P and C/L; review checklist passes with evidence pack attached.
Creepage ok, clearance fails at terminals—connector package weak link?
Likely cause: the controlling clearance is at the connector/terminal geometry or solder meniscus, not the PCB barrier band; 3D shortest air path is smaller than expected.
Quick check: locate the minimum air path around terminal bodies, pins, and solder fillets under worst-case tolerances and contamination build-up areas.
Fix: select a connector/terminal family with adequate spacing, add barriers/partitions, and enforce keepouts that account for assembly and solder limits.
Pass criteria: measured minimum terminal clearance ≥ X mm across X samples; terminal family and inspection method are documented in BOM/drawing fields.
Two isolation barriers used, but still not accepted—are they truly independent?
Likely cause: the two barriers share the same failure mechanism (same surface path, same contamination source, or same process/material), so they are not independent in practice.
Quick check: audit whether both barriers can be defeated by one event (one residue film, one crack, one assembly shift) and whether the shortest paths overlap.
Fix: enforce independence by separating paths/materials/process controls, and document “independence rationale” as a required design gate artifact.
Pass criteria: independence checklist meets X/X items; no single documented failure mechanism defeats both barriers; evidence pack retained.
Production yield drops after flux change—what’s the quickest ionic contamination check?
Likely cause: flux chemistry or cleaning window changed the ionic residue level, creating humidity-activated leakage and tracking risk along the surface path.
Quick check: run a fast ionic contamination screen on suspect lots and correlate with IR drift at the barrier; inspect for residue pooling near the isolation band.
Fix: lock flux/cleaning/bake parameters, add in-line cleanliness verification, and set a reject gate tied to contamination and IR thresholds.
Pass criteria: contamination ≤ X (method-defined); IR ≥ X MΩ at V=X; yield returns to ≥ X% for X consecutive lots.
After potting, IR improves but failures appear after thermal cycling—mechanical stress cracking?
Likely cause: potting improves initial insulation resistance but introduces stress/CTE mismatch that causes micro-cracks or delamination paths after cycling.
Quick check: compare IR/leakage trends before vs after thermal cycling; inspect for cracks at barrier edges and interfaces (potting-to-board, potting-to-component).
Fix: tune potting material/process window, add mechanical relief features, and extend verification to include post-cycle IR/HiPot with evidence retention.
Pass criteria: post-cycle IR ≥ X MΩ and leakage ≤ X at Vtest=X; no crack/delamination evidence in X samples after X cycles.
