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PoDL for SPE (Single-Pair Ethernet): Class A/B/C, Loss & Thermal

← Back to: Industrial Ethernet & TSN

PoDL for SPE succeeds when the powered device operating point is guaranteed at the worst corner: PD-side voltage stays above Vmin, total power stays within budget, and temperature rise stays within limits—without restart storms.

This page turns “long cable failures” into an engineering budget and verification path (class → line-loss compensation → thermal derating → logs), so the same design remains stable across cable length, load steps, and temperature.

H2-1 · Definition & Scope (PoDL for SPE)

What this section enables

  • Define PoDL for Single-Pair Ethernet in one engineering sentence.
  • Explain why long-run deployments fail (voltage margin, line loss, thermal, and recovery behavior).
  • Lock the page boundary (scope guard) so later chapters stay deep without overlapping sibling pages.

One-sentence definition

PoDL (Power over Data Line) delivers controlled DC power over the same SPE twisted pair that carries Ethernet data, so the remote Powered Device (PD) receives data + power on one pair with defined protection, limits, and recovery behavior.

Success criteria (engineering pass/fail)

  • PD-side voltage margin: under worst-case length + worst-case temperature + worst-case load step, VPD,min ≥ Vmin + X V (or margin ≥ X%).
  • Power budget integrity: total loss (cable + connectors + protection + PCB copper) stays within Ploss,total ≤ X%, and available PD power meets Pavail ≥ Pload,peak + X%.
  • Thermal stability: with the real enclosure and ambient, hot spots satisfy Tj,max ≤ Tlimit − X °C (or ΔTcase ≤ X °C).
  • Controlled fault & recovery: UVLO/OCP/OTP events must not create reboot storms: retries ≤ X per minute, and post-recovery stability ≥ Y minutes with logs.

Scope guard (to avoid overlap)

In-scope

  • PoDL class selection (A/B/C) in practical power-and-reach terms.
  • Line-loss and PD-voltage budgeting (including temperature impact).
  • Line-loss compensation strategies and their stability/limit hooks.
  • Thermal management and derating for long-run sensor deployments.

Out-of-scope (link-only)

  • SPE PHY equalization/training and EMI fine details → SPE PHY page.
  • 802.3 PoE (af/at/bt) end-to-end mechanisms → PoE PSE/PD pages.
  • TSN scheduling/parameterization and timing algorithms → TSN / Timing pages.
  • Low-cap TVS/CMC deep selection rules → Protection page.

Deliverable: decisions this page will enable

  1. Target PD load envelope: Pload,peak, Vmin, and allowable ripple/steps.
  2. Candidate cable & connector plan driven by Rloop and temperature rise.
  3. PoDL class (A/B/C) choice aligned with reach, power, and thermal constraints.
  4. Loss-compensation method (static/dynamic/temp-aware) and required sensing taps.
  5. Derating policy (thresholds + step-down ladder) to avoid uncontrolled resets.
  6. Verification matrix (length × load × temperature) and pass/fail criteria placeholders (X/Y).
  7. Field-service logging: voltage/current/temperature/event counters to make “rare failures” reproducible.
PoDL for SPE: Scope Map PoDL over SPE Data + Power on one pair Class A B C Budget Compensation Thermal Out-of-scope links: SPE PHY · PoE (802.3) · TSN/Timing · Industrial Stacks · Protection
Diagram goal: define what this page owns (Class, Budget, Compensation, Thermal) and what belongs to sibling pages.

H2-2 · System Architecture (Power + Data on One Pair)

What this section enables

  • Make the system explicit: where power is injected, where it is consumed, and where voltage drop/heat is created.
  • Separate two views that must coexist: the data path and the DC current loop.
  • Define measurement taps (V/I/T) so budgeting, compensation, and field diagnostics become repeatable.

System roles (kept PHY-agnostic)

  • Power sourcing side: sets class/limits, senses V/I, applies compensation and protection policy.
  • Cable + connectors: contribute distributed Rloop and thermal rise; contact resistance can dominate long-run failures.
  • Protection / coupling network: shapes surge/ESD return and may add leakage and heat; placement matters more than raw rating.
  • Remote PD: enforces UVLO/OCP/OTP behavior, converts power to load rails, and exports telemetry for diagnostics.

Two-path model (must be drawn as two overlays)

Data path (AC/differential)

Treated as a differential pair that must remain balanced; protection and coupling must avoid adding asymmetry that degrades link margin.

Power path (DC current loop)

Treated as a current loop that creates I×R voltage drop and I²×R heating across cable, connectors, protection, and PCB copper. Without an explicit loop drawing, surge return, TVS placement, and shield bonding are commonly implemented incorrectly.

Why the current loop must be explicit

  • Surge/ESD anomalies: the system can pass a lab shot yet become “more fragile” later if return paths force stress through sensitive regions.
  • Reboot storms: inrush or load steps trigger OCP/UVLO, causing repeat retries and unstable sensor behavior.
  • Temperature-only failures: copper resistance rises with heat, shrinking VPD margin and pushing the PD into UVLO thresholds.
  • Connector aging: contact resistance drift acts like an invisible “extra cable length,” shifting both drop and heat hotspots.

Deliverable: measurement taps (V / I / T) to standardize budgeting and diagnostics

Tap Location Primary purpose Pass criteria (placeholders)
Vtap-SRC Source output (before cable) Budget reference for total drop Stable within X% under load steps
Vtap-IF After protection/coupling Detect added drop/leakage from protection ΔV ≤ X V vs Vtap-SRC at I=Y
Itap-SRC Source current sense Capture inrush + OCP boundary Ipeak ≤ X; no OCP trips in Y runs
Vtap-PD PD input (after cable) Validate PD-side margin and UVLO immunity VPD,min ≥ Vmin + X V under worst-case
Ttap-HOT PD hotspot / connector hotspot Anchor thermal derating and cable heating assumptions ΔT ≤ X °C; stable after Y minutes steady-state

Tip: use consistent naming (Vtap-*, Itap-*, Ttap-*) in schematics, firmware telemetry, and lab reports to avoid metric-definition drift.

One-Pair Power Path + Measurement Taps PoDL Source Class / Limit / Sense Protection Coupling / Clamp Conn Contact R Long Cable Rloop + Temp Rise Remote PD UVLO/OCP/OTP Load Sensor Rails DATA POWER Vtap-SRC Vtap-IF Vtap-PD Itap-SRC Ttap-HOT Budget and diagnostics start here: measure V/I/T at defined taps before tuning compensation or derating.
Diagram goal: force a dual overlay (data path + DC current loop) and standardize V/I/T measurement taps for repeatable power budgeting.

H2-3 · Class A/B/C: What They Guarantee and What They Don’t

What this section enables

  • Turn “Class A/B/C” into an engineering guarantee at the PD side, not a marketing number.
  • Correct common misconceptions that cause long-run deployments to fail after temperature rise or connector aging.
  • Choose class using a decision tree based on power, reach, and thermal constraints.

What a class actually means (engineering view)

  • PD-side guarantee: the class is meaningful only when expressed as VPD and PPD envelopes under stated assumptions.
  • Assumption set: the guarantee depends on Rloop (cable + connectors + protection + copper), the load profile (average, peak, inrush), and the limit policy (OCP/OTP/UVLO behavior and retry rules).
  • Failure mode matters: exceeding the assumption set should lead to a controlled behavior (derate/limit/shutdown with bounded retries), not uncontrolled reset storms.

Common misconceptions and the first sanity check

Misconception 1: “Source power looks fine, so the class is fine.”

First check: verify Vtap-PD under worst-case load step and temperature; confirm VPD,min ≥ Vmin + X.

Misconception 2: “Average power is enough for sizing.”

First check: capture Ipeak at Itap-SRC; confirm inrush and load steps do not trip OCP or collapse Vpd during the transient window.

Misconception 3: “Cable length is the only reach variable.”

First check: test hot/cold and connector swaps; a small contact resistance drift can behave like “extra meters” and move the system across UVLO/thermal thresholds.

Misconception 4: “Higher class always improves stability.”

First check: confirm thermal coupling: higher delivered power can increase I²R heating, increase Rloop with temperature, and reduce Vpd margin unless derating and compensation are disciplined.

How to choose Class A/B/C (three dominant constraints)

  1. Reach-limited: long cable + connector resistance dominates. Focus on Rloop control and Vpd margin under worst-case temperature.
  2. Load-step limited: inrush and peak current dominate. Focus on limit policy and transient behavior (no OCP/UVLO ping-pong).
  3. Thermal-limited: enclosure and ambient dominate. Focus on derating hooks and hotspot telemetry; avoid thermal runaway loops (heat → resistance → drop → resets).

Deliverable: class mapping table (scenario → constraint → must-verify)

Class Target scenario Dominant constraint Must-verify (length × load × temp) Common failure symptom
A Low-power long-run sensors where voltage margin is the key risk. Reach-limited Vtap-PD margin at worst-case length; hot/cold sweep; connector swap sensitivity. Intermittent resets at high temperature; “works on bench, fails in enclosure.”
B Moderate power and mixed transients; some headroom needed for peaks. Load-step limited Inrush capture (Itap-SRC); OCP/UVLO event counters; repeatability across Y cycles. Reset storms after power-up; random dropouts when load toggles.
C Higher delivered power where thermal and derating policy become critical. Thermal-limited Hotspot Ttap-HOT; derating ladder validation; “heat-soak then step-load” tests. Stable cold start but fails after minutes; derating triggers and service complaints.

Selection principle: treat class as a PD-side guarantee under assumptions. If assumptions are unknown, prioritize measuring Rloop, capturing inrush, and validating thermal derating before committing to a class.

Class A/B/C Decision Tree (Power vs Reach) Requirements Vmin · Load Profile · Cable/Connector · Ambient/Enclosure Reach-limited Distance Rloop Vpd Margin Load-step limited Power Inrush Limit Policy Thermal-limited Temperature Derating Hotspots Recommended Class Region A B C Validate assumptions first
Diagram goal: pick class based on the dominant constraint (reach, transients, or thermal) and treat the result as a PD-side guarantee under assumptions.

H2-4 · Power Budget Model (Cable R, Vdrop, PD Min)

What this section enables

  • Convert “long-run failures” into a budget that can be calculated, reviewed, and verified.
  • Model the full loop resistance Rloop and compute Vdrop = I × Rloop.
  • Include temperature as a first-class budget term, not a post-mortem excuse.
  • Treat PD minimum voltage Vmin and UVLO behavior as part of stability, not an afterthought.

Core model (use worst-case current and worst-case temperature)

Vdrop = I × Rloop

Rloop must include cable conductors, connectors/contact resistance, protection path contribution, and PCB copper drop. Evaluate I at the relevant worst case (peak, inrush, or sustained depending on the failure mode).

Temperature term (budget it explicitly)

Cable and contact resistance increase with heat; budget a hot-case Rloop and verify it using steady-state soak. Treat temperature rise as a driver that shrinks Vpd margin and can trigger UVLO/derating loops.

PD minimum voltage and UVLO behavior (stability definition)

Vmin is not “just a number.” UVLO thresholds and recovery behavior can interact with inrush, retries, and thermal rise. Stability requires VPD,min ≥ Vmin + X under worst-case length, temperature, and load step, with bounded retry behavior (no reboot storms).

Deliverable: Power Budget table (Term / Nom / Worst / Margin / How to measure)

Term Nom Worst Margin How to measure
Cable conductor R R@25°C (X Ω) R@hot (X Ω) X% Measure loop resistance end-to-end; validate hot soak drift.
Connector/contact R X mΩ X mΩ (aging + hot) X mΩ Swap connectors; log ΔV at fixed I; identify hotspot Ttap.
Protection path drop X V @ I X V @ Ipeak X V Compare Vtap-SRC vs Vtap-IF across load steps and surge conditions.
PCB copper drop X mV X mV (hot) X mV Probe from injection node to connector pins; validate at Ipeak.
PD margin vs Vmin Vpd − Vmin = X Vpd_min − Vmin = X ≥ X V Measure Vtap-PD during worst-case load step and hot soak; log UVLO events.

Budget discipline: if Vpd margin is short, identify the dominant term (cable, connector, protection, copper) and select the knob (better cable/connector, compensation, or derating) before tuning anything else.

Voltage Drop Budget Along the Pair Vsrc Vpd (Nom) Vpd (Worst) Cable R Connector R Protection PCB Drop Vmin + margin Nom Worst (hot + peak)
Diagram goal: visualize how each resistance term consumes PD-side voltage margin and ensure worst-case Vpd stays above Vmin + margin.

H2-5 · Line-Loss Compensation (Static/Dynamic + Temp)

What this section enables

  • Explain why the same cable and load can be stable in winter but fail in summer: Rloop and protection policies are drifting with temperature.
  • Build a compensation strategy that closes the gap without triggering oscillation, overshoot, or thermal runaway.
  • Define guardrails so compensation never violates PD safety, OCP/OTP, or UVLO stability.

Root cause chain (field pattern)

  • Temperature rises → Rloop increases → Vdrop increases → Vpd margin shrinks.
  • Margin shrinks → UVLO/OCP policies start to interact with load steps → retry bursts and resets appear.
  • Blind “voltage lift” can worsen heating: higher delivered power can increase I²R loss and accelerate the thermal loop.

Compensation is a closed-loop control problem: Sense → Decide → Actuate → Limit → Prove.

Static compensation (pre-set by cable assumptions)

  • Approach: pre-configure Vsrc setpoint or P/I ceilings based on length/loop resistance targets.
  • Works best when: cable type and connector quality are controlled; load profile is stable.
  • Risks: real-field variance (contact resistance drift, temperature rise, aging) can invalidate assumptions and erase PD margin.
  • Validation: verify Vpd_min ≥ Vmin + X under worst-case length, temperature, and load step.

Dynamic compensation (feedback-based, but must be stabilized)

  • Approach: regulate using Vsense/Isense to maintain a PD-side envelope (or an injected-node target).
  • Key design point: sense placement determines what is actually corrected (source-only sensing can miss connector drift).
  • Major risks: oscillation (loop instability) and overshoot (transient stress and heat acceleration).
  • Guardrails: slope limiting, integral clamp, and hard limiters (OCP/OTP/UVLO) must dominate during faults.

Stability proof checklist

  • Step-load test: verify no persistent oscillation and bounded settling time.
  • Overshoot limit: ensure Vpd or injected node does not exceed X during fast transients.
  • Protection interaction: confirm OCP/UVLO do not ping-pong under repetitive events.

Temperature-aware compensation (avoid “compensate → heat → fail” loops)

  • Approach: incorporate Tsense into control so hot conditions reduce allowable P/I targets or slow the response.
  • Goal: keep compensation inside a thermal-safe operating region rather than chasing voltage at any cost.
  • Policy example: apply a temperature ladder to Pout/Imax targets; maintain clear hysteresis to avoid hunting near thresholds.

Protection coordination (hard and soft boundaries)

  • Hard limits: never exceed PD absolute ratings and thermal limits; keep OCP/OTP dominant under faults.
  • Soft limits: near boundaries, reduce target, apply slope limit, and enforce retry backoff to prevent storms.
  • Pass definition: Vpd_min ≥ Vmin + X, overshoot ≤ X, protection events ≤ X per hour, and recovery is bounded.

Deliverable: compensation strategy comparison (Static vs Dynamic vs Temp-aware)

Method What it controls Required sensing Key risks Guardrails How to validate
Static Vsrc setpoint or P/I ceilings Minimal (Vsense at source) Assumption drift (temp/aging), missed connector R Conservative margins, fixed ceilings Worst-case length × hot soak × load step
Dynamic PD-side envelope via feedback Vsense + Isense (placement critical) Oscillation, overshoot, protection ping-pong Slope limit, integral clamp, hard limiters Step-load stability + overshoot bound + event counters
Temp-aware Targets adapt with Tsense Tsense + (Vsense/Isense) Thermal hunting near thresholds, slow recovery if mis-tuned Temperature ladder + hysteresis + backoff policy Hot soak + repeated transients + threshold repeatability

Strategy selection rule: if the field variance is high (connectors, temperature, unknown loads), dynamic or temp-aware policies typically outperform static presets—but only when stability and limit coordination are proven.

Compensation Loop: Sense → Decide → Limit Sense Vsense Voltage tap Isense Current tap Tsense Thermal tap Controller / Policy Slope limit Integral clamp Output Adjust V / P / I Limiters OCP · OTP · UVLO Feedback Prove stability
Diagram goal: show compensation as a controlled loop that must be stabilized and bounded by OCP/OTP/UVLO policies.

H2-6 · Thermal Management & Derating (PD + Cable Heating)

What this section enables

  • Prevent the most common field failure: “works for minutes, then resets” caused by heat-driven derating and UVLO coupling.
  • Split heat sources and thermal paths so the dominant term can be controlled.
  • Provide a derating template (Tamb vs Pout) and a thermal test checklist with clear steady-state criteria.

Heat sources (split the ledger)

  • PD silicon and DC/DC: conversion losses, conduction losses, and hotspot concentration.
  • Cable I²R: heating rises with current and can elevate resistance, shrinking voltage margin.
  • Protection devices: energy absorption and bias losses can create localized heating.
  • Connectors/contacts: small resistance drift can become a dominant hotspot in sealed enclosures.

Thermal path (why mounting dominates)

  • Chain: Junction → Package → PCB → Enclosure → Ambient.
  • Mounting variance: sealed box, airflow duct, metal contact, and thermal pad strategy can change effective resistance dramatically.
  • Engineering requirement: derating must be defined against the worst-case thermal path, not the best-case bench setup.

Derating strategy (thresholds → ladder → backoff)

Thresholds

  • Define temperature gates (Tamb and Tsense) with hysteresis: T1/T2/T3 (placeholders).
  • Specify recovery behavior and required dwell time to avoid hunting near boundaries.

Power ladder

  • Use a step ladder for Pout or Imax: P1/P2/P3 and I1/I2/I3 (placeholders) for easy validation.
  • Ensure the ladder preserves Vpd margin and prevents repetitive UVLO triggers.

Retry throttling

  • Bound retries to prevent storms: max attempts, increasing backoff, and a stable fail-safe state if repeated trips occur.
  • Pass definition: limited events per hour (X) and bounded recovery time (X).

Heat–power–line-loss coupling (must be explicitly controlled)

  • Heat ↑ → Rloop ↑ → Vdrop ↑ → Vpd ↓.
  • Vpd ↓ → control/protection interactions increase retries and transient current → I²R ↑ → heat rises faster.
  • Therefore, compensation (H2-5) must be bounded by derating hooks (this section) to avoid runaway loops.

Deliverable: Derating template (Tamb vs Pout)

Tamb bin Tsense bin Pout max Imax Expected Vpd margin Action
T0–T1 S0–S1 P1 I1 ≥ X V Full power allowed
T1–T2 S1–S2 P2 I2 ≥ X V Derate step 1
T2–T3 S2–S3 P3 I3 ≥ X V Derate step 2 / throttle

Deliverable: thermal test checklist (taps, steady-state, repeatability)

  • Taps: Ttap-PD (PDIC/DC-DC hotspot), Ttap-CONN (connector hotspot), Ttap-CBL (cable representative point), plus Vtap-PD and Itap-SRC.
  • Steady-state criteria: |dT/dt| ≤ X °C/min for Y minutes; power within ±X% during the window.
  • Repeatability: repeat N cycles; trip/recovery thresholds drift ≤ X; unit-to-unit variance ≤ X.
  • Pass criteria: derating transitions do not hunt; protection events ≤ X per hour; Vpd_min ≥ Vmin + X.
Thermal Path + Derating Hooks Heat Sources PDIC Hotspot DC/DC Loss Cable I²R Heating Protection Connector Thermal Path Junction Package PCB Enclosure Ambient Derating Hooks Tsense Power ladder Retry backoff Derate P1 P2 P3 T1/T2/T3
Diagram goal: split heat sources, show the thermal path to ambient, and place explicit derating hooks (Tsense, power ladder, retry backoff).

H2-7 · Protection & EMC Hooks (Low-C TVS, Surge Return, IS)

Engineering intent

  • Protection for PoDL is not “stronger is better”. It must balance SI impact, leakage/heat, and surge return control.
  • Surge current must be routed to the correct return target; otherwise systems become “more fragile” even if devices survive.
  • For hazardous/process deployments, ensure energy limiting and isolation principles are explicitly enforced (no clause-by-clause standards expansion here).

Low-C TVS selection logic (PoDL-specific framing)

  • Differential vs common-mode effect: even “low C” loads the pair and can reshape high-frequency return behavior. Treat this as a risk flag to be validated, not assumed safe.
  • Leakage and temperature: hot leakage can become a steady power term, creating TVS/connector hotspots that steal PoDL margin.
  • Pass framing: leakage-driven loss ≤ X, hotspot rise ≤ ΔT(X), and post-event behavior does not induce resets or link flaps.

Surge return path (must be drawn and enforced)

  • Rule 1: surge/ESD current must flow through a short, direct path to the intended return target (shield/chassis/defined reference).
  • Rule 2: keep surge return out of “quiet” reference areas used by sensing and control decisions (Vsense/Isense references).
  • Rule 3: placement defines the path—protection far from the connector increases the chance of current entering board copper and creating ground bounce.

Field signature that indicates a return-path error

  • Protection devices survive, but the system becomes easier to reset or drop link after events.
  • Intermittent UVLO/OCP ping-pong appears only after surge/ESD campaigns.
  • Sensing readings show unexplained spikes during events (reference contamination).

Intrinsic safety (IS) / hazardous areas (principles, not standard clauses)

  • Energy limiting: enforce explicit ceilings for V/I/P so fault energy stays bounded.
  • Isolation and spacing: treat isolation and creepage/clearance as primary design constraints, not add-ons.
  • Fault containment: require that a single fault does not defeat energy limits or push temperatures beyond safe envelopes.

Deliverable: protection network checklist (placement, return, leakage, thermal)

Item What to verify How to check Pass criteria (placeholders)
Placement Protection close to connector, minimal trace inductance Layout review + event waveform capture Distance ≤ X, no board-internal detours
Return target Surge returns to shield/chassis/defined node (not quiet ref) Current path sketch + continuity/impedance sanity No ref contamination; stable sensing during events
Leakage (hot) Leakage-driven power term does not steal PoDL margin Hot soak measurement + current logging Extra loss ≤ X; Vpd_min ≥ Vmin + X
Thermal hotspot TVS/connector temperature stays bounded under load and events IR/TC probe + steady-state criteria ΔT ≤ X; no drift after event series
Post-event stability No “more fragile after test” behavior Counters + reboot logs + margin re-check Events ≤ X/hr; recovery ≤ X; margins unchanged
Protection + Return Path (Do / Don’t) DO DON’T Connector TVS / Clamp Pair to PD Sense ref PD / DC-DC Dirty zone Quiet zone Shield Surge return Connector TVS / Clamp Pair to PD Quiet GND Sense ref PD / DC-DC Surge detour Return crosses quiet ref
Use the Do/Don’t map to review protection placement and surge return routing. The goal is to keep event current out of sensing references and quiet ground regions.

H2-8 · Hardware Implementation Hooks (Sensing, Limits, Layout)

Engineering intent

  • Make PoDL implementation measurable and controllable: sensing placement must match compensation and derating policies.
  • Limiters and retry throttling must prevent reset storms and protection ping-pong.
  • Layout hooks must keep differential routing stable while maintaining intact return paths for surge and power currents.

Required sensing (Vsense / Isense / Tsense): placement and accuracy framing

  • Vsense: measure near the node that defines PD margin (avoid source-only sensing if connector and protection drops dominate).
  • Isense: capture line current to quantify I²R loss, enforce OCP, and support dynamic compensation.
  • Tsense: place at the dominant hotspot candidate (PD, connector, or TVS) so derating triggers correspond to real risk.

Naming convention (recommended)

Vtap-PD · Itap-SRC · Ttap-PD · Ttap-CONN · Ttap-TVS

Limiters and system behavior (avoid reset storms)

  • Limiters: OCP/OVP/OTP/UVLO must have clear priority and deterministic outcomes.
  • Soft-start: constrain inrush so startup does not immediately collide with OCP and collapse margin.
  • Retry throttling: enforce max attempts, increasing backoff, and a stable fail-safe mode to prevent repeated trips.
  • Pass framing: events ≤ X per hour, bounded recovery time ≤ X, and Vpd_min ≥ Vmin + X under worst-case conditions.

Layout hooks (PoDL-specific focus)

  • Connector → protection → pair corridor: keep protection adjacent to the interface to prevent event current from entering board copper.
  • Dirty vs quiet separation: confine high-current injection/return paths to a “dirty zone”; keep sensing references in a “quiet zone”.
  • Keep return intact: avoid plane cuts and detours that force return currents through sensitive regions.

Deliverable: bring-up required taps table (what/how/pass/first fix)

Tap name Purpose How to measure Pass criteria (placeholders) Failure signature First fix
Vtap-PD Validate PD margin and UVLO behavior Min/peak logging over load steps and events Vpd_min ≥ Vmin + X Reset storm, periodic drop, UVLO ping-pong Improve return path, tune limits, reduce overshoot
Itap-SRC Quantify I²R loss and enforce OCP correctness Peak capture at startup and step loads Ipeak ≤ X; OCP events ≤ X/hr OCP chatter, repeated trips Adjust soft-start, verify sensing reference, reroute current path
Ttap-PD Confirm hotspot and derating trigger alignment Hot soak + steady-state criteria window ΔT ≤ X; |dT/dt| ≤ X Runs then fails; thermal cycling instability Improve thermal path, apply power ladder, tune thresholds
Ttap-CONN Detect contact heating and drift risk Steady-state hotspot scan + repeatability ΔT ≤ X; no drift after events Only certain builds fail; heat localized near connector Improve return and connector selection, reduce current peaks
Ttap-TVS Confirm leakage/energy absorption is not creating a hotspot Hot soak + after-event re-check ΔT ≤ X; leakage loss ≤ X Post-test fragility, margin shrink over time Relocate protection, improve chassis return, refine limits
Placement Map: PD / Protection / Sense Dirty zone Quiet zone Connector TVS / Clamp Diff pair corridor PD front-end DC/DC Load sensor Vtap-PD Itap-SRC Ttap-PD Ttap-TVS Ttap-CONN Keep return intact
Use this placement map to keep protection and surge handling in the dirty zone, while preserving clean sensing references and stable control behavior in the quiet zone.

H2-9 · Control/Firmware & Telemetry (State, Logs, Black-Box)

Engineering intent

  • Intermittent field failures must be explainable: the system should prove why it derates, drops power, retries, and recovers.
  • Telemetry must bind physical quantities (V/I/T) to control outcomes (state, limiter flags, events) and configuration versions.
  • Black-box logs should be event-driven, compact, and aligned with common “seasonal / after-heat / batch-to-batch” symptoms.

Power state machine: explicit entry/exit evidence

Entry evidence (must be logged)

  • DERATE: Tsense ≥ X or Vtap-PD margin low for X time.
  • FAULT: UVLO/OCP/OTP/OVP event code and snapshot.
  • RECOVER: retry policy (backoff level, max attempts) and selected fallback mode.

Exit criteria (must be deterministic)

  • DERATE exit: temperature falls below threshold minus hysteresis X.
  • FAULT exit: stability window X + explicit clear conditions (policy-defined).
  • Anti-chatter: dwell time X to prevent repeated state toggling.

Telemetry must cover three layers (energy → causality → configuration)

Layer 1 · Physical quantities

Vtap-PD (min/avg/dip) · Itap-SRC (peak/avg) · Ttap-* (steady/dT/dt)

Layer 2 · Control evidence

State · Last event (UVLO/OCP/OTP/OVP) · Limiter flags · Retry count · Backoff level

Layer 3 · Config & versioning

Cable profile ID · Length profile ID · Comp algo version · Derate table ID · Firmware/config CRC

Black-box logs: event-driven, compact, correlation-ready

  • Triggers: UVLO/OCP/OTP/OVP, state transitions, retry bursts, fast V margin shrink.
  • Windows: pre/post X seconds with min/avg/max snapshots; log rate tiers by importance.
  • Correlation keys: ambient proxy (if available), power mode, cable profile, and config versions.

Deliverable: telemetry field dictionary (Field / Unit / Rate / Trigger / Diagnose)

Field Unit Rate Trigger Diagnose
Vtap-PD_min V Fast stat State change, UVLO Margin collapse, line loss, UVLO cause
Itap-SRC_peak A Fast stat Startup, OCP Inrush/OCP trip, load steps
Ttap-PD_steady °C Slow Derate, OTP Thermal runaway risk, derate alignment
State enum On change All events Causal chain of behavior
LastEvent enum On change Fault/derate Why the transition happened
LimiterFlags bitset On change Derate/OCP/OTP Which limiter constrained power
RetryCount count On fault Retry bursts Reset storm detection
CableProfileID id On boot Any anomaly Batch-to-batch mismatch explanation
ConfigCRC hex On boot Any anomaly Prove config identity on-site
PoDL Power State Machine + Events OFF DETECT POWER_ON REGULATE DERATE FAULT RECOVER V / I / T OTP UVLO OCP Retry Backoff OVP
Keep state transitions explainable by logging entry evidence (V/I/T snapshots + event code) and enforcing deterministic exit criteria (hysteresis and dwell time).

H2-10 · Verification Plan (Bring-up → Production Gates)

Engineering intent

  • Provide a repeatable route that eliminates PoDL risks in the lab and scales to production sampling.
  • Use ladders for Length × Load × Temp, with fixed metric definitions and placeholder pass thresholds X.
  • Bind verification to telemetry requirements so every failure is diagnosable, not just observable.

Bring-up gate: three ladders with fixed pass framing

Length ladder

Short → Mid → Long → Max. Track Vtap-PD_min, event counts, retry bursts, and stable runtime ≥ X.

Load ladder

Idle → Light → Typical → Peak/Stress. Track Itap-SRC_peak, V dips, OCP events, recovery time ≤ X.

Temp ladder

Cold → Ambient → Hot. Validate derate monotonicity, no chatter, and post-heat margins unchanged.

Production gate: sampling subset + traceability requirements

  • Sampling subset: representative short/long lengths, typical/heavy loads, and a thermal offset spot check.
  • Traceability: log cable profile ID, compensation version, derate ID, and config CRC for every unit under test.
  • Repair criteria: event rate > X, V margin < X, hotspot ΔT > X, or recovery time > X.

Common pitfalls: fast signature and first fix

Light-load OK, full-load fails

Check Itap peak, connector/TVS heating drift, and Vtap-PD dips. First fix: soft-start, limiter hysteresis, return/placement.

Room temp OK, hot causes resets

Verify derate thresholds and hysteresis, and watch UVLO bursts during derate. First fix: derate ladder, dwell time, retry backoff.

Comp loop oscillation

Look for state chatter and alternating OCP/UVLO. First fix: limit compensation slope, adjust filtering, enforce dwell time.

Deliverable: verification matrix template (Condition / Steps / Metrics / Pass / Notes)

Condition Steps Metrics Pass criteria (X) Notes
Length × Load @ Ambient Run grid points; dwell ≥ X per point Vtap-PD_min, Itap_peak, events, retries V margin ≥ X; events ≤ X; recovery ≤ X Bind to config CRC and profile IDs
Temp ladder @ Long line Cold/Amb/Hot, plus post-heat re-check Ttap steady, derate steps, chatter count No chatter; ΔT ≤ X; margins unchanged Track UVLO bursts during derate
Production sampling subset Short+Long × Typical+Heavy + thermal offset Key V/I/T stats + event rate Event rate ≤ X; recovery ≤ X; hotspot ≤ X Require config identity for traceability
Verification Ladder (Length × Load × Temp) Load → Length ↓ Idle Typical Peak Stress Short Mid Long Max Cold Amb Hot Cold Amb Hot Cold Amb Hot Cold Amb Hot Production sampling subset Record profile IDs + config CRC for traceability
Use the full grid for bring-up coverage, then select a stable subset for production sampling while enforcing telemetry traceability.

H2-11 · Engineering Checklist (Design → Bring-up → Production)

Convert PoDL risks into execution-ready gates. Every checklist item includes an owner, measurable evidence, and a numeric pass threshold (X) to prevent “it seemed fine” failures on long-run sensors.
Design Gate — lock the budget & hooks
Budget sheet is complete (Nom/Worst/Margin)
Owner: HW Lead · Evidence: signed budget table (Rloop, Vdrop, VPDmin, ΔT) · Pass: VPD(min) ≥ X V at worst Rloop & Tamb
Sense taps are physically placed (V/I/T)
Owner: HW + Test · Evidence: schematic + PCB locations + testpoint IDs · Pass: Vsense error ≤ X% , Isense error ≤ X% , Tsense within X °C
Protection return path is drawn and verified
Owner: HW + EMC · Evidence: “return-path map” + layout screenshots · Pass: surge/ESD return stays on intended path (no plane-cut detours)
Limits are defined (OCP/OVP/OTP + retry throttle)
Owner: HW + FW · Evidence: threshold table + state chart · Pass: no restart storm; retry rate ≤ X / hour under faults
Derating policy is explicit (Tamb → Pout)
Owner: ME + HW · Evidence: derating curve template + thermal assumptions · Pass: ΔT steady-state ≤ X °C at worst-case load/length
Bring-up Gate — prove stability on ladders
Length × Load × Temp ladder is executed
Owner: Test · Evidence: matrix log + raw telemetry traces · Pass: VPD never dips below X V; no brownout loops
Compensation loop is stable (no oscillation/overshoot)
Owner: HW + FW · Evidence: step-load response + limit-event captures · Pass: Vout overshoot ≤ X%; settling ≤ X ms; no limit chatter
Protection triggers are correlated to logs
Owner: FW + Test · Evidence: event timeline (UVLO/OCP/OTP/Retry) · Pass: every shutdown has a unique code + timestamp + context
Thermal points are repeatable (fixture-defined)
Owner: ME + Test · Evidence: IR images + thermocouple map · Pass: hotspot location stable; ΔT variance ≤ X °C across repeats
Production Gate — freeze versions & field-forensics
Golden cable/fixture and calibration are locked
Owner: MFG + QA · Evidence: fixture ID + calibration record · Pass: station-to-station deltas within X% for V/I/T readings
Screen tests cover worst-case corners
Owner: QA · Evidence: shortened ladder + pass log · Pass: no brownout / no retry storm in corner set
Field black-box is enabled by default
Owner: FW · Evidence: log schema + retention policy · Pass: last N events retained; includes V/I/T + state + class cfg version
Diagram — Three-Gate Checklist Flow
Design Gate Budget locked V/I/T taps placed Limits defined Return path verified Bring-up Gate Length×Load×Temp Loop stability Event correlation Thermal repeatability Prod Gate Fixture lock Screens Black-box Version Each item must produce evidence and a numeric pass threshold (X) to avoid ambiguous sign-off.

H2-12 · Applications & IC Selection Logic (Long-run Sensors)

The selection goal is not “max power”. The goal is a guaranteed powered-device operating point: VPD ≥ Vmin, P ≤ budget, ΔT ≤ limit, and controlled recovery (no restart storms) across the worst cable and temperature corners.
Typical long-run SPE + PoDL use cases
  • Process automation sensors on long cable runs (power + data on one balanced pair)
  • Remote I/O blocks with constrained wiring and enclosure thermal limits
  • Low-power edge nodes requiring deterministic power behavior and field diagnostics
Selection funnel (requirements → architecture → must-have hooks)
  1. Lock the PD operating point: VPD(min), steady Pload, startup inrush, and UV behavior.
  2. Budget the worst cable path: Rloop (wire + connectors + protection + PCB copper) at hot temperature.
  3. Decide compensation + limits: static/dynamic/temp-aware strategy with OCP/OTP/derating and retry throttling.
  4. Select implementable IC blocks: PoDL PSE/PD control, power tree, sensing/telemetry, and SPE PHY.
Application → Constraints → Must-have hooks → Example IC blocks (MPNs)
Scenario Key constraints Must-have hooks MPN examples
24 V class (long-run sensors) Hot cable resistance, enclosure thermal, controlled brownout recovery Vsense/Isense/Tsense, derating table, OCP/OTP, event logs PSE-side examples: MSPM0G1107 + DP83TD510E, LMR36006 (6.5 V rail), LM74700-Q1 (reverse)
PD-side examples: TPS2660 (eFuse), TLVM13630, TPS62825A, TPS61023, TVS3300, CSD19538Q2, DP83TD510E
24/54 V “controllerized” SPoE path Faster integration, standardized class control, telemetry, multi-port scaling PSE telemetry + per-port protection, SCCP handling, PD UV behavior + sleep/wake PSE: LTC4296-1 (5-port SPoE PSE controller)
PD: LTC9111 (SPoE PD controller)
Data example: ADIN1100 (10BASE-T1L PHY)
Intrinsic-safety leaning (energy-limited) Energy limitation, leakage control, predictable fault behavior Strict current limiting, thermal cutback, explicit fault logs, conservative recovery policy Use an eFuse/current-limit stage and log-centric firmware hooks (example eFuse: TPS2660).
Note: “MPN examples” are implementation references, not an exhaustive shortlist. Always validate against the selected PoDL class, cable worst-case, and enclosure thermal limits.
Concrete MPN examples (by function bucket)
PoDL PSE / control (digital + analog)
MSPM0G1107 (PSE control MCU), plus per-port analog blocks in the TI PoDL approach; controllerized option: LTC4296-1 (5-port SPoE PSE).
PoDL PD / control
MSP430FR2476 (PD SCCP handling example), TPS2660 (PD-side protection/eFuse), controllerized option: LTC9111 (SPoE PD).
Power tree building blocks (examples from PoDL reference designs)
PSE board rails: LMR36006 (PoDL rail), LM74700-Q1 (reverse protection), TLVM13630, TPS62825, TLV62568A, TPS2553.
PD board rails: TLVM13630, TPS62825A, TPS61023, LM74700-Q1.
Protection / clamps (examples)
TVS3300 (interface protection example), CSD19538Q2 (power MOSFET example).
SPE PHY / data path (kept minimal, only as architecture context)
DP83TD510E (10BASE-T1L PHY example); ADIN1100 (10BASE-T1L PHY example).
Diagram — Selection Funnel: Requirements → Architecture → Must-have Hooks
Requirements VPDmin Pbudget Length Tamb IS? Architecture PSE + CDN Cable CDN + PD Must-have hooks Vsense Isense Tsense OCP / OTP / Retry Telemetry + Logs SCCP / class config Derating (Tamb→P)

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H2-13 · FAQs (PoDL for SPE) — Long-run Troubleshooting

This section only closes long-tail troubleshooting within this page scope (class, line-loss compensation, thermal, long-run sensors). Each answer is fixed to four lines: Likely cause / Quick check / Fix / Pass criteria (X).
Same class, short cable is stable but long cable drops — cable R or compensation mismatch?

Likely cause: Worst-case Rloop (wire + connectors + protection + copper) exceeds the class margin, or the compensation profile does not match the actual cable gauge/length.

Quick check: Measure VPD at the PD input (Vtap) under max load; if VPD(min) < X V, also check if Isense hits OCP or power-limit at X A / X W.

Fix: Update Rloop(worst) with hot temperature and connector contact R, then re-select class/profile; cap Pout for long-run, or switch to a temp-aware profile with explicit limits.

Pass criteria: Longest cable + hottest corner + max load: VPD ≥ X V for Y minutes, and UVLO events = 0.

Works at room temp, but becomes a restart storm at high temp — PD heating or cable R(T) → UVLO?

Likely cause: Hot cable resistance raises Vdrop, pushing VPD below UVLO; or PD/DC-DC thermal derating triggers power cycling and aggressive auto-retry.

Quick check: Log VPD(min), Tsense/hotspot, and event timeline; confirm whether failures correlate with UVLO (VPD < X V) or OTP (T > X °C).

Fix: Tighten derating (Tamb→Pout) and add retry backoff; reduce steady load or inrush; recalibrate compensation for hot Rloop and enforce a minimum VPD margin.

Pass criteria: At Tamb = X °C, VPD ≥ X V and Retry_rate ≤ X / hour for Y hours (no restart storms).

Enabling compensation makes it less stable — loop oscillation/overshoot or limits too tight?

Likely cause: Closed-loop compensation induces oscillation or overshoot; or OCP/power-limit thresholds cause limit “chatter” under dynamic load.

Quick check: Capture Vout/VPD and Isense during a load step; flag periodic limit toggling ≥ X times/min or overshoot > X% / settling > X ms.

Fix: Reduce loop gain / increase filter time constants; widen OCP hysteresis to X and add a minimum dwell time; enforce backoff after repeated limit hits.

Pass criteria: Step-load tests: overshoot ≤ X%, no limit chatter, and event_count(OCP) ≤ X in Y minutes.

Cable-length profile changed, field power is abnormal — budget definition or missing log fields?

Likely cause: Rloop assumptions changed but the budget table/limits were not updated; or the deployed configuration version is unknown (no traceability).

Quick check: Compare “profile ID / config CRC” in logs vs expected; verify VPD(min), I-limit hits, and class/profile selection at boot.

Fix: Freeze and version-lock: class + length profile + derating table; add mandatory log fields (profile ID, CRC, limits) and block power-up on mismatch.

Pass criteria: 100% of field logs include profile ID + CRC; deployed profile matches golden (CRC match = X) and metrics stay within spec.

No-load is fine, but it drops when load is applied — soft-start/inrush or OCP trigger?

Likely cause: Inrush peak (DC/DC start or bulk cap) trips OCP, or VPD dips below UVLO during ramp due to cable Vdrop at peak current.

Quick check: Capture VPD and Isense during load enable; check if Ipeak > X A or if VPD dips below X V for > X ms before reset.

Fix: Add/adjust soft-start (limit dv/dt), pre-charge or stage the load, raise OCP blanking to X ms, and enforce retry backoff.

Pass criteria: Load step to X W: VPD ≥ X V throughout ramp; event_count(OCP+UVLO) = 0 over Y cycles.

Stable in winter, but more BER/power drops in summer — R(T) → Vdrop → undervoltage chain?

Likely cause: Cable and connector resistance increases at higher temperature, shrinking VPD margin; thermal derating reduces available power right when Vdrop rises.

Quick check: Compare Rloop (measured) or inferred Vdrop at two temperatures; confirm VPD(min) at summer Tamb is still ≥ X V under the same load.

Fix: Treat temperature as a first-class budget term: use hot Rloop(worst), reduce steady load, tighten derating, and ensure compensation does not push thermal runaway.

Pass criteria: Across Tamb range (X to X °C), VPD margin ≥ X V and no UVLO events for Y hours at representative load.

Protection part change increases temperature rise — leakage/clamp power or return-path stress?

Likely cause: Higher leakage or higher clamp dissipation under normal bias, or altered return path causing unintended current through protective elements.

Quick check: Measure protection device DC leakage at operating voltage and its case temperature; verify current return path is not forced through the clamp network.

Fix: Re-qualify the replacement for leakage vs temperature; adjust placement/return routing; apply a derating rule if clamp dissipation can exceed X W in worst corner.

Pass criteria: Protection case ΔT ≤ X °C at Vop and worst Tamb; no added UVLO/OTP events over Y hours.

One sensor batch drops power more easily — startup inrush spike or PD UVLO threshold variation?

Likely cause: Higher inrush (capacitor/boot behavior) or slightly higher UVLO threshold reduces margin on long runs, turning borderline into failures.

Quick check: Compare Ipeak, VPD dip depth, and UVLO entry between “good” and “bad” units over the same cable; look for VPD(min) < X V or Ipeak > X A.

Fix: Increase soft-start control, reduce bulk input capacitance or stage enable; widen allowable UV margin by lowering steady load or tightening derating/limits.

Pass criteria: Across batch extremes, Ipeak ≤ X A and VPD ≥ X V during startup; failure rate ≤ X% over Y cycles.

Long cable but low power still unstable — connector contact R/oxidation or measurement definition?

Likely cause: Intermittent contact resistance (oxidation/loose crimps) creates random Vdrop; or the “length” configuration does not reflect actual Rloop.

Quick check: Measure connector ΔV under load and look for step-like changes; compare inferred Rloop = Vdrop/I to expected; flag ΔR > X mΩ events.

Fix: Improve connector specification/process, add contact-R screening, and tie compensation to measured/inferred Rloop rather than nominal length only.

Pass criteria: Under steady load, inferred Rloop stays within ±X% and VPD margin ≥ X V for Y hours with zero unexplained resets.

Field intermittent, cannot reproduce on bench — which 3 black-box fields to add first?

Likely cause: A missing observability gap hides the true trigger (temp corner, inrush pattern, or limit chatter) and bench tests do not hit the same corner.

Quick check: Add and verify the first three fields: VPD(min) in a rolling window, Tsense/hotspot, and Retry/event counters with timestamps.

Fix: Log pre/post context for every UVLO/OCP/OTP (X seconds before/after), plus profile ID/CRC; then reproduce using the same corner (length/load/temp) indicated by logs.

Pass criteria: ≥ X% of field failures have a single dominant trigger identified within Y days, based on the new fields.

After derating, the application misbehaves — derating steps vs load curve mismatch?

Likely cause: Derating staircase reduces available power below the application’s minimum operating point, causing functional brownouts even if the device stays “on”.

Quick check: Correlate derating level vs application current demand; verify whether functional failures start when Pavailable < X W or VPD(min) < X V under load bursts.

Fix: Align derating steps to the application load curve (reserve headroom), add a “minimum service level” mode, and rate-limit transitions between derating levels.

Pass criteria: At Tamb = X °C, application meets KPIs while ΔT ≤ X °C; derating transitions ≤ X/hour; no functional brownouts for Y hours.

Multi-node shared power policy causes mutual interference — current limiting or retry throttling?

Likely cause: One node hitting OCP/UVLO triggers a supply dip or policy reallocation, causing cascaded resets; aggressive auto-retry synchronizes failures across nodes.

Quick check: Compare per-node event timelines; if resets cluster within X seconds, check shared limit thresholds and whether backoff is disabled (Retry_rate spikes).

Fix: Add per-port isolation (policy separation), enforce randomized/graded backoff, and cap simultaneous restarts; set a hard budget per node with a minimum VPD margin.

Pass criteria: Under worst-case combined load, no clustered resets; Retry_rate ≤ X/hour per node and VPD ≥ X V for Y hours.

Tip: keep the same measurement taps and pass thresholds (X) across lab, production, and field logs to avoid “metrics mismatch” debugging loops.