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RJ45 & Magnetics Placement: Layout, Return Plane, PoE Paths

RJ45 & Magnetics Placement: Layout, Return Plane, PoE Paths

← Back to: Industrial Ethernet & TSN

Core idea
RJ45 + magnetics placement is about controlling boundaries and return paths: keep the PHY↔magnetics↔RJ45 corridor short and symmetric, keep the reference plane continuous, and force ESD/PoE currents to return to the chassis at the connector. Do that, and CRC/link flaps/EMI failures drop from “mystery problems” to measurable checks with clear pass criteria.

What “Placement” Means for RJ45 + Magnetics

Card A · Key outcomes Turn “placement” into auditable checks (distance / domains / return plane / current paths)

Placement is a boundary-control problem where three flows must be separated and kept predictable: MDI differential signal, PoE DC power, and ESD/surge return. A “good-looking layout” is not enough—success is measured by short, symmetric MDI, a continuous return plane, and power/return loops that avoid sensitive PHY/clock areas.

The 3-path model (audit lens)
  • Path-1: PHY ↔ Magnetics (MDI sensitive segment)
    Target: shortest + most symmetric differential routing with a solid reference plane.
    Audit: equal via count, no stubs/branches, no plane cuts/voids under the pair.
  • Path-2: Magnetics ↔ RJ45 (edge + shielding boundary)
    Target: keep the “field boundary” near the board edge; avoid dragging coupling sources into the board.
    Audit: RJ45 and magnetics form a tight edge cluster; routing avoids switch nodes/clock regions.
  • Path-3: RJ45 ↔ Chassis (shield + ESD/surge return)
    Target: ESD/surge energy returns to chassis through the shortest, lowest-inductance path.
    Audit: return loop area minimized; no return path crossing PHY/clock/power-sensitive zones.
What placement failure typically looks like (field-observable)
  • CRC spikes / drops that correlate with cable, enclosure, or grounding changes.
  • Link flaps during load events (PoE power steps, surge exposure, or thermal rise).
  • EMI peaks that shift with shield bonding or chassis contact quality.
  • Post-ESD “fragile” behavior: passes once, then becomes error-prone without hard failure.
  • PoE hot spots / voltage drop near connector or center-tap routing constraints.
Page deliverables (what this subpage provides)
  • Placement rules checklist (copy-and-audit ready, with X-threshold placeholders).
  • Anti-pattern library (plane cut under MDI, floating shield, power loop crossing sensitive zones).
  • Validation matrix (what to measure, what “pass” looks like, and which placement defect it points to).
Card B · Failure symptoms map Quick routing: symptoms → likely placement area (chapter anchors appear later in the full page)
Fast triage (no deep dive here)
  • CRC spikes → first audit MDI length/symmetry + return-plane continuity.
  • EMI fails only in enclosure → first audit shield-to-chassis path and loop area.
  • Post-ESD fragile → first audit ESD/surge return path and protection placement side.
  • PoE hot/drop → first audit PoE current loop avoiding PHY/clock zones.
Board-review micro-checklist (30 seconds)
  • RJ45 + magnetics cluster at board edge, not deep inside the board.
  • MDI pair is short, straight, symmetric with no plane cuts underneath.
  • Shield/chassis path is defined (no floating shield, no random multi-point loops).
  • PoE current loop avoids PHY/clock region; copper/vias sized for thermal + drop limits (X).
Return plane (keep continuous) PHY MDI source MAGNETICS isolation RJ45 shield + PoE Chassis Keep MDI short & symmetric · Avoid plane cuts PoE current path ESD/Surge → chassis return Keep PoE/Surge out

Top Failure Modes Caused by Bad Placement

Routing map (symptom → placement cause) Each item stays within placement/return-path scope (no protocol deep dives)

Bad placement failures are repeatable patterns. The fastest way to avoid chasing the wrong layer is to classify the symptom, check the placement root cause, and validate using a short “quick check”. Repairs are described later; this chapter only defines what the failure looks like and which placement defect it most often points to.

SI class Reflection / asymmetry / common-mode conversion
What it looks like
  • CRC or error counters increase with cable length or connector variation.
  • Errors appear near throughput peaks; stability returns when link conditions change.
  • Small physical changes (enclosure, hand proximity, ground contact) shift behavior.
Likely placement root causes
  • MDI pair too long, too many layer changes, or unequal via count.
  • Reference plane discontinuity (split/cut/void) under MDI causing return detour.
  • Asymmetric placement around magnetics pins converting differential energy into common-mode.
Quick checks
  • Inspect: MDI pair symmetry, via parity, and any plane cuts under the route.
  • Compare: error rate with enclosure open vs closed; strong sensitivity hints common-mode coupling.
  • Pass criteria: MDI via difference = 0; no split/void under route; stub length < X.
EMC class Return detour / plane gaps / floating shield
What it looks like
  • Radiated peaks strongly depend on shield bonding or chassis contact.
  • EMI pre-scan fails at stable frequencies that match noise sources (clock/power harmonics).
  • Behavior improves by touching chassis/adding temporary bonding, indicating uncontrolled return paths.
Likely placement root causes
  • Return loop area enlarged by plane splits/cuts near connector/magnetics region.
  • Shield can “float” or connect unpredictably, turning the cable + enclosure into a radiator.
  • Noisy regions (switch node/clock) placed too close to the MDI boundary cluster.
Quick checks
  • Inspect: any plane gaps under/around the edge cluster and the shield pads.
  • Compare: EMI level with alternative chassis contact points; large deltas imply return-path issues.
  • Pass criteria: shield/chassis path defined; no plane cuts under MDI; keep noisy zones outside a keepout of X.
ESD/Surge class Return path through PHY/clock region (latent fragility)
What it looks like
  • ESD test may “pass” once, then the link becomes more fragile later.
  • Drops occur without obvious hardware damage; resets are sporadic or temperature-dependent.
  • Errors correlate with touch points on shield/chassis, implying uncontrolled return injection.
Likely placement root causes
  • ESD/surge return path has large inductance and crosses PHY/clock/power-sensitive regions.
  • Protection return “loops” are big (long path to chassis), forcing energy into the board.
  • Shield bonding is inconsistent, allowing discharge current to find unintended routes.
Quick checks
  • Inspect: discharge return to chassis is shortest and does not run under PHY/clock region.
  • Compare: pre/post-ESD error counters; latent fragility often shows as a rising baseline.
  • Pass criteria: return loop area minimized; protection-to-chassis path length < X.
PoE class Power loop crossing sensitive zones / copper bottlenecks
What it looks like
  • Link drops during power steps or load transients; temperature rise makes failures more frequent.
  • Connector-area hot spot; voltage drop is measurable across the power path.
  • EMI changes when PoE is enabled (power loop coupling into MDI boundary).
Likely placement root causes
  • PoE current loop runs through PHY/clock keepout, injecting noise via ground bounce or coupling.
  • Copper/vias are undersized, creating thermal and drop bottlenecks near the edge cluster.
  • Power/return paths share space with MDI routes, reducing isolation between flows.
Quick checks
  • Thermal scan: confirm hot spots align with planned copper/via spreading, not a narrow choke.
  • Voltage drop: measure under full load; unexpected drop implies routing bottlenecks.
  • Pass criteria: loop avoids PHY/clock keepout; power trace width/via count meets X A and X °C rise limits.
Symptom → Placement Root Cause (routing map) Symptom groups SI CRC spikes Throughput dip Cable sensitive EMC Radiated peak Enclosure-only Bonding delta ESD/Surge Post-ESD fragile Soft resets Touch sensitive PoE Link drop on load Hot connector Drop (V) Placement root causes Return-plane cut Long / asym MDI Floating shield Power loop cross Bad return path to chassis (large loop) Use this map to avoid layer-chasing: classify symptom → inspect placement root cause → validate with quick checks.

Anatomy: PHY–Magnetics–RJ45 Partitioning

Core idea Partitioning = controlled domains + controlled return paths (not “just placement”)

Partitioning is the discipline of keeping three worlds from mixing: (1) PHY digital/clock, (2) MDI sensitive corridor, and (3) cable/shield/chassis return. Magnetics is the isolation + common-mode boundary; RJ45 shield bonding defines where EMI/ESD energy returns. A correct partition makes MDI return short + continuous, and keeps PoE/Surge return out of the PHY/clock domain.

Magnetics is more than a “signal part”
  • Isolation boundary: separates board reference/return from cable/chassis environment.
  • Common-mode boundary: determines whether common-mode energy exits to shield/chassis or couples into the board.
  • Placement consequence: moving magnetics “inward” often enlarges loop areas and increases EMC sensitivity.
Card A · Two archetypes Compare by placement/paths only (no selection deep dive)
Archetype A
Discrete magnetics + RJ45
  • Placement priority: PHY↔Magnetics corridor is shortest + symmetric; magnetics defines the boundary.
  • Typical pitfall: Magnetics↔RJ45 is stretched inward, enlarging near-field coupling and EMC sensitivity.
  • Keepout focus: keep noisy power/clock zones away from the MDI corridor and boundary cluster.
  • Fast review: edge cluster should look “compact”; no long routing between magnetics and connector.
Archetype B
MagJack (magnetics integrated in RJ45)
  • Placement priority: PHY↔MagJack corridor is kept short + symmetric; the boundary is naturally at the edge.
  • Typical pitfall: longer PHY↔connector routes cross domain boundaries or plane splits.
  • Keepout focus: stronger mechanical/shield constraints near the connector demand a clean chassis return corridor.
  • Fast review: MDI corridor must remain “one clean shot” to the edge cluster; no detours around splits.
Card B · Domains & keepouts Red lines that prevent cross-domain coupling (auditable yes/no)
Domains (what belongs where)
  • PHY digital/clock zone: switching edges and clock distribution stay inside this zone.
  • MDI sensitive corridor: short differential corridor with continuous reference plane underneath.
  • Isolation boundary: magnetics defines the crossing point between board and cable environment.
  • Shield boundary: RJ45 shield region where common-mode energy exits the board.
  • Chassis return corridor: preferred low-inductance route for ESD/surge energy back to chassis.
  • PoE current corridor: high-current DC loop that must avoid PHY/clock and MDI corridor.
Keepout rules (red lines)
  • MDI corridor must not cross any plane split/cut/slot (audit: Yes/No).
  • PoE current corridor must not pass through PHY/clock keepout (audit: Yes/No).
  • ESD/surge return corridor must not traverse PHY/clock domain (audit: Yes/No).
  • Shield-to-chassis path must be defined and kept near the edge cluster (audit: Yes/No).
  • Isolation boundary is a strict partition: do not mix copper/features across it beyond intended crossings (audit: Yes/No).
Chassis PHY digital/clock zone PHY digital MDI corridor Isolation boundary MAG isolation boundary Shield boundary RJ45 Return plane (continuous) MDI diff PoE path ESD/Surge → chassis KEEP OUT

Placement Rules: Distance, Orientation, and Edge Strategy

Checklist-ready rules Use X placeholders to fit speed/cable/board stackup constraints

These rules are designed for board review. Each line can be audited as a yes/no check. Where numeric limits depend on PHY/speed/stackup, placeholders are marked as X (mm / mil / °C / A / length mismatch).

Card A · DO (5) Direct-copy placement rules (measurable, auditable)
  1. Keep PHY↔Magnetics (or PHY↔MagJack) MDI corridor short & symmetric.
    Check: via parity difference = 0; mismatch ≤ X; no branches/test stubs.
  2. Keep a continuous reference plane under the entire MDI corridor.
    Check: no split/cut/slot/void under the pair; return plane continuity = Yes.
  3. Form an edge cluster: Magnetics + RJ45 close to the board edge.
    Check: connector/boundary is not dragged inward; boundary-to-edge distance ≤ X.
  4. Route PoE DC as a defined high-current corridor away from PHY/clock & MDI.
    Check: power loop avoids keepout; copper/via meets X A and X °C rise limits.
  5. Reserve test/loopback features without breaking symmetry.
    Check: test pads are mirrored; stub length < X; no asymmetric component placement near the corridor.
Card B · DON’T (5) Anti-patterns that repeatedly cause CRC/EMI/ESD/PoE failures
  1. Do not snake or detour the MDI pair.
    Typical outcome: asymmetry/common-mode conversion → CRC spikes and cable sensitivity.
  2. Do not route MDI across a plane cut/split/slot.
    Typical outcome: return detour increases loop area → EMI peaks and link instability.
  3. Do not place RJ45/magnetics deep inside the board.
    Typical outcome: boundary becomes an “antenna region” → enclosure-dependent EMI and ESD sensitivity.
  4. Do not run PoE current loops through PHY/clock/MDI keepout.
    Typical outcome: load-step events inject noise → link flaps and sporadic drops.
  5. Do not create large ESD/surge return loops inside the board.
    Typical outcome: latent fragility → post-ESD becomes error-prone without hard damage.
Good vs Bad Placement (visual audit) GOOD BAD EDGE plane continuous PHY MAG boundary RJ45 PoE out ESD → chassis short MDI · edge cluster · clean plane EDGE plane cut PHY MAG RJ45 PoE crosses keepout ESD loop (large) detours · splits · loops · inward boundary Visual audit: short symmetric MDI + continuous plane + edge cluster + PoE/ESD returns outside PHY/clock keepout.

Return-Plane Integrity: No Cuts Under the MDI Path

Core rule Differential pairs still need a clean return path (common-mode is the failure amplifier)

Even a differential MDI pair generates common-mode whenever symmetry is imperfect (via imbalance, coupling, pin asymmetry, nearby copper). If the reference plane is cut, return current is forced to detour, increasing loop area and converting the corridor into an EMI antenna. The typical end result is CRC spikes, link flaps, and post-ESD fragility.

Typical sources of “plane cuts” under MDI
  • Split grounds / domain partitions that unintentionally cross the MDI corridor.
  • Layer changes without paired return stitching (signal vias break the return continuity).
  • Connector mounting holes / keepouts that carve anti-pads and voids under the pair.
  • Slots / windows / mechanical cutouts placed too close to the MDI corridor.
  • Over-aggressive copper relief that creates local voids right below the pair.
Card A · What to audit One-glance checks (yes/no)
  • Under-pair continuity: under the MDI corridor projection, no split/cut/slot/void (Yes/No).
  • Layer-change discipline: every signal layer change has nearby return stitching vias (Yes/No).
  • Mounting-hole avoidance: connector holes/keepouts do not sit under the MDI corridor (Yes/No).
  • Boundary proximity: any unavoidable void is outside the most sensitive segment and minimized (Yes/No).
  • Fence availability: stitching fence exists along the corridor edges where needed (Yes/No).
Stitching strategy (rule + X placeholders)
  • Near each layer change: place return stitching within ≤ X mm of the signal via.
  • Along corridor edges: via fence pitch ≤ X mm to suppress return spread.
  • Across unavoidable gaps: stitch both sides of the gap; spacing ≤ X mm to shorten detours.
Card B · Quick fix Fastest fixes when re-spinning a board
  1. Remove the cut: re-route the plane split/slot away from the MDI corridor (highest ROI).
  2. Restore return at layer changes: add paired stitching vias next to every MDI via transition.
  3. Bridge the gap: if a void is unavoidable, stitch both sides to reduce loop area.
  4. Pull the corridor back: shift the MDI corridor into a continuous-plane region (avoid mechanical windows).
  5. Fence for containment: add a via fence along the corridor to limit common-mode spread.
MDI crosses a plane cut → return detour MDI diff Reference plane plane cut intended return return detour EMI ↑ CRC ↑ stitching fence Audit rule: no cuts/slots/voids under MDI; if unavoidable, stitch both sides to minimize detour loop area.

Shielding & Chassis Ground: 360° Bonding Without Making a Noise Loop

Core idea 360° bonding is about low-inductance short returns, not “more connections”

The RJ45 shield is the preferred exit for common-mode and ESD energy. A correct design defines a short, low-inductance shield-to-chassis path near the connector edge cluster. Two recurring failures are floating shields (energy spills into the board) and multi-point random bonds (loops amplify noise and inject ground potential differences). This section focuses on placement and paths only.

360° contact priority (placement view)
  • Best: shield metal couples directly into chassis metal at the panel/edge region.
  • Acceptable: a controlled bridge exists at the edge cluster (not deep inside the board).
  • Avoid: long shield connections that create large loops across the PCB.
Card A · Bonding patterns (3) Patterns by placement/path only
Pattern 1
Direct shield-to-chassis at the edge
  • Best for: maximizing local return for ESD/common-mode at the connector.
  • Placement rule: bond point(s) are inside the connector edge cluster; loop length ≤ X.
  • Risk if wrong: long “chassis path” across the PCB becomes a noise loop.
Pattern 2
Single-point controlled bridge near the edge
  • Best for: reducing loop risk while still providing a defined return path.
  • Placement rule: the bridge element sits at the shield boundary; no long traces to inner board.
  • Risk if wrong: bridge moved inward → return detours through board ground and sensitive zones.
Pattern 3
Split domains: chassis vs board ground with defined coupling
  • Best for: systems with multiple grounds or strong isolation discipline.
  • Placement rule: coupling is explicit and kept at the connector boundary corridor.
  • Risk if wrong: multiple accidental bonds create unpredictable noise loops.
Card B · EMC trade-offs Decision logic (not a tutorial)
  • If the top priority is local ESD/common-mode return, prefer a pattern that keeps shield-to-chassis path short and edge-local.
  • If the system is sensitive to ground potential differences, enforce a single controlled coupling point at the boundary corridor.
  • If there are multiple chassis connections in the product, avoid random multi-point bonds; treat each bond as a potential noise loop.
  • Never allow floating shield states at the connector region; energy then seeks alternate paths through the PCB.
Audit red lines
  • Shield bonding points are defined and edge-local (Yes/No).
  • No “extra” shield-to-board bonds appear deep in the PCB (Yes/No).
  • ESD return arrows can be drawn to chassis without crossing PHY/clock keepouts (Yes/No).
Shield bond patterns (placement + paths) Pattern 1 · Direct Pattern 2 · Single-point Pattern 3 · Split domains Chassis Chassis Chassis RJ45 Shield ESD return (short) edge-local bond RJ45 Shield BR ESD return (controlled) bridge at boundary RJ45 Shield Board GND Chassis GND ESD return (defined) single coupling point avoid random bonds Placement rule: keep shield→chassis returns edge-local and controlled; avoid floating shields and multi-point loops.

PoE Current Paths: Center Tap Routing, Copper, and Thermal

Core rule PoE failures are frequently “current went through the wrong place,” not “insufficient power”

When data and PoE coexist, the dominant risk is an uncontrolled DC current corridor. The intended path runs RJ45 → magnetics center tap → rectifier / power entry and should stay out of PHY, reference clock, and sensitive analog zones. A wrong path creates IR drop, ground bounce, hot spots, and surge coupling that shows up as link flaps and post-event fragility.

Path-only scope (no standards, no topology)
  • Define the DC corridor: draw the PoE loop on the layout and keep it edge-local.
  • Reserve copper and vias: treat the corridor as a power bus, not a signal trace.
  • Validate by heat and drop: accept/reject with thermal and voltage-drop checkpoints.
Card A · PoE keepout map Where PoE current must NOT go
  • Red keepout: PHY core, reference clock, MDI corridor, and any high-impedance nodes.
  • No-cross rule: PoE feed/return must not cross plane cuts that force detours into digital/clock regions.
  • Edge-local corridor: keep the PoE loop close to the connector cluster and power entry region.
  • Mounting holes & cutouts: do not squeeze the PoE corridor through mechanical windows that enlarge loop area.
Copper + via capacity (rules with X placeholders)
  • Main corridor width: DC trunk width ≥ X (or equivalent copper area ≥ X).
  • Layer transitions: use via arrays; total parallel vias ≥ X per transition.
  • Local spreading: widen near the connector and rectifier to reduce current density and hot spots.
Card B · Thermal checks Acceptance points (thermal + drop)
Thermal acceptance
  • Hotspot location: any hotspot must stay in the PoE corridor, not in PHY/clock keepouts (Pass/Fail).
  • Hotspot limit: peak temperature rise ≤ X °C at load for X minutes.
  • Connector proximity: check around center tap / rectifier area for localized heating.
Voltage-drop acceptance
  • Drop budget: RJ45/center-tap to power-entry drop ≤ X mV at target load.
  • Sense points: measure at the connector cluster and at the rectifier/power-entry node (avoid long ground leads).
  • Event stress: after plug/unplug or surge stress, no sustained flapping attributable to brownout or corridor heating.
PoE DC current loop (path + keepouts) RJ45 Magnetics Center Tap Rectifier Power Entry PHY Clock KEEP OUT PoE DC loop wrong path Rule: keep PoE current edge-local; avoid PHY/clock keepouts; size copper and via arrays for load and thermal margin.

Protection Placement: TVS/CMC/Y-Caps/Magnetics Coordination

Core idea Protection effectiveness is dominated by placement and a closed return loop

This section focuses on where to place protection components along the PHY → magnetics → RJ45 → cable path. It avoids part-number debates and instead enforces three invariants: correct side of the boundary, short loop to chassis/controlled return, and no energy spill into PHY/clock zones. A recurring symptom of wrong placement is: ESD passes once, then the link becomes fragile.

Card A · Placement matrix Component → recommended location → goal → common mistake → quick check
TVS
Cable-edge clamp (boundary-aware)
  • Recommended location: at the connector boundary corridor; as close to the cable entry as practical.
  • Primary goal: divert ESD/surge energy to chassis/controlled return before it travels inward.
  • Most common mistake: placing the clamp deep in-board, creating a long, inductive loop.
  • Quick check: the clamp loop can be drawn to chassis without crossing PHY/clock keepouts (Yes/No).
CMC
Common-mode corridor choke (position matters)
  • Recommended location: on the intended common-mode corridor, near the connector-side boundary.
  • Primary goal: contain common-mode energy before it spreads across planes and shield structures.
  • Most common mistake: placing it where common-mode already entered the board ground/shield loop.
  • Quick check: the CMC sits in the shortest path between cable entry and the controlled return boundary (Yes/No).
Y-cap
Common-mode bleed to chassis (short loop)
  • Recommended location: at the shield/chassis boundary corridor; close to a defined chassis node.
  • Primary goal: provide a controlled HF return and avoid floating shield behavior.
  • Most common mistake: scattering multiple bleed points deep in-board, creating unpredictable loops.
  • Quick check: bleed current returns to chassis locally without traversing the board interior (Yes/No).
Boundary
Magnetics defines the isolation/common-mode boundary
  • Placement rule: do not route protection returns across the boundary in a way that injects energy into PHY/clock zones.
  • Quick check: protection loops close at the boundary corridor and exit to chassis, not into the MDI corridor (Yes/No).
Card B · ESD/Surge return path Path checks only (no part selection)
  • Shortest loop wins: clamp and bleed loops must be short and boundary-local, not board-wide.
  • Keepouts respected: return arrows must not cross PHY/clock keepouts (Yes/No).
  • Single controlled exit: chassis/controlled return points should be defined and not multiply scattered.
  • Fragility signature: if ESD passes but later CRC/link flaps rise, suspect long inductive loops and energy spill inward.
Protection placement along PHY → magnetics → RJ45 → cable PHY Magnetics RJ45 Cable Boundary Chassis TVS CMC Y-cap Too inward Rule: place protection at the boundary corridor; keep clamp/bleed loops short to chassis; avoid moving clamps inward across keepouts.

Routing Patterns: Differential Symmetry, Vias, and Keepouts

Template mindset Geometry symmetry + continuous reference plane → stable link and lower EMI risk

MDI differential routing must be treated as a repeatable geometry template. The audit focus is on symmetry, via budget, stub bans, keepouts, and reference-plane continuity. When any of these break, common-mode conversion rises, radiated emissions increase, and CRC/link flaps become more likely.

Audit fields (X placeholders)
  • Zdiff target: X Ω (layout constraint, not a suggestion).
  • Pair skew: |ΔL| ≤ X.
  • Via budget: vias per line ≤ X; transitions must be mirrored.
  • Stub length: forbidden by default; if unavoidable, stub ≤ X.
  • Noise keepout: distance to SW node / inductor / clock ≥ X.
Card A · Do’s (8) Executable rules (audit-ready)
  1. Keep the pair symmetric end-to-end. Audit: both lines share the same bends and spacing. Threshold: |ΔL| ≤ X.
  2. Mirror every layer transition. Audit: via count and locations match left/right. Threshold: vias/line ≤ X.
  3. Use paired vias with local stitch vias. Audit: stitch vias placed near transitions to keep return current local. Threshold: stitch spacing ≤ X.
  4. Maintain a continuous reference plane under the MDI corridor. Audit: no plane cuts/windows under the pair. Result: lower common-mode radiation.
  5. Route in a protected corridor with clear keepouts. Audit: distance to SW node/inductor/clock ≥ X; corridor stays edge-local.
  6. Use via fences where the corridor borders noisy regions. Audit: fence lines formed by grounded vias. Threshold: fence pitch ≤ X.
  7. Keep breakouts short and parallel at PHY, magnetics, and RJ45 pads. Audit: no early separation/merge patterns; pad escape is matched.
  8. Plan measurement without creating stubs. Audit: no branch test pads; use in-line placeholders when needed. Threshold: stub ≤ X (or 0).
Card B · Don’ts (8) Common failure shapes (avoid)
  1. Do not T-branch or “probe-pad branch” the MDI pair. Stub reflections and common-mode rise.
  2. Do not make via counts asymmetric. One extra via is enough to skew and excite common-mode.
  3. Do not cross plane cuts or split grounds. Return detours increase EMI and error sensitivity.
  4. Do not route beside SW nodes, inductors, or fast clock egress. Coupled noise appears as bursts and CRC spikes.
  5. Do not separate lines then re-join near pads. Non-uniform coupling produces imbalance.
  6. Do not create long “meander fixes” without symmetry. Length match must preserve geometry.
  7. Do not place stitching/via fences far away from transitions. The return path becomes uncontrolled.
  8. Do not squeeze the corridor through mounting holes and cutouts. Plane voids and detours magnify loop area.
DO DON’T PHY Magnetics RJ45 SW node Via fence Continuous plane Keepout PHY Magnetics RJ45 SW node Stub Plane cut Too close Rule: keep MDI geometry symmetric, ban stubs, avoid plane cuts, enforce keepouts from SW nodes, and add local stitch/via fences.

Bring-up & Validation: What to Measure and What “Pass” Looks Like

Validation asset Every step must be measurable, repeatable, and mapped back to placement/routing suspects

Bring-up should behave like a gated flow: each gate has a Pass/Fail definition and a short list of placement/routing suspects. The goal is not to “measure more,” but to decide faster and reduce re-spins.

Card A · Validation flow (Gates) Link → PRBS/Loopback → Counters → TDR/RL → EMI/ESD → PoE thermal/drop
Gate 1
Link stability baseline
  • Pass (X): link stays up ≥ X minutes with no periodic flaps.
  • If fail: check keepouts and plane integrity (H2-5/H2-9) and shield bonding patterns (H2-6).
Gate 2
PRBS / loopback capability check
  • Pass (X): error count ≤ X during X minutes test window.
  • If fail: suspect differential symmetry/vias/stubs (H2-9) and placement distances (H2-4).
Gate 3
Counters: CRC / drops / down reasons
  • Pass (X): CRC increment ≤ X per X minutes, stable over temperature/power states.
  • If fail: map bursts to keepouts and plane detours (H2-5/H2-9) and protection return loops (H2-8).
Gate 4
TDR / return-loss signature
  • Pass (X): reflection/return-loss markers within X bounds for the harness setup.
  • If fail: suspect discontinuities at connector/magnetics escape and routing stubs (H2-4/H2-9).
Gate 5
EMI prescan + ESD spot-check
  • Pass (X): prescan margin ≥ X; after ESD spots, no persistent fragility signature.
  • If fail: return-plane detours (H2-5), shield bond patterns (H2-6), and protection placement loops (H2-8).
Gate 6
PoE full-load thermal + drop
  • Pass (X): hotspot rise ≤ X °C; corridor drop ≤ X mV; no brownout-driven flaps.
  • If fail: PoE corridor/copper/via arrays and keepouts (H2-7) plus routing proximity to power loops (H2-9).
Card B · Pass criteria list Card-per-item (mobile-safe)
Item: Link stability
How to measure: monitor link-up time and flap periodicity over a fixed window.
Pass criteria (X): stable ≥ X min; flap count ≤ X.
If fail → likely suspects: H2-5 (plane), H2-6 (shield), H2-9 (keepouts).
Item: PRBS / loopback error rate
How to measure: run a fixed-duration loopback/PRBS window and count errors.
Pass criteria (X): errors ≤ X per X minutes.
If fail → likely suspects: H2-4 (distance/orientation), H2-9 (symmetry/vias/stubs).
Item: CRC / drop counters
How to measure: record counters by time window and correlate with temperature and power events.
Pass criteria (X): CRC increment ≤ X per X min; no burst clusters.
If fail → likely suspects: H2-9 (keepouts), H2-8 (return loops), H2-5 (detours).
Item: TDR / return-loss signature
How to measure: capture reflection markers and compare against the expected harness profile.
Pass criteria (X): markers within X bounds; no strong discontinuity near connector/magnetics.
If fail → likely suspects: H2-4 (escape geometry), H2-9 (stubs/plane cuts).
Item: EMI prescan + ESD spot-check
How to measure: prescan hot spots and apply ESD spots around connector/shield boundaries.
Pass criteria (X): margin ≥ X; post-ESD no persistent “more fragile link” behavior.
If fail → likely suspects: H2-6 (bonding), H2-8 (protection placement), H2-5 (return detours).
Item: PoE full-load thermal + drop
How to measure: thermal image + connector-to-power-entry drop at steady load.
Pass criteria (X): hotspot rise ≤ X °C; drop ≤ X mV; no brownout-driven flaps.
If fail → likely suspects: H2-7 (PoE corridor/copper/vias), H2-9 (routing proximity).
Bring-up validation flow (OK/Fail gates) Gate 1 · Link Pass: stable ≥ X min Fail → suspects H2-5 · H2-6 · H2-9 Gate 2 · PRBS / Loopback Pass: errors ≤ X Fail → suspects H2-4 · H2-9 Gate 3 · CRC / Counters Pass: CRC ≤ X / window Fail → suspects H2-5 · H2-8 · H2-9 Gate 4 · TDR / Return-loss Pass: markers within X Fail → suspects H2-4 · H2-9 Gate 5 · EMI + ESD spots Pass: margin ≥ X Fail → suspects H2-5 · H2-6 · H2-8 Gate 6 · PoE thermal + drop (Pass: X) Fail → H2-7 · H2-9

H2-11 · Field Debug Playbook: Fast Isolation Without Re-spinning First

Scope lock (this page only)
Debug focuses on three layout-rooted causes only: placement, return-plane integrity, and PoE/ESD current paths. No protocol tuning, no stack analysis, no “brand battles”.
Card A · Debug decision tree (symptom → quickest check → layout suspect)
Use the tree to force a fast “layout-first” isolation before blaming firmware. Each leaf points back to the exact chapter to audit (H2-4…H2-9) and the validation gate (H2-10).
Fast “3 things first” rule
  • Voltage drop / power events: PoE or input sag can mimic link instability.
  • Shield-to-chassis bonding: floating or multi-point chaos amplifies common-mode.
  • Plane cuts under MDI corridor: return detours create EMI + CRC together.
Fast layout isolation Symptom → Quick check → Suspect (H2-#) Symptoms (pick one) CRC spikes Link flaps EMI fails PoE hot Quick checks (minutes) Measure PoE/input droop + events Verify shield-to-chassis bonding path Inspect plane cuts under MDI corridor Likely layout suspects (this page) H2-7 PoE current loop invaded sensitive zones H2-6 Shield bond: floating / noisy loop H2-5 Plane cut forced return detour H2-8 Protection return injected into PHY area Next: validate via H2-10 flow (X pass limits)
Card B · 3-minute checks (record before/after)
Check
PoE/input droop under load (measure at RJ45 entry and at DC/DC input).
Tool
DMM + event log (UVLO/brownout flag).
Pass criteria (X)
ΔV ≤ X mV and no UVLO/brownout events within Y minutes.
Fail → suspect
H2-7 (PoE loop/copper/vias) or H2-9 (keepout from power loops).
Check
Shield-to-chassis contact is real (360° mechanical path), not “floating metal”.
Tool
Visual + continuity check (defined single-point or defined network).
Pass criteria (X)
Bonding matches intended pattern; no accidental multi-point loop.
Fail → suspect
H2-6 (bonding pattern) and H2-8 (Y-cap/TVS return path).
Check
No plane cuts/slots/mount holes under the MDI corridor between PHY↔magnetics↔RJ45.
Tool
Layout viewer + quick eyeball trace of return reference continuity.
Pass criteria (X)
Continuous reference plane (no slot crossing). Stitching via fence present where needed (pitch ≤ X mm).
Fail → suspect
H2-5 (return detour) and H2-9 (layer transition strategy).
Check
Temporary A/B swap (one variable only): cable, port, or bonding pattern.
Tool
Counter snapshot (CRC/link-down reasons) before/after.
Pass criteria (X)
CRC/link-down rate stays within X per Y minutes after swap.
Fail → suspect
Improvement strongly indicates placement/return-path issue (H2-4…H2-9).
Risk note (diagnostic only)
Temporary copper-foil bridging across a plane slot must be short-duration and controlled. Purpose is diagnosis of return detour only; it may change EMC behavior and safety assumptions.

H2-12 · Engineering Checklist + Typical Use Cases & Selection Notes

Deliverable
A gate-based checklist that can be executed and signed off (Design → Bring-up → Production), plus tightly-scoped examples of product forms and part-number references that affect placement and current paths.
Part A · Engineering Checklist (Design → Bring-up → Production)
Each gate uses a fixed record format: Check / Tool / Pass criteria (X) / Fail → suspect (H2-#).
Design gate · Placement / Plane / Shield / PoE corridor / Protection
Check
PHY↔magnetics distance minimized, straight, symmetric; via count balanced per pair.
Tool
Layout measurement + pair-length report.
Pass criteria (X)
Length mismatch ΔL ≤ X mm; via mismatch ≤ X; no serpentine in MDI corridor.
Fail → suspect
H2-4 (distance/orientation) + H2-9 (routing symmetry).
Check
No plane cuts/slots/mount holes under the MDI corridor (PHY↔magnetics↔RJ45).
Tool
Layer-by-layer plane continuity audit.
Pass criteria (X)
Continuous reference plane; stitching/via fence pitch ≤ X mm near any boundary.
Fail → suspect
H2-5 (return-plane integrity) + H2-9 (layer transitions).
Check
Shield can and chassis bond path is short and defined (no accidental multi-point loop).
Tool
Mechanical review + continuity map for shield/chassis nets.
Pass criteria (X)
Bonding matches chosen pattern; no “floating shield”; loop area minimized.
Fail → suspect
H2-6 (shield/chassis strategy).
Check
PoE corridor: center-tap / rectifier / hot-swap path stays out of PHY/clock/MDI keepout.
Tool
Current-loop sketch + copper width/via parallel check.
Pass criteria (X)
Copper width ≥ X; via parallel count ≥ X; no high-current return through sensitive zones.
Fail → suspect
H2-7 (PoE current paths) + H2-9 (keepouts).
Check
Protection parts sit where their return loop is shortest to chassis/shield domain (not into PHY area).
Tool
Return-path trace audit (ESD/Surge energy route).
Pass criteria (X)
Loop area minimized; dedicated chassis return; no shared skinny neck through digital ground.
Fail → suspect
H2-8 (TVS/CMC/Y-cap coordination).
Bring-up gate · Link / Counters / TDR / EMI prescan / ESD spot / PoE thermal
Check
Link stability window measured and recorded before any “tuning”.
Tool
Link status + link-down reason counters.
Pass criteria (X)
No flaps; link-down reasons count ≤ X within Y hours.
Fail → suspect
H2-4/H2-9 (length/symmetry) or H2-5 (plane cuts).
Check
CRC/packet drop counters captured at fixed traffic profile and time window.
Tool
Switch/PHY counters snapshot + timestamped log.
Pass criteria (X)
CRC ≤ X per 10^9 bits (or ≤ X per Y minutes, define once).
Fail → suspect
H2-9 (stubs/vias/keepout) + H2-8 (CMC/TVS placement impact).
Check
TDR / return-loss signature matches target shape (no unexpected branch/stub).
Tool
TDR or cable diagnostic mode (if available).
Pass criteria (X)
No extra reflection peak above X; discontinuity locations align with expected connectors only.
Fail → suspect
H2-4 (distance) + H2-9 (stubs/testpoints).
Check
PoE full-load thermal and voltage drop recorded at ambient extremes.
Tool
Thermal camera + sense points (RJ45 entry, center-tap path, hot-swap).
Pass criteria (X)
ΔT ≤ X °C and ΔV ≤ X mV at rated power for Y minutes.
Fail → suspect
H2-7 (current corridor/copper/vias).
Production gate · Geometry consistency / Shield solder / PoE high-current joints / Sample TDR
Check
RJ45/magnetics placement geometry consistent across builds (distance/orientation/edge).
Tool
Assembly drawing + AOI rules on critical dimensions.
Pass criteria (X)
Critical dimensions within X mm; no rotation error; no “alternate footprint stuffing”.
Fail → suspect
H2-4 (edge strategy) + H2-3 (partitioning boundaries).
Check
Shield can solder/contacts are consistent (mechanical bonding defines EMC behavior).
Tool
Visual inspection + continuity spot-check.
Pass criteria (X)
No cold joints; bonding resistance stable within X.
Fail → suspect
H2-6 (bonding) and H2-8 (return paths).
Check
Sample TDR signature or cable diagnostic signature stays within template.
Tool
Manufacturing test step (signature compare).
Pass criteria (X)
Signature delta ≤ X vs golden board.
Fail → suspect
H2-9 (routing/stubs) + H2-4 (placement distances).
Part B · Typical Use Cases & Selection Notes (placement-driven only)
Use cases highlight where placement rules are most unforgiving. Selection notes list only part-number references that change physical boundaries, current corridors, and return paths.
Typical use cases (where placement dominates)
  • Industrial gateway: crowded edge, mixed power noise, chassis bonding complexity.
  • Multi-port switch: port-to-port symmetry + PoE heat density + shield consistency.
  • PLC / remote I/O box: frequent ESD/surge exposure; shield/return paths must be deterministic.
  • Camera & motion control: EMI sensitivity + timing-triggering stability makes common-mode critical.
Selection notes (example PNs that affect placement boundaries)
RJ45 with integrated magnetics (MagJack): changes the “isolation/magnetics boundary” and often simplifies PHY↔magnetics routing length. Example PN: Pulse J0011D21BNL (RJ45 with magnetics).

ESD/TVS for Ethernet signal lines: placement must minimize the transient return loop to chassis/shield domain. Example PNs: Semtech RClamp0504PA, Nexperia PESD2ETH-D.

Common-mode choke (CMC) on data lines: position influences EMI and can alter the effective return path behavior. Example PNs: Würth 744232090 (WE-CNSW), TDK ACM2012-900-2P-TL002.

PoE controllers (corridor + thermal planning impact): power stage placement and high-current joints drive keepouts and copper strategy. Example PNs: TI TPS23881 (PSE controller), TI TPS2373-3 / TPS2373-4 (PD interface).
SVG · Gate summary + reference placement pattern (edge template)
Top: three gates. Bottom: a reusable board-edge template showing corridors and keepouts (placement-first).
Gates + reference placement Deterministic paths, not guesses Gate checklist (sign-off) Design gate placement · plane · shield · PoE · protection Bring-up gate counters · TDR · EMI · ESD · PoE thermal Production gate geometry · shield joints · sample signature Board-edge reference template EDGE RJ45 MAG PHY MDI corridor (short + symmetric) PoE DC current loop ESD/surge return → chassis KEEPOUT SW node · inductors · clocks Continuous plane under MDI + via fence Rule: no cuts under corridor; fence pitch ≤ X mm

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H2-13 · FAQs (Field Debug, No Scope Creep)

Intent
Only closes real-world long-tail troubleshooting around placement, return-plane integrity, shield/chassis bonding, and PoE/protection current paths. No protocol tuning, no new knowledge domains.
Pass-criteria conventions (use consistent denominators)
  • CRC rate window: CRC ≤ X per Y minutes (define Y once for the test).
  • Link stability: link flaps ≤ X per Y hours; record link-down reasons.
  • PoE thermal & droop: hotspot ΔT ≤ X °C and ΔV ≤ X mV at Prated for Y minutes.
  • EMI margin: pre-scan margin ≥ X dB at the worst peak (same setup/band).
Bench passes, enclosure fails EMI — first placement check?
Likely cause: Shield/chassis bonding path becomes long or multi-point in the enclosure, turning common-mode return into an antenna.
Quick check: Map shield-to-chassis contact points and verify a single intended bond; inspect any plane slot/mount hole under the MDI corridor near the connector.
Fix: Move/define the chassis bond near RJ45, minimize loop area, and enforce a continuous reference plane + stitching near the boundary (audit H2-5/H2-6).
Pass criteria: Radiated pre-scan margin ≥ X dB at worst peak, while CRC ≤ X per Y minutes (same traffic profile).
Link flaps only when PoE is enabled — current path or return-plane issue?
Likely cause: PoE high-current loop shares return with MDI/PHY area or crosses a split plane, injecting noise into the link reference.
Quick check: Capture PHY-rail droop during PoE load steps and correlate flaps/CRC with load; visually trace the center-tap corridor for bottleneck vias/copper and plane cuts.
Fix: Reroute PoE corridor along board edge, widen copper, parallel vias, and keep it out of PHY/clock keepouts; restore continuous reference under MDI (audit H2-7/H2-5).
Pass criteria: Link flaps ≤ X per Y hours at Prated, PHY ΔV ≤ X mV on load steps, and CRC ≤ X per Y minutes.
CRC spikes after ESD but no hard damage — where is the first return-path audit?
Likely cause: ESD energy returns through board ground/PHY region due to TVS/Y-cap placement, or a floating shield forces unpredictable return paths.
Quick check: Trace the shortest return from TVS/Y-cap ground pads to chassis/shield; look for a narrow “ground neck” and compare CRC before/after a controlled spot test.
Fix: Relocate protection to the connector boundary and return directly to chassis/shield domain; shorten loop area and add chassis stitching (audit H2-8/H2-6).
Pass criteria: After X controlled strikes, CRC returns to baseline ≤ X per Y minutes for Y minutes and link-down reasons do not increase.
Changing RJ45 vendor breaks stability — magnetics footprint/orientation or shield bond?
Likely cause: Pin mapping/orientation changed (pair polarity/center-taps), or shield pins/bonding geometry differs, shifting common-mode behavior.
Quick check: Cross-check footprint mapping against the datasheet and a golden board; compare TDR “signature” and verify shield-to-chassis continuity is as intended.
Fix: Lock a vendor-agnostic footprint with explicit net naming, enforce a defined shield bonding pattern, and add assembly/AOI checks (audit H2-3/H2-6).
Pass criteria: TDR signature delta ≤ X vs golden, CRC ≤ X per Y minutes, and EMI pre-scan margin ≥ X dB.
Only long cables fail — MDI trace length or plane cut moving reflection/common-mode?
Likely cause: Long on-board MDI corridor and/or a plane slot increases mode conversion; the long cable amplifies common-mode sensitivity.
Quick check: Sweep cable length and log CRC/flaps; audit plane continuity under the MDI path and check symmetry (ΔL, via mismatch, stubs).
Fix: Shorten PHY↔magnetics↔RJ45 routing, eliminate plane cuts, add via fencing/stitching, and keep the corridor away from noise sources (audit H2-4/H2-5/H2-9).
Pass criteria: At Lmax, CRC ≤ X per Y minutes and no link flaps for Y hours (same load/temperature).
ESD passes once, later becomes “fragile” — TVS placement or shield bonding?
Likely cause: Protection return loop injects stress into the PHY region or a noisy/multi-point chassis bond creates repeated common-mode stress.
Quick check: Repeat a small count of controlled strikes while logging CRC drift; trace TVS/Y-cap ground to chassis and verify there is no accidental second bond point.
Fix: Move protection to the boundary with direct chassis return; define a single bond or a controlled network; remove long skinny ground necks (audit H2-8/H2-6).
Pass criteria: Across N = X repeated strikes, CRC drift ≤ X% and link-down reasons do not trend upward within Y minutes post-test.
PoE runs hot near the connector — copper/via/keepout violated?
Likely cause: High-current corridor is bottlenecked (thin copper, insufficient via parallelism) or routed through sensitive/keepout zones, increasing loss and heating.
Quick check: IR scan at Prated; measure ΔV across the connector-to-power path; identify the hottest segment and count parallel vias on that segment.
Fix: Increase copper width/plane support, add parallel vias, keep the loop tight along the edge, and keep it out of PHY/clock areas (audit H2-7).
Pass criteria: Hotspot ΔT ≤ X °C and path ΔV ≤ X mV at Prated for Y minutes, with CRC ≤ X per Y minutes.
Radiated peak at harmonics — clock/switcher coupling into MDI due to placement?
Likely cause: MDI corridor violates keepouts (too close to switch node/inductor/clock) and/or return-plane discontinuities magnify coupling into common-mode.
Quick check: Correlate peak with clock/DC-DC frequency; near-field scan along the MDI corridor; verify any keepout/plane-slot violations close to the connector.
Fix: Enforce keepouts, reroute MDI away from aggressors, add via fence and restore continuous reference plane (audit H2-9/H2-5).
Pass criteria: Worst peak reduced by ≥ X dB (same setup), while CRC remains ≤ X per Y minutes under worst-case activity.
Return loss looks fine but errors persist — common-mode conversion from asymmetry?
Likely cause: Differential imbalance (ΔL, via mismatch, stubs) creates common-mode noise that may not show up as obvious return-loss degradation.
Quick check: Audit symmetry: ΔL ≤ X mm, via count parity, stub length ≤ X; verify protection/CMC placement is symmetric per pair.
Fix: Remove stubs/testpoint spurs, balance transitions, keep routing symmetric, and ensure continuous reference plane + stitching (audit H2-9/H2-5).
Pass criteria: CRC ≤ X per 10^9 bits (or ≤ X per Y minutes) under standardized traffic, and link stable for Y hours.
Extra CMC helps EMI but increases errors — CMC placement causing imbalance?
Likely cause: CMC location adds discontinuity or breaks symmetry (unequal vias/stubs), increasing mode conversion and degrading link margin.
Quick check: Compare TDR signature and check if one pair has extra transition near the CMC; verify CMC is placed where both pairs share the same geometry.
Fix: Place CMC where the corridor is short and symmetric, keep reference plane continuous, and remove nearby stubs (audit H2-8/H2-9).
Pass criteria: EMI margin improves ≥ X dB with CRC delta ≤ X% vs baseline over Y minutes (same traffic).
MagJack design worse than discrete magnetics — what’s the first layout delta check?
Likely cause: The boundary shifted: PHY↔MagJack routing grew longer/less symmetric, shield bond geometry changed, or PoE corridor became congested.
Quick check: Compare three deltas vs the discrete design: MDI corridor length, plane cuts near the connector, and shield-to-chassis bond points; compare TDR signature to the golden board.
Fix: Treat MagJack as “magnetics boundary at the connector”: move PHY closer, straighten/symmetrize the corridor, define shield bonding, reserve PoE copper/vias (audit H2-3/H2-4/H2-6/H2-7).
Pass criteria: TDR signature delta ≤ X vs baseline, CRC ≤ X per Y minutes, and EMI pre-scan margin ≥ X dB (same setup).
Chassis ground connection reduces EMI but increases dropouts — noise loop created?
Likely cause: An unintended multi-point bond creates a noisy loop; chassis noise couples into the PHY reference or PoE return re-routes through sensitive zones.
Quick check: Identify every chassis↔shield and chassis↔board bond; remove/disable only one extra bond (single-variable test) and check if flaps/CRC change; compare common-mode noise with/without.
Fix: Enforce a single defined bond or controlled-impedance network near RJ45; keep PoE return out of the PHY/clock keepout; add stitching to control return paths (audit H2-6/H2-7/H2-5).
Pass criteria: EMI margin ≥ X dB AND link flaps ≤ X per Y hours simultaneously, with CRC ≤ X per Y minutes at Prated.
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