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Bio-Potential Front Ends for ECG / EEG / EMG (INA)

Bio-Potential Front Ends for ECG / EEG / EMG (INA)

← Back to:Instrumentation Amplifiers (INA)

Bio-potential front ends succeed when the “real” error sources are controlled: electrode impedance imbalance, wiring coupling, bias/RLD stability, and overload recovery—not just headline INA specs. This page turns those mechanisms into a practical signal-chain plan and measurable bench gates, so ECG/EEG/EMG waveforms stay stable under real leads, motion, and mains environments.

Scope, use-cases, and what this page does NOT cover

Page boundary (to prevent topic overlap)

This page covers
  • Bio-potential front-end signal chain for ECG / EEG / EMG: electrodes → input protection → INA/AFE → HP/LP/notch → ADC interface → digital post-processing hooks.
  • How real-world CMRR is set by wiring, electrode impedance imbalance, bias return paths, and RLD/bias loop stability (not only by datasheet numbers).
  • Production-minded design: bench checks, reproducible fault isolation, and pass criteria templates for hum, drift, motion artifacts, and saturation/recovery.
Not covered here
  • INA internal topology deep-dives (3-op-amp / 2-op-amp / chopper / PGA internals). Keep the discussion at the external behavior level for this page.
  • Full IEC/medical compliance clauses (standards text). Only design hooks and failure paths are referenced when needed.
  • ADC architecture tutorials. Only the interface, range plan, settling, and noise-budget linkage relevant to bio-potential chains is discussed.

ECG vs EEG vs EMG (engineering quick map)

ECG mV-level signals, low-to-mid bandwidth
  • Dominant pain points: mains hum residual, baseline wander, overload recovery after large transients.
  • Front-end priority: stable bias return + high practical CMRR + controlled high-pass behavior.
EEG µV-level signals, very low-frequency content
  • Dominant pain points: 0.1–10 Hz drift/1/f, leakage-induced offsets, electrode impedance sensitivity.
  • Front-end priority: leakage budgeting + guard/cleanliness discipline + low-frequency noise control.
EMG µV–mV signals, higher bandwidth dynamics
  • Dominant pain points: aliasing control, headroom/saturation, motion artifacts during bursts.
  • Front-end priority: bandwidth + anti-alias plan + fast recovery + robust range setting.

Read by symptom (keeps the main text focused)

  • Mains hum dominates: treat it as a bias return + wiring + electrode-imbalance problem first; RLD/bias loop stability and system CMRR are the usual levers.
  • Baseline drifts for minutes: prioritize electrode polarization + leakage checks before tuning filters.
  • Waveform changes when the lead is touched/moved: isolate shield termination / ground potential / leakage paths vs true electrode motion artifacts.
  • Occasional clipping or long recovery: verify common-mode range + headroom + recovery as a chain (electrode → AFE → filter nodes → ADC range).
Diagram — Bio-potential signal chain map (ECG / EEG / EMG)
Bio-potential front-end signal chain map for ECG, EEG, and EMG Three parallel lanes show electrodes, input protection, INA/AFE, filters, ADC, and digital processing. Each lane labels bandwidth, amplitude, and dominant artifacts. ECG / EEG / EMG: same chain, different dominant constraints Blocks Min text ECG EEG EMG Electrodes Protection INA / AFE HP/LP/Notch + ADC BW: low–mid Amp: mV Artifact: hum / drift Electrodes Protection INA / AFE HP/LP/Notch + ADC BW: very low Amp: µV Artifact: drift / leak Electrodes Protection INA / AFE LP / AAF + ADC BW: higher Amp: µV–mV Artifact: alias / sat RLD / Bias
The same block chain appears in ECG/EEG/EMG, but the dominant constraint shifts (hum/drift/leakage/aliasing). Keeping this map explicit prevents accidental expansion into unrelated topics.

Electrode–skin interface as the real “source impedance”

Minimal electrode model (enough to predict hum, drift, and motion artifacts)

  • Half-cell potential (Vhc): a DC-like polarization source that can shift with chemistry and contact conditions.
  • Contact resistance (Re): changes with pressure, gel, sweat, and lead motion; often the strongest contributor to time-variant imbalance.
  • Double-layer capacitance (Cdl): sets low-frequency settling and recovery; drives “slow return” after disturbances.
Treating the electrode pair as a fixed resistor hides the real failure mode: time-varying impedance imbalance converts common-mode interference into differential error inside the measurement band.

Why “high CMRR” collapses on real electrodes

Mechanism
With Z1 ≠ Z2, mains/common-mode interference produces a differential residual at the amplifier input. The residual typically scales with the imbalance ratio (ΔZ/Z) and is amplified like a real signal. This is why a system can show poor hum rejection even when the INA datasheet lists excellent CMRR.
Design actions that actually help
  • Match anything that touches both inputs: series resistors, RC components, and clamp paths should be symmetric to avoid adding extra mismatch.
  • Keep bias return controlled: a floating input will wander to rails and destroy practical CMRR. A defined bias path is required before filtering can behave predictably.
  • Budget leakage as an error source: input protection leakage and board surface leakage can create a pseudo-signal through high source impedance (especially in EEG).

Motion artifact: a wiring-and-contact problem, not a notch problem

The dominant causal chain is usually:
Mechanical motion → contact impedance changes (ΔZ(t)) → low-frequency differential steps/drift → baseline wander
A mains notch only targets a narrow frequency band. Motion artifacts are often non-stationary and low-frequency, so the right fix is to control contact variability, leakage paths, and the bias return/RLD loop behavior rather than trying to “filter it away.”

Bench checks (A/B tests) to identify the true root cause

Test 1 — Input short (baseline)
  • Quick check: short inputs symmetrically (or use a symmetric resistor network) to measure intrinsic noise/hum.
  • Watch: 0.1–10 Hz drift, mains component in FFT, wideband RMS in the target bandwidth.
  • Pass criteria: baseline should meet the noise/hum budget before chasing electrode issues; otherwise inspect leakage, grounding, and symmetry first.
Test 2 — Electrode simulator (controlled mismatch)
  • Quick check: emulate electrodes with RC networks and intentionally add imbalance (Z1 ≠ Z2).
  • Watch: mains residual rising with ΔZ; confirm CM→DM conversion dominance.
  • Pass criteria: mains residual should scale predictably with mismatch; unexpected sensitivity usually indicates protection mismatch or hidden leakage.
Test 3 — Motion injection (repeatable artifact)
  • Quick check: apply small, repeatable changes to the simulator (or controlled electrode press/release).
  • Watch: low-frequency steps, recovery time, and any amplifier saturation/recovery behavior.
  • Pass criteria: recovery to within the acceptable baseline window should meet the application time target (set by the system budget).
Test 4 — Leakage sensitivity (EEG-critical)
  • Quick check: compare clean/dry vs touched/humid conditions around high-impedance nodes.
  • Watch: drift and low-frequency wander amplification; temperature-dependent offsets after protection devices.
  • Pass criteria: if leakage dominates, prioritize guarding/cleanliness and protection leakage specs before tuning filters.
Diagram — Electrode interface + mismatch converts common-mode to differential error
Electrode impedance mismatch converting common-mode mains interference into differential residual Left shows two electrode models with half-cell potential and RC interface. Middle highlights Z1 not equal Z2 and motion-induced delta Z over time. Right shows common-mode interference producing a differential residual. Practical CMRR is set by Z mismatch + leakage paths, not only by datasheet CMRR Electrode interfaces Electrode 1 Vhc + (Re || Cdl) Electrode 2 Vhc + (Re || Cdl) Z1 source impedance Z2 source impedance Mismatch Z1 ≠ Z2 imbalance ratio motion ΔZ(t) time-varying Result Vcm 50/60 Hz Vdm residual in band amplified
A small impedance mismatch (or motion-driven ΔZ(t)) can turn a large common-mode interference into a measurable differential residual. This is why electrode balance, symmetric protection, leakage control, and bias return design are primary CMRR levers in bio-potential systems.

Patient biasing & return path: RLD / bias resistor networks

Why a bias return is mandatory (before any filtering “works”)

  • No defined return path → common-mode drifts: tiny input bias currents, leakage, and capacitive pickup can push the input common-mode until nodes clip near rails. Once that happens, hum rejection and recovery become unpredictable.
  • Return path sets the operating point: a controlled DC/low-frequency path keeps electrode and amplifier common-mode inside the linear range, which is a prerequisite for stable notch/band-pass behavior.
  • Practical symptom: “sometimes hum is low, sometimes it explodes” often indicates a floating bias condition rather than a bad notch filter.
Fast check: compare with/without bias return — look for rail-hugging, slow baseline crawl, and non-repeatable hum.
Pass criteria (template): with the bias return enabled, the signal chain should stay out of saturation, the baseline should settle to a stable window, and the measured mains component should be repeatable across power cycles and cable handling.

RLD as a closed-loop common-mode servo (what each block “owns”)

Core loop
  • CM extraction: estimate electrode common-mode at a defined point in the front end (avoid DM leakage into the CM estimator).
  • RLD amplifier + low-pass shaping: set loop gain around mains frequency while maintaining phase margin.
  • Body drive / return: inject a counter-phase CM component through a controlled, current-limited path to reduce the CM seen by the inputs.
Success metrics
  • Mains CM reduction: the CM at the inputs drops measurably near 50/60 Hz.
  • Stability: no sustained ringing/self-oscillation at the RLD output or at the AFE output.
  • Recovery: motion events and transients do not push the loop into long saturation or slow return.

Stability knobs (what to change first, and what it breaks)

Phase margin (loop stability)
  • Helps: prevents hum from getting worse after enabling RLD, prevents sustained oscillation.
  • Hurts if ignored: RLD can amplify noise or create low-frequency “wobble”.
  • Quick check: observe RLD output for ringing; verify hum is reduced in a repeatable way.
Riso (output isolation / current limiting)
  • Helps: stabilizes the driver against capacitive loading and constrains fault currents.
  • Trade-off: too large reduces effective body drive, leaving CM insufficiently controlled.
  • Quick check: sweep Riso and compare hum reduction vs recovery time and stability symptoms.
Cf (loop shaping / LPF)
  • Helps: suppresses high-frequency loop gain and improves phase margin.
  • Trade-off: too strong can reduce mains-band loop effectiveness (hum reduction plateaus).
  • Quick check: confirm that hum decreases without introducing slow “breathing” or delayed recovery.
Common pitfalls
  • RLD makes hum worse: usually indicates insufficient phase margin or a CM extractor that leaks DM content into the loop.
  • Bias resistor too large: CM becomes weakly defined; the system becomes sensitive to leakage and cable motion.
  • Bias resistor too small: increases leakage/current concerns and can worsen noise pickup via return currents.

Topology scenarios (2-electrode / 3-electrode / multi-lead)

Two-electrode
Most sensitive to floating CM. Bias return must be explicitly defined; otherwise the front end can drift and clip. RLD stability is more fragile because the “body drive” interacts strongly with electrode imbalance and cable capacitance.
Three-electrode (dedicated RLD)
The RLD electrode provides a controllable CM drive path. Keep the injection path current-limited and stable; verify that enabling RLD reduces mains-band CM without creating long recovery after motion events.
Multi-lead / multi-channel
CM extraction and injection must remain symmetric. A robust approach treats RLD as a shared CM servo with carefully controlled routing and a clear “single-owner” return path to avoid distributed ground loops that convert CM into DM.

Bench SOP (fast validation without over-modeling)

SOP-1 — A/B: RLD OFF vs ON
  • Measure: mains component (FFT peak), baseline stability, and any rail-hugging events.
  • Interpret: if hum does not reduce repeatably, focus on loop stability, CM extraction point, and return path integrity before tuning filters.
SOP-2 — Stability sniff test
  • Probe: RLD output node and AFE output node.
  • Fail signs: sustained ringing, periodic low-frequency wobble, or hum increasing after enabling RLD.
  • Fix knobs: reduce loop gain near high frequency, adjust Cf, adjust Riso, and re-check phase margin symptoms.
SOP-3 — CM-only injection
  • Method: inject a controlled common-mode signal into a body/electrode simulator without adding differential stimulus.
  • Goal: confirm the RLD loop reacts to CM (not DM) and reduces the measured residual at the output.
  • Pass: CM reduction correlates with loop settings; non-correlation suggests DM leakage into the extractor or return-path issues.
Diagram — RLD loop block diagram + stability knobs
Driven Right Leg loop showing CM extraction, loop shaping, and body drive Five blocks in a loop: Electrodes, AFE, CM extractor, RLD amp with LPF, and Body drive. Knobs indicate phase margin, Riso, and Cf. RLD is a closed-loop CM servo: effectiveness + stability must be validated together Electrodes CM pickup AFE INA / AFE CM Extract estimator RLD Amp + LPF loop shaping Body Drive return path Phase margin Riso Cf Hum ↓ Stable Key validation 1) CM-only injection → residual falls 2) No ringing at RLD output 3) Recovery stays fast
Treat RLD as a control loop. Verify CM reduction and stability together; otherwise hum can increase or recovery can degrade even when the schematic looks correct.

“Real CMRR” budgeting: wiring, imbalance, and common-mode range

System CMRR is dominated by CM→DM conversion paths (not a single datasheet line)

The measured mains residual behaves like a real differential input because multiple paths can convert a large common-mode interference into an in-band differential component. Practical debugging starts by identifying which path dominates in the current build.
Rule of thumb
If changing the INA to a “higher CMRR” part does not improve hum, the dominant path is almost always mismatch or wiring coupling, not the amplifier core.

Contributors (prioritized by how controllable they are on the PCB)

Protection mismatch (often the quickest win)
  • Unmatched series resistors, RC parts, or clamp paths create extra ΔZ that converts CM to DM.
  • Fix by symmetric values, symmetric placement, and mirrored routing into the AFE inputs.
  • Debug hint: swapping left/right input networks that changes hum strongly indicates mismatch dominance.
Electrode mismatch (system-inherent, but measurable)
  • Imbalance in electrode impedance turns a large CM interference into a DM residual within the passband.
  • Manage with consistent electrode contact, stable placement, and a bias scheme that keeps CM within linear range.
  • Debug hint: controlled ΔZ injection that scales hum residual confirms electrode-dominant behavior.
Cable coupling (field-dominant)
  • Lead capacitance, shield termination, and ground potential differences inject CM that later converts to DM through mismatch.
  • Manage with consistent shield strategy, minimized loop area, and robust lead handling sensitivity tests.
  • Debug hint: touching/moving the cable changing hum indicates coupling + conversion dominance.
AFE CM range (near-rail nonlinearity & recovery)
  • If CM approaches rails, internal stages can enter nonlinear regions; CMRR becomes irrelevant and recovery time dominates observed artifacts.
  • Manage by setting a robust CM operating point, headroom planning, and validating recovery after CM steps.
  • Debug hint: shifting the bias point changing hum/recovery strongly indicates CM range or saturation involvement.

Weighting differs by modality (keep budgets modality-specific)

ECG
The dominant budget pressure is usually mains rejection and baseline stability. Prioritize return-path integrity, RLD stability, and CM headroom so the chain avoids overdrive and slow recovery.
EEG
µV-level signals amplify leakage and low-frequency drift sensitivity. Budget should emphasize electrode imbalance slope, leakage control, and low-frequency stability more than wideband noise density alone.
EMG
Higher bandwidth makes aliasing and cable RF pickup more visible. Budget should include anti-alias and recovery behavior so dynamic bursts do not saturate the chain or fold noise into the band.

CM injection SOP (turn “CMRR” into a measurable budget table)

Step-by-step
  1. Baseline: short inputs symmetrically (or use a symmetric network) to establish intrinsic hum residual.
  2. CM-only injection: inject a controlled mains-band CM into a body/electrode simulator without a DM stimulus.
  3. Measure: output hum residual (and convert to input-referred residual if desired).
  4. Isolate contributors: (a) add controlled electrode ΔZ, (b) add intentional protection mismatch, (c) change cable/shield handling, (d) shift CM operating point.
  5. Budget table: record each contributor as a worst-case residual or sensitivity slope; map each to the primary mitigation action.
Pass criteria (template)
  • Repeatability: under the same CM injection, hum residual stays within a defined window across power cycles and cable handling.
  • Directionality: when only one contributor is changed (e.g., protection mismatch), the residual changes in the expected direction.
  • Headroom safety: CM shifts do not push the AFE into saturation or slow recovery that would invalidate the CMRR budget.
Practical warning: a “good” CMRR number is meaningless if the chain is operating near rails or in recovery.
Diagram — System CMRR contributors stack (what to budget and validate)
System CMRR contributor stack showing conversion paths A common-mode interference arrow feeds a stacked contributor bar: electrode mismatch, protection mismatch, cable coupling, and AFE common-mode range. The stack produces a differential residual output. System CMRR = sum of CM→DM conversion contributors (measure each, then fix the dominant one) Vcm mains / E-field Contributors Electrode mismatch Protection mismatch Cable coupling AFE CM range Vdm residual in band amplified Measure by CM injection Budget each contributor
A practical CMRR plan budgets conversion paths (mismatch, coupling, headroom) and validates them with a CM-only injection procedure. This reveals whether the next fix should be symmetry, wiring, bias point, or recovery behavior.

Noise strategy: 0.1–10 Hz vs wideband, and why it differs for ECG/EEG/EMG

Pick the dominant noise metric first (avoid the “nV/√Hz trap”)

A single noise number never predicts usable bio-signal resolution. The correct approach is to select the dominant metric for the modality, map it into the target bandwidth, and validate with repeatable bench measurements.
EEG
Prioritize 0.1–10 Hz peak-to-peak and the 1/f corner. Low-frequency drift and flicker dominate what can be resolved.
ECG
Prioritize baseline stability, mains residual, and overload recovery. A low density number does not help if the chain clips or recovers slowly.
EMG
Prioritize wideband density → RMS in band and anti-alias. Wider bandwidth makes integrated RMS and aliasing the dominant risks.
Practical rule: EEG starts from 0.1–10 Hz p-p, EMG starts from RMS-in-band, ECG starts from “no clipping + controllable mains + fast recovery.”

Close the loop: datasheet noise → bandwidth → input-referred resolution

  1. Define the usable band: choose the measurement bandwidth for the modality (the band is the “noise integration window”).
  2. Select the metric: 0.1–10 Hz p-p for low-frequency fidelity, density for wideband, and integrated RMS for “what the ADC really sees”.
  3. Map into band: translate density into RMS in band using the actual analog/digital filters used in the chain.
  4. Translate to resolution: compare input-referred RMS or p-p against the minimum detectable signal (or required SNR) for the application.
  5. Validate on hardware: measure shorted-input PSD and band-limited RMS (do not rely on a single typical spec).
Bench measures (minimum set)
Shorted input → PSD (spectrum), 0.1–10 Hz p-p (long window), and RMS in band (using the same passband used in production).
Pass criteria (template)
  • 0.1–10 Hz: peak-to-peak stays below the low-frequency resolution budget.
  • RMS in band: integrated RMS stays below the in-band noise budget with guardband.
  • Repeatability: metrics remain stable across power cycles and cable handling under the same test setup.

Zero-drift / chopper: external symptoms and system-level handling

Zero-drift techniques can improve offset and low-frequency drift, but they may introduce visible artifacts that must be managed at the system level. The focus here is on what shows up at the pins and how to validate it.
Ripple peaks / tones
  • Symptom: narrow spectral peaks or ripple energy appears in PSD.
  • Handle: place ripple outside the passband using filter planning; verify it does not fold into band via aliasing.
High source impedance interaction
  • Symptom: unexpected low-frequency noise or drift sensitivity increases with electrode impedance.
  • Handle: validate with electrode-simulator networks; keep input networks symmetric and leakage-controlled.
Overload & recovery
  • Symptom: motion artifact or input disturbance causes long baseline return.
  • Handle: include recovery time in acceptance tests; avoid operation near rails and confirm headroom.
Acceptance template: ripple peaks stay out of band, integrated RMS stays within budget, and recovery time after a defined disturbance stays below a system-defined threshold.
Diagram — Noise map to bandwidth (EEG vs ECG vs EMG)
Noise metrics mapping for EEG ECG and EMG Three modality panels show dominant noise metrics and the shared validation set: shorted input PSD, 0.1–10 Hz peak-to-peak, and RMS in band. Choose the dominant metric by modality, then validate with band-limited measurements EEG ECG EMG 0.1–10 Hz p-p 1/f corner drift baseline mains recovery density RMS in band anti-alias Validate Shorted input PSD 0.1–10 Hz p-p RMS in band
Report both 0.1–10 Hz peak-to-peak and band-limited RMS from a shorted-input setup. Use modality weighting to decide what is a pass/fail driver.

Filtering integration: HP/LP band-pass + notch without breaking stability or CMRR

High-pass (HP): baseline control vs low-frequency information

  • Purpose: remove electrode polarization drift and motion-induced baseline wander so the front end stays inside its linear window.
  • EEG boundary: raising HP too aggressively discards true low-frequency content and can create apparent “flatness” that is not real fidelity.
  • ECG boundary: baseline stability and fast return after motion often dominate perceived quality more than incremental density improvements.
Pass criteria (template): after a defined motion / disturbance event, baseline returns within the allowed window within a defined recovery time, without HP-induced ringing or shape distortion in the passband.

Low-pass (LP) / anti-alias (AAF): protect the ADC from out-of-band noise

  • Purpose: limit out-of-band energy so it cannot fold into the band after sampling.
  • EMG emphasis: wider passbands increase integrated noise and raise alias sensitivity; AAF placement and sampling rate must be planned together.
  • System check: vary sample rate (or decimation) and confirm in-band noise does not show alias-driven anomalies.
Pass criteria (template): with a controlled out-of-band injection, in-band RMS stays within budget and does not rise unexpectedly with sampling configuration changes.

Notch: analog vs digital (system trade-offs, not a DSP lesson)

Analog notch
  • Pros: reduces large mains content before the ADC, lowering overload risk.
  • Cons: tolerance-driven depth/phase changes; can add distortion and unwanted group delay effects.
Digital notch
  • Pros: stable depth and tunability; can be very deep without analog tolerance penalties.
  • Cons: requires analog headroom and recovery so the ADC is not already saturated by mains content.
Pass criteria (template): notch depth at the target frequency meets budget, and out-of-notch band distortion / shape change remains within allowed limits.

Avoid breaking CMRR: symmetry rules when filtering touches the inputs

  • Pre-INA networks are dangerous when asymmetric: any unmatched input RC or protection element creates ΔZ and converts common-mode pickup into in-band differential residual.
  • Mirror placement matters: same values are not enough—use symmetric placement and symmetric routing into the AFE pins.
  • Validation: repeat the CM injection test with and without the input network to verify it does not worsen mains residual.
Quick check: swap left/right input networks — strong hum change implies mismatch dominance.

Output drive stability: filters can look like capacitive loads

  • Problem: RC/AAF networks at the output can reduce phase margin and create ringing, overshoot, or slow recovery.
  • Mitigation knobs: use Riso to isolate capacitive loading; keep large capacitors behind isolation; verify step response in the final configuration.
  • Acceptance: step response overshoot, ringing, and settling remain within budget; recovery remains fast after large disturbances.
Pass criteria (template): controlled step injection shows bounded overshoot/ringing and settling within a defined time, while notch depth and in-band noise targets are preserved.
Diagram — Where to place HP/LP/notch relative to INA + ADC
Filter placement slots pre-INA post-INA and digital A signal chain shows electrodes, input network, INA/AFE, ADC, and digital. Three filter slots highlight pre-INA, post-INA, and digital placement with pros and cons chips. Place HP/LP/notch by intent: headroom, CMRR symmetry, and stability must stay intact Electrodes Input net INA / AFE ADC DSP pre-INA slot post-INA slot digital slot CMRR risk anti-overload stability clean gain deep notch needs headroom Validate step FFT CM inject overload recovery
Filter placement is a system decision. Pre-INA placement risks CMRR through mismatch, post-INA placement risks stability through capacitive loading, and digital notch requires analog headroom and fast recovery.

Input protection & safety hooks: ESD, defib, lead-off, and fault modes

Design order: protect the person → protect the AFE → protect accuracy

  • Person-first: ensure any fault energy is handled by the front protection stages and does not create uncontrolled current paths through the body interface.
  • AFE survival: clamp and limit so pins do not latch into a “stuck” state; allow fast return to linear operation after disturbances.
  • Accuracy last: model and budget the protection side-effects (leakage → offset, capacitance → bandwidth/distortion, series impedance → noise/settling).
Protection is not “free”. Every added device must close a loop: side-effect → budget → validation.

Staged protection ladder: clamp early, limit energy, then pin-level protection

A robust bio-potential input uses a staged ladder from the connector to the AFE. The early stage absorbs large transients, the middle stage limits current/energy into sensitive nodes, and the final stage prevents pin overstress while preserving recoverability.
Stage 1 — line-side clamp
Primary clamps near the connector reduce peak stress before it reaches high-impedance nodes.
Stage 2 — series limit
Series impedance limits surge current and defines how much energy downstream clamps and the AFE must handle.
Stage 3 — pin-level clamp
Final clamps define the pin voltage limits and improve survival, but their leakage/capacitance must be budgeted.

Defib / large transients: prioritize “no lock-up” and fast recovery

  • Goal: allow controlled clamping and saturation during the event, but prevent the AFE from remaining stuck in saturation afterward.
  • Energy control: the line-side clamp handles the bulk, the series stage limits downstream current, and the pin-level clamp keeps pins inside safe ranges.
  • Recoverability: the chain should return to linear operation quickly so post-event data is usable without long blind time.
Pass criteria (template): after a defined transient injection, the output returns to its linear window within Trecover, baseline shift remains within the offset budget, and in-band noise does not remain elevated.

Lead-off detection: interface hooks (injection / bias), not algorithms

Lead-off is a system interface problem: the analog front end must provide a reliable observable signature under “connected” and “open” conditions without contaminating the measurement band.
Injection method
  • Hook: inject a small test stimulus and observe the response.
  • Risk: stimulus visibility depends on the band-pass / notch chain.
Bias method
  • Hook: use bias return behavior so open circuits move to a predictable state.
  • Risk: leakage and high source impedance can create false states.
Pass criteria (template): false open / false connected rates stay below a threshold across electrode impedance ranges and cable motion conditions.

Fault modes: what changes on the pins (and what to probe first)

Common faults produce repeatable symptoms. Mapping each symptom to a first probe point shortens debug time and reduces “random” protection tuning.
  • Open lead: output rails or becomes mains-dominated; check bias return node and lead-off hook node first.
  • Short to ground / rail: clamps conduct continuously; check series stage current and clamp node voltage.
  • Cable plug/unplug: large spikes and long recovery indicate inadequate energy limiting or insufficient headroom.
  • Clamp conduction tail: slow return suggests leakage/RC tails into the bias path or output saturating too close to rails.
Diagram — Staged protection ladder + leakage budget node
Staged protection ladder from connector to AFE with leakage budget node A three-stage protection chain shows line-side clamp, series limit, and pin clamp. A leakage budget node highlights leakage-to-offset risk and validation chips for drift, recovery, and lead-off error. Staged protection: clamp early → limit energy → clamp at pins, then budget leakage and recovery Connector Stage-1 clamp Stage-2 limit Stage-3 clamp INA / AFE pins ESD Defib I_leak node Leakage → offset Validate post-ESD drift recovery time lead-off error rate no lock-up after events leakage budget stays inside spec
The ladder must survive large events and also preserve low-frequency fidelity. Leakage paths must be modeled as input-referred offset and validated after stress.

ADC & reference co-design: dynamic range, input range, and ratiometric thinking

ADC fields that matter here (keep the list tight)

Input form & range
  • Diff vs SE: match the AFE output type and common-mode requirements.
  • FSR / input range: defines usable dynamic range and headroom before clipping.
  • Input common-mode constraints: ensure linearity away from rails.
Noise & rate
  • Input-referred noise: must be consistent with EEG/ECG/EMG bandwidth choices.
  • Sample rate: must close the loop with analog AAF and digital decimation.
  • Digital filtering hooks: useful only when headroom and recovery are already solved.
Multi-channel coherency
  • Sync sampling / trigger: reduces timing skew across channels.
  • Timestamp alignment: helps correlate events and reject artifacts.
  • Consistent recovery: ensures channels do not diverge after overload.

Range planning: maximize FS use without living at the rails

  • Do not chase 100% FS: reserve headroom for motion artifacts, mains pickup, and electrode imbalance events.
  • Budget clipping events: a low-noise chain that clips frequently delivers worse usability than a slightly noisier chain with stable headroom.
  • Verify recovery: the chain must return to linear operation quickly after a large disturbance.
Pass criteria (template): FS utilization stays within a target window, clip/saturation event count stays below a limit, and recovery time after a defined disturbance stays below Trecover.

Reference & bias: place the signal in the most linear region

  • Reference choice: low noise and low drift matter only if dynamic headroom and recovery are already controlled.
  • Bias planning: align AFE output common-mode with ADC input requirements; avoid near-rail operation to reduce distortion and slow recovery.
  • Stability with filters: confirm reference/bias networks do not create load steps or coupling that pushes the AFE into non-linear regions.

Sampling-rate ↔ filtering: minimal closed-loop checks for ECG/EEG/EMG

  • EEG: low-frequency fidelity and long-window stability dominate; decimation must preserve 0.1–10 Hz performance.
  • ECG: mains residual and recovery windows dominate; sampling and notch must not hide overload artifacts.
  • EMG: anti-alias is dominant; confirm out-of-band energy cannot fold into band across rate configurations.
Pass criteria (template): changing sampling/decimation does not produce unexpected in-band noise jumps, and multi-channel timing alignment stays within the system-defined skew budget.
Diagram — Range plan: electrodes → AFE gain/bias → ADC full-scale (with headroom)
Range planning from electrode signal through AFE gain and bias to ADC full-scale A three-stage map shows electrode microvolt to millivolt levels, AFE gain and bias, and ADC full-scale with headroom bands. Validation chips include FS utilization, clip count, and recovery. Range planning: use FS efficiently while reserving headroom for artifacts and recovery Electrode AFE gain + bias ADC full-scale µV–mV artifact Gain (G) Bias (Vcm) linear headroom headroom clip events count Validate FS utilization clip count recovery time sync
The range plan must preserve headroom under artifacts. Track full-scale utilization, clip events, and recovery time as production-ready metrics.

Cabling, shielding, grounding: how to keep mains and RF out in real leads

When touching or moving the cable changes the reading: debug by coupling path

Cable sensitivity is almost always a coupling-path problem. The fastest path to a stable waveform is to isolate which path dominates first, then apply the smallest physical change that breaks it.
Shield termination
A floating or wrong-terminated shield turns touch into an E-field injection point.
Ground potential & return
Shared return impedance and reference shifts convert common-mode pickup into differential error.
Leakage into high-Z nodes
Moisture/contamination plus high source impedance produces touch-driven drift and steps.
RLD / bias loop coupling
A bias loop that fights the cable reference can amplify mains instead of suppressing it.
Differential asymmetry
Unequal series elements or routing imbalance turns common-mode fields into a differential signal.
Priority rule: identify the dominant coupling path before changing components.

Shield termination: 1-end vs 2-end vs hybrid (pick by loop risk vs HF shielding)

  • 1-end termination: reduces low-frequency loop risk; may be weaker at high-frequency shielding if the far end floats.
  • 2-end termination: improves high-frequency shielding; increases the chance of a low-frequency ground loop (mains hum can rise).
  • Hybrid termination: one end bonded for DC reference, the other end tied through a small HF path (capacitive/RC) to close the high-frequency loop without a strong DC loop.
The termination choice must be validated with a controlled touch/sway test, not by rules of thumb.

Guarding high-Z nodes: prevent leakage-driven drift (EEG-class sensitivity)

High source impedance makes leakage behave like a signal source. Guarding reduces the electric field gradient at sensitive nodes and limits how surface leakage converts into input-referred offset and drift.
  • Where: guard the input pins, bias return nodes, and any high-impedance traces.
  • How: keep guard continuous and reference it to a suitable potential near the guarded node.
  • Common failure: broken guard continuity or wrong reference turns guard into another coupling antenna.
Budget reminder (template): leakage × source impedance must stay within the offset/drift budget.

Single-supply systems: define one reference point and keep return paths predictable

  • Define the measurement reference: choose the point the shield and bias network consider “ground”.
  • Avoid narrow shared returns: keep high-impedance measurement returns away from noisy digital return bottlenecks.
  • Keep continuity: do not force shield or reference current across splits or high-impedance bridges.

RF ingress: stop it at the connector with symmetry before tuning filters

RF often shows up as low-frequency drift, random steps, or unstable baselines because non-linearities can demodulate RF into the passband. The first fix is to reduce RF at the entry with symmetric networks and clean reference routing.
  • Symmetry first: match both input sides so common-mode remains common-mode.
  • Entry first: place RF suppression close to the connector so the cable is not an antenna feeding the board.
  • Validate: bring a near-field RF source close and confirm the baseline does not shift beyond the budget.

Touch / sway sensitivity test (repeatable template)

Define a repeatable action and quantify its impact. Use the same cable routing and the same motion profile for every A/B test.
  • Touch: hold the cable jacket/shield for thold seconds.
  • Sway: swing the cable with amplitude Amove at fmove for tmove.
  • Observe: mains amplitude change ΔHum, baseline change ΔBaseline, spike count Nspike.
  • Pass criteria: ΔHum < Hum_budget, ΔBaseline < Drift_budget, Nspike/min < Spike_rate_budget.
Diagram — Cable + shield termination patterns (1-end vs 2-end vs hybrid)
Shield termination patterns for bio-potential leads Three side-by-side diagrams show one-end shield termination, two-end termination with loop risk, and hybrid termination using an HF path. Validation chips show touch, sway, and hum. Shield termination: trade low-frequency loop risk against high-frequency shielding 1-end 2-end hybrid cable shield REF LF safer cable shield REF REF loop risk cable shield REF REF C HF shield Validate touch sway hum A/B compare
Use the same touch/sway script for all termination A/B tests. The best termination is the one that reduces hum and motion sensitivity in the real lead setup.

Validation plan: what to measure first when the waveform is messy

Priority 1 — shorted input: baseline noise and mains residual

  • Condition: differential short at the input to remove external coupling.
  • Measure: in-band RMS, 0.1–10 Hz p-p, 50/60 Hz residual.
  • Gate: if all are inside budgets, move to Priority 2.
Pass criteria (template): RMS < Noise_budget, LF p-p < LF_budget, hum < Hum_budget.

Priority 2 — body network: system CMRR and RLD effectiveness

  • Condition: use a body-equivalent network and compare RLD/bias on vs off.
  • Measure: hum residual, stability symptoms, recovery time after disturbances.
  • Gate: if RLD reduces hum without instability and recovery stays fast, move to Priority 3.
If hum gets worse with RLD enabled, treat it as a loop/reference coupling problem before changing parts.

Priority 3 — electrode substitute: sensitivity to impedance mismatch

  • Condition: compare a matched network versus a controlled ΔZ network.
  • Measure: hum increase and low-frequency drift increase versus the matched case.
  • Gate: if ΔZ does not explode hum/drift beyond budgets, move to Priority 4.
Pass criteria (template): ΔHum < ΔHum_budget, ΔDrift < ΔDrift_budget.

Priority 4 — cable A/B: touch/sway sensitivity and termination choice

  • Condition: A/B compare termination and cable types with the same scripted touch/sway action.
  • Measure: ΔHum, ΔBaseline, Nspike per minute.
  • Gate: select the wiring/termination that meets budgets before changing silicon.
Diagram — Debug flowchart (Hum / Drift / Saturation / Motion)
Debug flowchart for messy waveforms A flowchart starts at messy waveform and branches into hum, drift, saturation, and motion paths. Each branch lists short test nodes and pass/fail gates leading to a fix priority list. Measure in order: shorted input → body network → ΔZ sensitivity → cable A/B, then fix by dominant path Messy waveform Hum Drift Saturation Motion Shorted input Body network Shield A/B Shorted input ΔZ electrode Leakage node Headroom Recovery Clamp check Sway test Termination Guard / RLD Fix priority list PASS → next step FAIL → fix path
The flow keeps debugging deterministic: measure the baseline first, then isolate common-mode behavior, mismatch sensitivity, and finally cable coupling.

Engineering checklist: layout reviews + production-ready hooks

This section is a reusable SOP for bio-potential front ends: review layout by priority, add test hooks that make failures diagnosable, and define production checks that keep field behavior consistent (hum, drift, saturation recovery, motion sensitivity).

A) Layout review checklist (P0/P1/P2)

P0 — must-pass
Differential symmetry
Match series/protection/filter elements on both inputs (value + placement) to prevent CM→DM conversion.
Check: overlay both input paths; pass if element pairs are mirrored and matched.
Guard continuity for high-Z nodes
Guard sensitive nodes (inputs, bias nodes) with continuous guard structures and clean surfaces to control leakage-driven drift.
Check: continuity + reference correctness; pass if no guard breaks and no “floating guard” segments.
RLD / bias routing isolation
Keep the bias drive away from the input differential area and avoid unintended coupling loops that can inject mains.
Check: spatial separation + controlled return; pass if RLD does not traverse input-zone bottlenecks.
Analog/digital partition + return predictability
Prevent digital clocks and IO return currents from crossing the input/protection zone; keep the reference path continuous.
Check: current-return sketches; pass if digital returns never “share” a narrow path with high-Z measurement returns.
P1 — performance & repeatability
  • Parasitic balance: keep parasitic C and routing asymmetry low to reduce RF demodulation into the passband.
  • Reference/bias integrity: avoid long, shared, impedance-heavy routes that shift baselines with load or activity.
  • Connector-first mitigation: place the first-stage protection and symmetry elements close to the connector to avoid “antenna-on-board”.
P2 — maintenance & bring-up speed
  • Rework space: reserve land patterns for Riso/Cf/EMI parts so stability and immunity can be tuned without flying wires.
  • Access points: place test pads where clips do not disturb the input symmetry or guard strategy.
Review order: symmetry → guard/leakage control → RLD/bias routing → partition/returns → maintainability.

B) Test hooks (make failures diagnosable on the bench)

Short-in node
Purpose: isolate the front-end baseline (noise + hum residual). Place: right at the input pins, before any asymmetric routing.
CM inject node
Purpose: measure system CMRR and RLD effect using a controlled common-mode stimulus on a body/electrode network.
Lead-off inject / sense node
Purpose: validate lead-off false positives/negatives under realistic leakage and cable movement conditions.
RLD loop open point
Purpose: separate “loop/reference coupling” from “true CMRR limits” by comparing loop-closed vs loop-open behavior.
Rule: every hook must map to a measurable gate (pass/fail) and a first-fix action, otherwise it is not a production-ready hook.

C) Production-ready checks (keep field behavior consistent)

Offset / gain self-check
Use short-in and/or injection hooks to record baseline offset and a known gain point.
Pass criteria (template): offset < Offset_budget, gain error < Gain_budget.
Temperature drift audit
Sample units across temperature with a defined soak condition and capture drift metrics.
Pass criteria (template): drift < Drift_budget under the defined soak profile.
Cable sensitivity audit (touch/sway)
Use a scripted touch/sway motion and record hum increase, baseline steps, and spike rate.
Pass criteria (template): ΔHum < Hum_budget, ΔBaseline < Drift_budget, spikes/min < Spike_budget.

D) SOP gate template (copy/paste)

What to measure: (metric)
How to stimulate: (setup + action)
Pass criteria: (budget thresholds)
If fail, fix first: (dominant coupling path)
Diagram — Conceptual layout + test-point map (zones + hooks)
Conceptual PCB zones and test hooks for bio-potential AFE An abstract board layout shows input/protection, AFE core, isolation/interface, and ADC/digital zones. Test points mark short-in, CM inject, lead-off inject, and RLD open-loop access points. Concept map: zones + test hooks (keep input symmetry and guard intact) Input / Protection symmetry guard AFE Core RLD / bias recovery ADC / Digital IO & clocks return control Isolation / Interface (if used) TP: short TP: CM inj TP: lead-off TP: RLD open avoid shared returns
Keep hooks accessible without disturbing input symmetry and guard. Partition returns so the measurement reference is predictable under digital activity.

IC selection logic: fields → risk mapping → vendor questions

Selection must be field-driven. For bio-potential signals, the best part is the one that survives mains pickup, leakage, motion artifacts, and overload events under realistic wiring—not the one with the best single-number headline spec.

A) Required fields (evaluate with a 4-line template)

Noise: 0.1–10 Hz + wideband density
Why it matters: sets real resolution after bandwidth choices (EEG is LF-dominated; EMG is wideband-driven).
Field symptom: baseline wander, noisy microvolt features, sensitivity to filter corner changes.
Quick check: shorted-input PSD + 0.1–10 Hz p-p; Pass: within Noise_budget and LF_budget.
Input bias / leakage (system view)
Why it matters: leakage into high-Z electrode paths becomes input-referred offset and drift.
Field symptom: slow drift that changes with humidity, cleaning, or cable handling.
Quick check: substitute electrode network A/B (matched vs ΔZ); Pass: ΔDrift < ΔDrift_budget.
CMRR vs frequency (and mismatch sensitivity)
Why it matters: mains pickup is a system problem; mismatch and wiring can collapse “datasheet CMRR”.
Field symptom: persistent 50/60 Hz that does not respond to simple filtering.
Quick check: CM injection on body network; RLD on/off compare; Pass: hum residual < Hum_budget.
Input common-mode range / headroom
Why it matters: near-rail behavior can introduce nonlinearity and long recovery tails after disturbances.
Field symptom: clipping, slow return to baseline, or “stuck” behavior after lead motion/plug events.
Quick check: headroom sweep + overload event; Pass: recovery time < T_recover_budget.
Overload recovery (real-world immunity)
Why it matters: motion/plug/defib-protection events must not force long saturation or baseline corruption.
Field symptom: “flatline” after a transient, long settling, or repeated false triggers.
Quick check: step disturbance at input network; Pass: return-to-baseline < T_recover_budget.
RLD / lead-off interfaces
Why it matters: stable biasing and robust lead-off detection reduce field instability and misdiagnosis.
Field symptom: intermittent lead-off flags or hum increase when biasing is enabled.
Quick check: open-loop access + lead-off injection; Pass: stable waveform and acceptable false rate.
Keep numbers honest: evaluate each field with the same test conditions and the same budgets across candidates.

B) Risk mapping: symptom → dominant spec / design risk

Hum (50/60 Hz)
CMRR vs f + mismatch sensitivity + cable shielding + RLD coupling/stability.
Drift / baseline wander
0.1–10 Hz noise + leakage/bias current + electrode polarization sensitivity + guarding quality.
Saturation / long recovery
CM range/headroom + protection clamp behavior + overload recovery.
Motion spikes / touch sensitivity
cable coupling path + shield termination + input symmetry + recovery behavior.

C) Vendor questions (request comparable worst-case evidence)

Ask for test conditions, not only typical numbers. The goal is to compare candidates under the same measurement method and the same corner assumptions.
1) Provide 0.1–10 Hz p-p and noise density, including bandwidth and filtering used.
2) Provide CMRR vs frequency and specify the source impedance conditions (balanced vs unbalanced).
3) Provide overload recovery time after a defined input disturbance (amplitude + duration + clamp conditions).
4) Provide input bias/leakage worst-case versus temperature and supply.
5) Describe RLD / lead-off interfaces and whether open-loop access or stability guidance is available.

D) Bench verification (4-step gate before choosing)

  1. Shorted input: baseline noise + hum residual (gate to budgets).
  2. Body network: CM inject + RLD on/off effect (no instability; hum reduces to budget).
  3. ΔZ sensitivity: matched vs unbalanced electrode substitute (ΔHum/ΔDrift within budgets).
  4. Cable A/B: scripted touch/sway sensitivity (ΔHum/ΔBaseline/spikes within budgets).

E) Reference part numbers (starting points only)

These part numbers are provided to speed up datasheet lookup and bench planning. Final selection must pass the 4-step verification gates above.
Bucket 1 — ECG wearable / low-power AFE (high integration)
  • AD8232 — single-lead ECG front-end reference
  • AD8233 — biopotential front-end reference
  • MAX30003 — biopotential AFE reference
Bucket 2 — multi-electrode ECG AFE
  • ADAS1000-1 — 5-electrode ECG AFE reference
Bucket 3 — EEG / multi-channel biopotential ADC
  • ADS1299 / ADS1299-4 / ADS1299-6 — multi-channel 24-bit biopotential ADC reference
  • ADS1292R — 2-channel biopotential AFE/ADC reference
Bucket 4 — discrete INA front-end references (when not using an integrated AFE)
  • INA333 — zero-drift INA reference point
  • AD8421 — instrumentation amplifier reference point
Diagram — Selection flow: symptom → spec → bench test → decision
Selection flow for biopotential front ends A four-step flow shows Need, Spec, Verify, and Choose. Each step includes small chips: application class, key specs, bench gates, and decision criteria. Flow: Need → Spec → Verify → Choose (bench gates control risk) Need Spec Verify Choose ECG / EEG / EMG BW artifact Noise CMRR vs f Recovery Short Body net ΔZ + Cable A/B Pass Risk Evidence Gate to budgets hum / drift recovery touch / sway
Reference parts help start quickly, but budgets and bench gates decide. The winner is the candidate that stays stable under wiring realities and overload events.

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FAQs (ECG / EEG / EMG front ends)

These FAQs capture long-tail debug and design decisions without expanding the main body. Each answer uses the same 4-line, measurable structure: Likely cause → Quick check → Fix → Pass criteria.

Why does touching/moving the lead wire change the waveform?
Likely cause: Shield/ground reference shifts or triboelectric/microphonic coupling converts external E-field into differential error; leakage paths change with handling.
Quick check: Run a scripted touch/sway test; compare 50/60 Hz residual and spike rate with (a) inputs shorted at the connector and (b) the actual leads connected.
Fix: Use a defined shield termination strategy (single-point vs driven shield), improve strain relief, keep input RC/protection symmetric, and enforce guard/cleanliness around high-Z nodes.
Pass criteria: ΔHum < Hum_budget and spikes/min < Spike_rate_budget under the same scripted handling.
RLD makes the hum worse—what is the fastest stability check?
Likely cause: The RLD/bias loop is unstable or strongly coupled into the input path, turning “hum suppression” into “hum injection.”
Quick check: Open the RLD loop (or disable RLD) and compare hum residual; probe the RLD output for oscillation/ringing and excessive amplitude at 50/60 Hz.
Fix: Increase phase margin (limit loop bandwidth with Cf, add Riso, reduce loop gain), and reroute RLD away from high-Z input routing and sensitive nodes.
Pass criteria: With RLD enabled, hum residual decreases by ≥ Hum_improve_budget and no sustained oscillation is observed at the RLD output.
How to tell electrode mismatch from poor board CMRR on the bench?
Likely cause: Electrode impedance imbalance converts common-mode mains into differential error, or board-side asymmetry (protection/RC/layout) collapses system CMRR.
Quick check: (1) Short inputs at the connector to measure board baseline; (2) use a matched electrode substitute, then introduce a known ΔZ and repeat CM injection.
Fix: If ΔZ dominates, raise input impedance and improve bias return/guarding; if board dominates, match series R/RC parts and routing symmetry, and reduce asymmetric parasitics.
Pass criteria: CM injection residual meets Hum_budget with matched network; ΔHum due to the defined ΔZ stays within ΔZ_sensitivity_budget.
Why does mains notch create ringing or slow recovery after motion?
Likely cause: A high-Q notch (or poorly damped stage) interacts with overload recovery and output drive limits, creating time-domain ringing and long tails after motion artifacts.
Quick check: Compare step/motion-like disturbance response with notch enabled vs bypassed; measure overshoot and time-to-baseline (same gain and bandwidth).
Fix: Reduce notch Q or add damping (series R), move the notch to digital, ensure the analog stage is stable under the load (Riso for capacitive loads), and avoid placing a sharp notch in an overload-prone node.
Pass criteria: Recovery time < T_recover_budget and overshoot < Overshoot_budget while notch depth ≥ Notch_depth_budget.
What bias resistor range keeps input CM stable without raising leakage risk?
Likely cause: Bias return too weak lets inputs float (CM drifts to rails); bias too strong increases leakage/current risk and makes offsets more sensitive to leakage and contamination.
Quick check: Sweep Rbias on a body/electrode substitute; log input CM trajectory, rail hits, and DC offset changes across humidity/cleanliness A/B.
Fix: Choose a symmetric Rbias that centers CM with margin, minimize leakage paths (guard + cleaning + low-leak components), and keep protection/RC symmetrical so bias does not create differential error.
Pass criteria: CM stays within CM_window_budget with zero rail hits; leakage-induced offset < Offset_leak_budget.
Lead-off detection causes spikes—where is the coupling path?
Likely cause: Lead-off injection couples into the measurement band through input RC asymmetry, protection clamp dynamics, ADC sampling charge kickback, or RLD/bias coupling.
Quick check: Disable lead-off and measure spike-rate change; then shift injection frequency and look for correlation between injection edges and output spikes.
Fix: Balance injection paths, slow edges with a small RC, add sampling blanking/synchronization, and improve guard/shield separation so injection does not modulate high-Z nodes.
Pass criteria: Spike_rate < Spike_rate_budget and lead-off false rate < LeadOff_false_budget under the standard cable motion test.
Why does the baseline wander for minutes after power-up?
Likely cause: Electrode polarization settling, dielectric absorption in input capacitors, long bias-return time constants, or leakage stabilization after power-up.
Quick check: Compare warm-up drift with (a) inputs shorted, (b) matched substitute network, and (c) real electrodes; log baseline vs time and humidity.
Fix: Ensure a stable bias return, reduce leakage (guard + cleanliness + low-leak parts), choose low-DA capacitors, and sequence RLD enable after the bias settles when applicable.
Pass criteria: Baseline reaches steady state within T_warmup_budget and drift rate < Drift_budget afterward.
Chopper ripple appears as a tone—how to filter without losing EEG content?
Likely cause: Modulation/chopper ripple leaks into the signal band or aliases into the EEG band due to sampling/anti-alias filter placement.
Quick check: Measure PSD; confirm the tone tracks the modulation/chop frequency (or its alias). Compare spectra with configuration changes that shift the tone or reduce modulation gain.
Fix: Attenuate the tone with a properly placed LPF before the ADC, add a narrow digital notch at the tone (outside critical EEG content), and avoid sampling choices that fold the tone into the EEG band.
Pass criteria: Tone amplitude in EEG band < Spur_budget while in-band flatness stays within Band_flat_budget.
EMG saturates during fast muscle bursts—gain vs headroom plan?
Likely cause: Gain is too high for burst amplitude and/or common-mode/headroom limits are violated, pushing the front end or ADC into clipping.
Quick check: Count clipping events and measure peak-to-full-scale margin during bursts; observe CM and output swing during the same events.
Fix: Reduce gain or distribute gain across stages, re-center bias away from rails, increase supply/headroom when possible, and ensure filters do not ring into clipping.
Pass criteria: Clip events/min < Clip_rate_budget, margin > Headroom_budget, and recovery < T_recover_budget.
Why does the signal clip near rails even when “RRI/RRO” is claimed?
Likely cause: Rail-to-rail behavior is conditional (load, gain, CM, temperature), and near-rail nonlinearity or capacitive-load instability can trigger early clipping.
Quick check: Sweep CM and output load; repeat with capacitive load removed; compare the observed clip point against datasheet test conditions.
Fix: Re-center bias/reference away from rails, add output isolation (Riso) for capacitive loads, and select a device with guaranteed swing under the required load and CM window.
Pass criteria: No clipping within CM_window_budget and output swing margin > Headroom_budget under the actual load.
How to set anti-alias LPF so EMG noise doesn’t fold into band?
Likely cause: LPF corner/stopband attenuation is insufficient relative to sampling rate, so wideband noise folds into the EMG band.
Quick check: Measure in-band RMS with LPF in/out; inspect out-of-band noise near Nyquist; vary sampling rate to confirm folding behavior.
Fix: Lower LPF corner, increase filter order/stopband attenuation, raise sampling rate, and place prefiltering before any stage that could saturate.
Pass criteria: Folded noise contribution < Folded_noise_budget and in-band RMS meets Noise_budget without added ringing (settling < T_settle_budget).
After ESD/defib event, readings drift—what quick checks isolate the damaged part?
Likely cause: Protection chain damage increases leakage or shifts bias components, creating a new offset/drift path (sometimes ADC input leakage also changes).
Quick check: Measure DC leakage at staged nodes; compare baseline with a matched substitute network; A/B isolate protection segments (where safe) to localize the leakage increase.
Fix: Replace the suspected TVS/clamp/series resistor stage; redesign staged protection to reduce stress and leakage sensitivity; add a production leakage-screen test.
Pass criteria: Leakage < Leakage_budget and offset/drift return within Offset_budget/Drift_budget while hum and recovery gates still pass.
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