What this front-end must guarantee

• Signal integrity: the differential reading must stay stable when cables move, grounds shift, and EMI exists.
• Low-frequency fidelity: offset/drift/1-f noise and leakage must not masquerade as temperature change.
• Common-mode survival: common-mode steps and ground offsets must not saturate the measurement chain.
• Production repeatability: calibration hooks and pass criteria must translate to lot-to-lot consistency.

Two measurement lanes (engineering abstraction)

Scope control (prevents cross-page overlap)

The three dominant error injection points (field reality)

Place protection/filtering inside the accuracy budget (not as an afterthought)

What is measured (engineering abstraction)

• Signal scale: thermocouple sensitivity is typically in the µV/°C range, so small electrical or thermal artifacts can look like real temperature change.
• Two junctions matter: the “cold junction” is the metal transition at the terminal/connector where thermocouple alloy meets copper.
• Absolute temperature requires CJC: without CJC, the result is only a temperature difference; with incorrect CJC, slow drift can mimic true sensor behavior.

Dominant error owners (what usually limits accuracy)

Minimum verification hooks (fast isolation of root cause)

1. Short at terminal: short the differential input at the connector to establish the low-frequency drift/noise baseline of the electronics.
2. Cable-only test: connect real cables but short at the far end; observe sensitivity to motion/touch (wiring pickup and shield termination issues).
3. CJC disturbance: apply a controlled thermal disturbance near the terminal region and verify recovery and gradient sensitivity.

Placement rules (do this first)

• Thermal coupling: place the CJC sensor adjacent to the terminal transition region so it tracks the real cold junction.
• Thermal isolation: use isolation slots/keep-outs to prevent remote heat sources from “warming the CJC” through copper spread.
• Heat-source distance: keep regulators, inductors, and high-power devices away from the terminal/CJC zone.
• Symmetry: balance copper and mechanical features around the terminal area to reduce lateral gradients.
• Cleanliness: keep high-impedance junction nodes away from contamination paths that can couple heat and leakage together.

Common traps (how “fake cold-junction” happens)

• Airflow sensitivity: local cooling/heating near the terminal changes the cold-junction region faster than the rest of the board.
• Terminal thermal resistance: the metal terminal can lag the CJC sensor unless the thermal path is intentional and short.
• Board hot spots: switching or load bursts warm nearby copper and bias the CJC reading upward.
• Copper heat short: large copper pours can import heat from remote zones, breaking the assumption that CJC equals terminal temperature.
• Asymmetric layout: uneven copper/planes across the terminal area creates gradients that look like slow drift.

Algorithm hooks (keep it engineering-simple)

• Linearization: use segmented approximation or lookup tables sized to the required accuracy, not to theoretical perfection.
• Calibration table: separate “electronics offset/gain” from “CJC placement bias” by running calibration with controlled thermal conditions.
• Sanity checks: flag implausible cold-junction rate-of-change (airflow or hot-spot events) before it contaminates the temperature estimate.

Verification methods (repeatable) + pass criteria (budget-driven)

One unified model (why wiring dominates)

• Measured quantity: voltage at the sense nodes reflects RTD + contact + lead unless the topology separates them.
• Lead resistance: changes with cable length, gauge, connectors, and cable temperature, so it creates drift-like behavior.
• Topology goal: push lead resistance out of the dominant error path or constrain its residual to a predictable bound.

What each topology cancels (and what it cannot)

Selection guidance (quick decision fields)

• Cable length: short → 2-wire; medium → 3-wire if matching holds; long → 4-wire.
• Cable temperature gradients: small → 3-wire may hold; large or variable → 4-wire strongly preferred.
• Accuracy target: low → 2-wire; medium → 3-wire; high → 4-wire (Kelvin).
• System constraints: cost and channel count favor 3-wire; calibration and field robustness favor 4-wire.

Verification hooks (fast checks that reveal lead dominance)

1. Known resistor at the sensor end: substitute a stable resistor and vary cable length/type; observe how much the reading moves.
2. Lead swap (3-wire): swap the two “matched” leads and measure change; large delta indicates mismatch sensitivity.
3. Cable temperature disturbance: heat/cool a cable segment; residual drift indicates lead-temperature coupling into the measurement.

Constant current vs constant voltage (error shapes)

Ratiometric measurement (make drift cancel)

• Principle: drive the RTD with a stimulus and feed the ADC reference from the same drift source so the final ratio rejects slow drift.
• Practical hook: route the reference path like a measurement path (short, quiet, and consistent filtering) to avoid creating a new error owner.
• Observable win: changes in supply or stimulus that previously moved readings become largely invisible in the final output.

Self-heating control (engineering method, not long math)

• Owner: RTD power dissipation drives local temperature rise; higher stimulus increases bias error and changes dynamics.
• Sequencing: measure at a consistent time after excitation to avoid “thermal settling” being mistaken for drift.
• Budget placeholder: choose stimulus so equivalent self-heating error stays below ΔT_{self_allow} for the application.

Switched excitation / duty cycle (multi-channel friendly) + verification

Two lanes (what sets the gain target)

INA selection fields (field → risk → what to verify)

• Vos & drift: directly map into temperature error for TC; confirm baseline stability over ambient steps.
• 0.1–10 Hz noise / 1/f corner: sets low-frequency resolution; validate by logging and confirming noise stays below the target band.
• Input bias & leakage sensitivity: series resistors, clamps, and contamination convert leakage into offsets; verify with input short/open tests and temperature sweeps.
• Input CM range: long-lead ground shifts and grounded junctions can push common-mode; verify no clipping near rails.
• Output swing & drive: ensure headroom into RC/ADC loads; verify settling and no saturation during transients.
• Overload recovery: cable touch, ESD, or mains pickup can overload the input; verify recovery time stays below T_rec.
• Zero-drift ripple / modulation: may create artifacts if not filtered or if sampled poorly; verify “no spur / no step” under quiet conditions.

When PGA helps (and how to keep gain switching stable)

Minimum verification (fast checks)

1. Input short baseline: confirm offset/noise meets the low-frequency target.
2. Ambient step: apply a controlled board ambient change and confirm drift stays within budget.
3. Overload & recovery: inject a disturbance (mains pickup / cable touch) and confirm recovery < T_rec.
4. PGA step test: switch gain, wait T_{set_G}, confirm no lingering step beyond ΔT_{step_allow}.

Differential RC vs common-mode RC (what each targets)

• Differential RC: attenuates differential spikes and broadband noise; preserves symmetry when components match well.
• Common-mode RC: shunts high-frequency common-mode energy; often more effective for RFI on long cables.
• Mains pickup: commonly driven by coupling and ground shifts; filtering helps but cannot replace sound grounding and topology choices.

Protection side effects (leakage → bias → drift-shaped error)

• Clamps / TVS can exhibit temperature-dependent leakage that creates a DC bias at high-impedance nodes.
• Series resistors limit surge current, but leakage across protection devices can develop a voltage across the series network.
• TC impact: µV-level offsets translate directly into temperature error; “slow drift” is often leakage + thermal gradients.
• RTD impact: leakage can shift sensed voltage or reference nodes and mimic long-term drift unless ratiometric structure constrains it.

Measurable pass criteria (TC/RTD-specific)

1. Mains rejection: applied 50/60 Hz disturbance produces < ΔT_{mains_allow} equivalent change.
2. Cable touch / movement: touching or moving the cable causes no step above ΔT_{touch_allow}.
3. RFI injection: near-field RF disturbance causes no sustained offset beyond ΔT_{RFI_allow}.

Staged input network (keep error owners visible)

• Terminal → series R: define a controlled surge/ESD current limit and isolate cable capacitance from the front-end.
• RC layer: apply symmetric differential filtering, then common-mode shunt for RF energy.
• Clamp layer: place clamps to protect while keeping leakage from dominating the sensing nodes.
• Audit mindset: every protection element must have an explicit leakage budget V_{leak_allow} and a temperature sweep check.

Two common ADC modes (what to prioritize in low-frequency sensing)

Anti-alias intent (for TC/RTD low-frequency accuracy)

• Stability first: verify no oscillation or edge-case instability when driving the ADC input network.
• Alias control: high-frequency RFI can fold into DC and look like drift; filtering must reduce RF energy before sampling.
• No new drift: leakage, dielectric absorption, and charge injection in the interface network must be bounded with temperature sweeps and “no-step” criteria.

Minimal verification (fast, repeatable)

1. Mains injection: apply 50/60 Hz disturbance; confirm equivalent change < ΔT_{mains_allow}.
2. Rate sweep: sweep sampling rate; confirm DC reading stays within ΔT_{rate_allow} (SAR-sensitive).
3. Input-network sweep: change R/C values around the interface; confirm no new step/long tail above E_{tail_allow}.
4. RFI susceptibility: near-field RF disturbance causes no sustained offset beyond ΔT_{RFI_allow}.

Budget philosophy (owner-driven)

• Find the top-3: do a quick worst-case estimate to identify dominant terms before optimizing everything.
• Assign ownership: every error term must belong to a block (Sensor / CJC / INA / ADC / PCB / Excitation / FW).
• Verify and iterate: define a repeatable test, measure distributions, then decide calibration or topology changes.

Fixed-header error table (fill with measurements)

Tip: keep the placeholders (ΔT_allow, V_leak_allow, T_response_allow) until measurements fill real distributions and worst-case bounds.

Calibration ladder (use the lightest step that meets the budget)

Guardrail: LUT is justified only when coefficient stability is proven and stimulus uncertainty is well below ΔT_total_allow.

Thermocouple linearization must be validated with CJC (not separately)

• Coupled validation: linearization and cold-junction behavior are inseparable in low-frequency accuracy tests.
• Gradient stress: local airflow/heat on the terminal area must not produce slow “tail” offsets beyond E_tail_allow.
• Repeatability: the same stimulus under the same fixture must reproduce within ΔT_repeat_allow across units.

RTD production detection: exposing 3-wire residual (mismatch & contact resistance)

Self-test hooks (factory mode): inject → read back → decide

• TC path: controlled microvolt-level injection validates offset, drift sensitivity, and recovery tails.
• RTD path: controlled resistor/current injection validates ratiometric chain and 3-wire residual behavior.
• Decision: pass/fail uses compact criteria (gain, offset, settling time), not just a single reading.

Minimal factory flow (fast, scalable)

1. Baseline: input short → record offset + 0.1–10 Hz noise baseline.
2. Injection #1: low-level step → verify settling tail < E_tail_allow.
3. Injection #2: second point → verify gain consistency < E_gain_allow.
4. RTD residual: lead swap / Rinj → verify ΔT_lead_allow and repeatability.
5. Log: store only key pass fields (offset, gain, settling, residual), not a database schema.

What NOT to “fix” with calibration (structural issues)

• Leakage/contamination drift: cleaning and protection leakage control are required; LUT cannot stabilize it.
• CJC thermal gradient: placement/thermal isolation is the fix; calibration only masks and will reappear in the field.
• SAR settling/alias artifacts: interface network and sampling plan must be corrected first.

Thermocouple checklist (thermal path first)

1. Terminal ↔ CJC thermal coupling: ensure CJC tracks terminal temperature; avoid copper “heat bridges” to warm areas.
2. Thermal isolation: keep power devices and hot regulators away; add a thermal slot / keepout near terminal zone.
3. Symmetry: keep copper and components symmetric around the input pair to prevent board-generated thermoelectric offsets.
4. Airflow sensitivity: confirm airflow changes do not shift reading beyond ΔT_air_allow.

RTD checklist (Kelvin & excitation loop discipline)

1. Kelvin routing: sense lines must not carry excitation current; keep sense high-impedance and protected.
2. 3-wire assumption: if 3-wire is used, match lead geometry and connector contacts as if they are components.
3. Excitation return path: define a clean current loop; prevent excitation return from sharing bottlenecks with digital return.
4. Connector contact resistance: detect by pressing/moving connector; |ΔT| < ΔT_contact_allow.

Leakage checklist (the hidden low-frequency failure mode)

• Cleanliness: flux residues and moisture can create temperature-dependent leakage that looks like drift.
• Protection leakage: clamp/ESD parts can leak more at high temperature; treat leakage as a budget line item.
• Guard ring: apply only for high-impedance nodes where leakage maps directly into bias-like error.

Bring-up: what to measure first (fast root-cause isolation)